Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8493865 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
129687 |
| auto[1] |
6269823 |
1 |
|
|
T24 |
146100 |
|
T25 |
30949 |
|
T1 |
48952 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13958597 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
257800 |
| auto[1] |
805091 |
1 |
|
|
T24 |
17987 |
|
T25 |
4343 |
|
T1 |
5358 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8521380 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
143154 |
| auto[1] |
6242308 |
1 |
|
|
T24 |
132633 |
|
T25 |
31232 |
|
T1 |
49285 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2723790 |
1 |
|
|
T24 |
53807 |
|
T25 |
13073 |
|
T1 |
21579 |
| auto[1] |
auto[0] |
auto[1] |
403389 |
1 |
|
|
T24 |
8309 |
|
T25 |
2118 |
|
T1 |
2641 |
| auto[1] |
auto[1] |
auto[0] |
2713427 |
1 |
|
|
T24 |
60839 |
|
T25 |
13816 |
|
T1 |
22348 |
| auto[1] |
auto[1] |
auto[1] |
401702 |
1 |
|
|
T24 |
9678 |
|
T25 |
2225 |
|
T1 |
2717 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |