Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8539314 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
139428 |
| auto[1] |
6224374 |
1 |
|
|
T24 |
136359 |
|
T25 |
28859 |
|
T1 |
47100 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13957907 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
256209 |
| auto[1] |
805781 |
1 |
|
|
T24 |
19578 |
|
T25 |
4295 |
|
T1 |
4742 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8529697 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
133943 |
| auto[1] |
6233991 |
1 |
|
|
T24 |
141844 |
|
T25 |
31431 |
|
T1 |
46265 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2730252 |
1 |
|
|
T24 |
60771 |
|
T25 |
14301 |
|
T1 |
21665 |
| auto[1] |
auto[0] |
auto[1] |
405337 |
1 |
|
|
T24 |
9840 |
|
T25 |
2202 |
|
T1 |
2561 |
| auto[1] |
auto[1] |
auto[0] |
2697958 |
1 |
|
|
T24 |
61495 |
|
T25 |
12835 |
|
T1 |
19858 |
| auto[1] |
auto[1] |
auto[1] |
400444 |
1 |
|
|
T24 |
9738 |
|
T25 |
2093 |
|
T1 |
2181 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |