Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8536634 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
136891 |
| auto[1] |
6227054 |
1 |
|
|
T24 |
138896 |
|
T25 |
31909 |
|
T1 |
48972 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13951644 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
257236 |
| auto[1] |
812044 |
1 |
|
|
T24 |
18551 |
|
T25 |
4074 |
|
T1 |
5205 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8484020 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
139545 |
| auto[1] |
6279668 |
1 |
|
|
T24 |
136242 |
|
T25 |
29950 |
|
T1 |
48504 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2744708 |
1 |
|
|
T24 |
58810 |
|
T25 |
13070 |
|
T1 |
21854 |
| auto[1] |
auto[0] |
auto[1] |
407435 |
1 |
|
|
T24 |
9194 |
|
T25 |
2077 |
|
T1 |
2648 |
| auto[1] |
auto[1] |
auto[0] |
2722916 |
1 |
|
|
T24 |
58881 |
|
T25 |
12806 |
|
T1 |
21445 |
| auto[1] |
auto[1] |
auto[1] |
404609 |
1 |
|
|
T24 |
9357 |
|
T25 |
1997 |
|
T1 |
2557 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |