Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8519950 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
138211 |
auto[1] |
6243738 |
1 |
|
|
T24 |
137576 |
|
T25 |
32045 |
|
T1 |
48846 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12180047 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
221218 |
auto[1] |
2583641 |
1 |
|
|
T24 |
54569 |
|
T25 |
17512 |
|
T1 |
31120 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8522596 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
139106 |
auto[1] |
6241092 |
1 |
|
|
T24 |
136681 |
|
T25 |
30046 |
|
T1 |
47276 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1817838 |
1 |
|
|
T24 |
42083 |
|
T25 |
5857 |
|
T1 |
7951 |
auto[1] |
auto[0] |
auto[1] |
1287384 |
1 |
|
|
T24 |
28152 |
|
T25 |
8152 |
|
T1 |
15512 |
auto[1] |
auto[1] |
auto[0] |
1839613 |
1 |
|
|
T24 |
40029 |
|
T25 |
6677 |
|
T1 |
8205 |
auto[1] |
auto[1] |
auto[1] |
1296257 |
1 |
|
|
T24 |
26417 |
|
T25 |
9360 |
|
T1 |
15608 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |