Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8519541 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
133324 |
auto[1] |
6244147 |
1 |
|
|
T24 |
142463 |
|
T25 |
31536 |
|
T1 |
48736 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12183491 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
222357 |
auto[1] |
2580197 |
1 |
|
|
T24 |
53430 |
|
T25 |
18178 |
|
T1 |
30763 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8538727 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
142024 |
auto[1] |
6224961 |
1 |
|
|
T24 |
133763 |
|
T25 |
30925 |
|
T1 |
47284 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1826045 |
1 |
|
|
T24 |
37559 |
|
T25 |
6200 |
|
T1 |
8170 |
auto[1] |
auto[0] |
auto[1] |
1291020 |
1 |
|
|
T24 |
26079 |
|
T25 |
8659 |
|
T1 |
15145 |
auto[1] |
auto[1] |
auto[0] |
1818719 |
1 |
|
|
T24 |
42774 |
|
T25 |
6547 |
|
T1 |
8351 |
auto[1] |
auto[1] |
auto[1] |
1289177 |
1 |
|
|
T24 |
27351 |
|
T25 |
9519 |
|
T1 |
15618 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |