Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13953709 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
256920 |
| auto[1] |
809979 |
1 |
|
|
T24 |
18867 |
|
T25 |
4666 |
|
T1 |
5195 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8509899 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
138311 |
| auto[1] |
6253789 |
1 |
|
|
T24 |
137476 |
|
T25 |
33717 |
|
T1 |
48464 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2731523 |
1 |
|
|
T24 |
57497 |
|
T25 |
15021 |
|
T1 |
20966 |
| auto[1] |
auto[0] |
auto[1] |
406587 |
1 |
|
|
T24 |
9062 |
|
T25 |
2356 |
|
T1 |
2437 |
| auto[1] |
auto[1] |
auto[0] |
2712287 |
1 |
|
|
T24 |
61112 |
|
T25 |
14030 |
|
T1 |
22303 |
| auto[1] |
auto[1] |
auto[1] |
403392 |
1 |
|
|
T24 |
9805 |
|
T25 |
2310 |
|
T1 |
2758 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |