Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8522934 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
136279 |
auto[1] |
6240754 |
1 |
|
|
T24 |
139508 |
|
T25 |
31260 |
|
T1 |
47943 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12180170 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
222075 |
auto[1] |
2583518 |
1 |
|
|
T24 |
53712 |
|
T25 |
17435 |
|
T1 |
31485 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8513995 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
141105 |
auto[1] |
6249693 |
1 |
|
|
T24 |
134682 |
|
T25 |
29578 |
|
T1 |
48145 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1832502 |
1 |
|
|
T24 |
40193 |
|
T25 |
6034 |
|
T1 |
8377 |
auto[1] |
auto[0] |
auto[1] |
1292724 |
1 |
|
|
T24 |
26338 |
|
T25 |
8705 |
|
T1 |
16008 |
auto[1] |
auto[1] |
auto[0] |
1833673 |
1 |
|
|
T24 |
40777 |
|
T25 |
6109 |
|
T1 |
8283 |
auto[1] |
auto[1] |
auto[1] |
1290794 |
1 |
|
|
T24 |
27374 |
|
T25 |
8730 |
|
T1 |
15477 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |