Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8537589 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
139833 |
auto[1] |
6226099 |
1 |
|
|
T24 |
135954 |
|
T25 |
30434 |
|
T1 |
47234 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12175264 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
221706 |
auto[1] |
2588424 |
1 |
|
|
T24 |
54081 |
|
T25 |
18751 |
|
T1 |
30822 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8499806 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
138594 |
auto[1] |
6263882 |
1 |
|
|
T24 |
137193 |
|
T25 |
31771 |
|
T1 |
47391 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1835451 |
1 |
|
|
T24 |
40575 |
|
T25 |
6766 |
|
T1 |
8402 |
auto[1] |
auto[0] |
auto[1] |
1295570 |
1 |
|
|
T24 |
26696 |
|
T25 |
9794 |
|
T1 |
15762 |
auto[1] |
auto[1] |
auto[0] |
1840007 |
1 |
|
|
T24 |
42537 |
|
T25 |
6254 |
|
T1 |
8167 |
auto[1] |
auto[1] |
auto[1] |
1292854 |
1 |
|
|
T24 |
27385 |
|
T25 |
8957 |
|
T1 |
15060 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |