Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8525066 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
136023 |
auto[1] |
6238622 |
1 |
|
|
T24 |
139764 |
|
T25 |
31168 |
|
T1 |
46104 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13962003 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
256867 |
auto[1] |
801685 |
1 |
|
|
T24 |
18920 |
|
T25 |
4281 |
|
T1 |
4815 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8549599 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
137517 |
auto[1] |
6214089 |
1 |
|
|
T24 |
138270 |
|
T25 |
30760 |
|
T1 |
44993 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2716628 |
1 |
|
|
T24 |
58472 |
|
T25 |
12932 |
|
T1 |
21049 |
auto[1] |
auto[0] |
auto[1] |
402170 |
1 |
|
|
T24 |
9334 |
|
T25 |
2138 |
|
T1 |
2572 |
auto[1] |
auto[1] |
auto[0] |
2695776 |
1 |
|
|
T24 |
60878 |
|
T25 |
13547 |
|
T1 |
19129 |
auto[1] |
auto[1] |
auto[1] |
399515 |
1 |
|
|
T24 |
9586 |
|
T25 |
2143 |
|
T1 |
2243 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |