Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8523973 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
139311 |
auto[1] |
6239715 |
1 |
|
|
T24 |
136476 |
|
T25 |
32808 |
|
T1 |
48846 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12190178 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
220709 |
auto[1] |
2573510 |
1 |
|
|
T24 |
55078 |
|
T25 |
18138 |
|
T1 |
31685 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8541224 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
135028 |
auto[1] |
6222464 |
1 |
|
|
T24 |
140759 |
|
T25 |
31051 |
|
T1 |
48104 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1829685 |
1 |
|
|
T24 |
43813 |
|
T25 |
6085 |
|
T1 |
7898 |
auto[1] |
auto[0] |
auto[1] |
1287181 |
1 |
|
|
T24 |
27912 |
|
T25 |
8512 |
|
T1 |
15324 |
auto[1] |
auto[1] |
auto[0] |
1819269 |
1 |
|
|
T24 |
41868 |
|
T25 |
6828 |
|
T1 |
8521 |
auto[1] |
auto[1] |
auto[1] |
1286329 |
1 |
|
|
T24 |
27166 |
|
T25 |
9626 |
|
T1 |
16361 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |