Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8497906 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
138111 |
auto[1] |
6265782 |
1 |
|
|
T24 |
137676 |
|
T25 |
29662 |
|
T1 |
45271 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12193192 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
221460 |
auto[1] |
2570496 |
1 |
|
|
T24 |
54327 |
|
T25 |
18327 |
|
T1 |
31205 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8555119 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
136480 |
auto[1] |
6208569 |
1 |
|
|
T24 |
139307 |
|
T25 |
31523 |
|
T1 |
47838 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1821098 |
1 |
|
|
T24 |
42557 |
|
T25 |
6977 |
|
T1 |
9008 |
auto[1] |
auto[0] |
auto[1] |
1289138 |
1 |
|
|
T24 |
26935 |
|
T25 |
9543 |
|
T1 |
17137 |
auto[1] |
auto[1] |
auto[0] |
1816975 |
1 |
|
|
T24 |
42423 |
|
T25 |
6219 |
|
T1 |
7625 |
auto[1] |
auto[1] |
auto[1] |
1281358 |
1 |
|
|
T24 |
27392 |
|
T25 |
8784 |
|
T1 |
14068 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |