Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8512103 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
134682 |
| auto[1] |
6251585 |
1 |
|
|
T24 |
141105 |
|
T25 |
32274 |
|
T1 |
47162 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13958630 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
257501 |
| auto[1] |
805058 |
1 |
|
|
T24 |
18286 |
|
T25 |
4327 |
|
T1 |
4986 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8526137 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
140279 |
| auto[1] |
6237551 |
1 |
|
|
T24 |
135508 |
|
T25 |
31525 |
|
T1 |
48039 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2699691 |
1 |
|
|
T24 |
59266 |
|
T25 |
13148 |
|
T1 |
22538 |
| auto[1] |
auto[0] |
auto[1] |
399713 |
1 |
|
|
T24 |
8998 |
|
T25 |
2092 |
|
T1 |
2726 |
| auto[1] |
auto[1] |
auto[0] |
2732802 |
1 |
|
|
T24 |
57956 |
|
T25 |
14050 |
|
T1 |
20515 |
| auto[1] |
auto[1] |
auto[1] |
405345 |
1 |
|
|
T24 |
9288 |
|
T25 |
2235 |
|
T1 |
2260 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |