Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8526851 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
137754 |
| auto[1] |
6236837 |
1 |
|
|
T24 |
138033 |
|
T25 |
30766 |
|
T1 |
47765 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13955382 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
255878 |
| auto[1] |
808306 |
1 |
|
|
T24 |
19909 |
|
T25 |
4576 |
|
T1 |
4711 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8504351 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
131763 |
| auto[1] |
6259337 |
1 |
|
|
T24 |
144024 |
|
T25 |
33309 |
|
T1 |
44333 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2721456 |
1 |
|
|
T24 |
61478 |
|
T25 |
15003 |
|
T1 |
19686 |
| auto[1] |
auto[0] |
auto[1] |
403907 |
1 |
|
|
T24 |
9936 |
|
T25 |
2429 |
|
T1 |
2344 |
| auto[1] |
auto[1] |
auto[0] |
2729575 |
1 |
|
|
T24 |
62637 |
|
T25 |
13730 |
|
T1 |
19936 |
| auto[1] |
auto[1] |
auto[1] |
404399 |
1 |
|
|
T24 |
9973 |
|
T25 |
2147 |
|
T1 |
2367 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |