Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8493383 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
139337 |
auto[1] |
6270305 |
1 |
|
|
T24 |
136450 |
|
T25 |
29038 |
|
T1 |
47116 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13960616 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
257265 |
auto[1] |
803072 |
1 |
|
|
T24 |
18522 |
|
T25 |
4194 |
|
T1 |
4865 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8540567 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
141100 |
auto[1] |
6223121 |
1 |
|
|
T24 |
134687 |
|
T25 |
30568 |
|
T1 |
46187 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2698078 |
1 |
|
|
T24 |
57394 |
|
T25 |
15223 |
|
T1 |
19708 |
auto[1] |
auto[0] |
auto[1] |
399139 |
1 |
|
|
T24 |
9255 |
|
T25 |
2424 |
|
T1 |
2160 |
auto[1] |
auto[1] |
auto[0] |
2721971 |
1 |
|
|
T24 |
58771 |
|
T25 |
11151 |
|
T1 |
21614 |
auto[1] |
auto[1] |
auto[1] |
403933 |
1 |
|
|
T24 |
9267 |
|
T25 |
1770 |
|
T1 |
2705 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |