Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8511297 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
139982 |
| auto[1] |
6252391 |
1 |
|
|
T24 |
135805 |
|
T25 |
30654 |
|
T1 |
47557 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13955534 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
256606 |
| auto[1] |
808154 |
1 |
|
|
T24 |
19181 |
|
T25 |
4184 |
|
T1 |
5136 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8504174 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
137500 |
| auto[1] |
6259514 |
1 |
|
|
T24 |
138287 |
|
T25 |
30550 |
|
T1 |
47924 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2728033 |
1 |
|
|
T24 |
61424 |
|
T25 |
13272 |
|
T1 |
21304 |
| auto[1] |
auto[0] |
auto[1] |
402845 |
1 |
|
|
T24 |
10030 |
|
T25 |
2066 |
|
T1 |
2512 |
| auto[1] |
auto[1] |
auto[0] |
2723327 |
1 |
|
|
T24 |
57682 |
|
T25 |
13094 |
|
T1 |
21484 |
| auto[1] |
auto[1] |
auto[1] |
405309 |
1 |
|
|
T24 |
9151 |
|
T25 |
2118 |
|
T1 |
2624 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |