Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8543999 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
137729 |
auto[1] |
6219689 |
1 |
|
|
T24 |
138058 |
|
T25 |
30459 |
|
T1 |
47283 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13958680 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
257615 |
auto[1] |
805008 |
1 |
|
|
T24 |
18172 |
|
T25 |
4393 |
|
T1 |
5024 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8525915 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
143318 |
auto[1] |
6237773 |
1 |
|
|
T24 |
132469 |
|
T25 |
31285 |
|
T1 |
47045 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2725294 |
1 |
|
|
T24 |
57688 |
|
T25 |
13390 |
|
T1 |
21105 |
auto[1] |
auto[0] |
auto[1] |
403451 |
1 |
|
|
T24 |
9260 |
|
T25 |
2153 |
|
T1 |
2523 |
auto[1] |
auto[1] |
auto[0] |
2707471 |
1 |
|
|
T24 |
56609 |
|
T25 |
13502 |
|
T1 |
20916 |
auto[1] |
auto[1] |
auto[1] |
401557 |
1 |
|
|
T24 |
8912 |
|
T25 |
2240 |
|
T1 |
2501 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8500902 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
132823 |
auto[1] |
6262786 |
1 |
|
|
T24 |
142964 |
|
T25 |
29855 |
|
T1 |
48076 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13958891 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
257179 |
auto[1] |
804797 |
1 |
|
|
T24 |
18608 |
|
T25 |
4116 |
|
T1 |
4933 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8525014 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
138823 |
auto[1] |
6238674 |
1 |
|
|
T24 |
136964 |
|
T25 |
29902 |
|
T1 |
46460 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2708001 |
1 |
|
|
T24 |
56816 |
|
T25 |
13482 |
|
T1 |
21130 |
auto[1] |
auto[0] |
auto[1] |
400948 |
1 |
|
|
T24 |
8981 |
|
T25 |
2143 |
|
T1 |
2540 |
auto[1] |
auto[1] |
auto[0] |
2725876 |
1 |
|
|
T24 |
61540 |
|
T25 |
12304 |
|
T1 |
20397 |
auto[1] |
auto[1] |
auto[1] |
403849 |
1 |
|
|
T24 |
9627 |
|
T25 |
1973 |
|
T1 |
2393 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8523973 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
139311 |
auto[1] |
6239715 |
1 |
|
|
T24 |
136476 |
|
T25 |
32808 |
|
T1 |
48846 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13953296 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
256565 |
auto[1] |
810392 |
1 |
|
|
T24 |
19222 |
|
T25 |
4224 |
|
T1 |
5040 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8495758 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
136066 |
auto[1] |
6267930 |
1 |
|
|
T24 |
139721 |
|
T25 |
30454 |
|
T1 |
46881 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2740100 |
1 |
|
|
T24 |
62543 |
|
T25 |
12795 |
|
T1 |
20649 |
auto[1] |
auto[0] |
auto[1] |
407512 |
1 |
|
|
T24 |
9922 |
|
T25 |
2069 |
|
T1 |
2476 |
auto[1] |
auto[1] |
auto[0] |
2717438 |
1 |
|
|
T24 |
57956 |
|
T25 |
13435 |
|
T1 |
21192 |
auto[1] |
auto[1] |
auto[1] |
402880 |
1 |
|
|
T24 |
9300 |
|
T25 |
2155 |
|
T1 |
2564 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8497906 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
138111 |
auto[1] |
6265782 |
1 |
|
|
T24 |
137676 |
|
T25 |
29662 |
|
T1 |
45271 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13956060 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
257884 |
auto[1] |
807628 |
1 |
|
|
T24 |
17903 |
|
T25 |
4039 |
|
T1 |
5338 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8517556 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
143170 |
auto[1] |
6246132 |
1 |
|
|
T24 |
132617 |
|
T25 |
30042 |
|
T1 |
49145 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2708625 |
1 |
|
|
T24 |
58607 |
|
T25 |
13412 |
|
T1 |
22710 |
auto[1] |
auto[0] |
auto[1] |
401947 |
1 |
|
|
T24 |
9214 |
|
T25 |
2077 |
|
T1 |
2831 |
auto[1] |
auto[1] |
auto[0] |
2729879 |
1 |
|
|
T24 |
56107 |
|
T25 |
12591 |
|
T1 |
21097 |
auto[1] |
auto[1] |
auto[1] |
405681 |
1 |
|
|
T24 |
8689 |
|
T25 |
1962 |
|
T1 |
2507 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8541755 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
140607 |
auto[1] |
6221933 |
1 |
|
|
T24 |
135180 |
|
T25 |
30233 |
|
T1 |
45211 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13952492 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
256237 |
auto[1] |
811196 |
1 |
|
|
T24 |
19550 |
|
T25 |
4021 |
|
T1 |
4971 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8488936 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
134877 |
auto[1] |
6274752 |
1 |
|
|
T24 |
140910 |
|
T25 |
29841 |
|
T1 |
47042 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2747603 |
1 |
|
|
T24 |
63055 |
|
T25 |
12758 |
|
T1 |
21431 |
auto[1] |
auto[0] |
auto[1] |
408646 |
1 |
|
|
T24 |
10329 |
|
T25 |
2034 |
|
T1 |
2557 |
auto[1] |
auto[1] |
auto[0] |
2715953 |
1 |
|
|
T24 |
58305 |
|
T25 |
13062 |
|
T1 |
20640 |
auto[1] |
auto[1] |
auto[1] |
402550 |
1 |
|
|
T24 |
9221 |
|
T25 |
1987 |
|
T1 |
2414 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8539018 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
135136 |
auto[1] |
6224670 |
1 |
|
|
T24 |
140651 |
|
T25 |
30218 |
|
T1 |
48813 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13960984 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
257478 |
auto[1] |
802704 |
1 |
|
|
T24 |
18309 |
|
T25 |
4264 |
|
T1 |
4849 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8547698 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
140992 |
auto[1] |
6215990 |
1 |
|
|
T24 |
134795 |
|
T25 |
30866 |
|
T1 |
46131 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2723934 |
1 |
|
|
T24 |
57239 |
|
T25 |
13372 |
|
T1 |
21274 |
auto[1] |
auto[0] |
auto[1] |
404364 |
1 |
|
|
T24 |
8820 |
|
T25 |
2092 |
|
T1 |
2437 |
auto[1] |
auto[1] |
auto[0] |
2689352 |
1 |
|
|
T24 |
59247 |
|
T25 |
13230 |
|
T1 |
20008 |
auto[1] |
auto[1] |
auto[1] |
398340 |
1 |
|
|
T24 |
9489 |
|
T25 |
2172 |
|
T1 |
2412 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8525066 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
136023 |
auto[1] |
6238622 |
1 |
|
|
T24 |
139764 |
|
T25 |
31168 |
|
T1 |
46104 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13953671 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
256963 |
auto[1] |
810017 |
1 |
|
|
T24 |
18824 |
|
T25 |
4523 |
|
T1 |
5367 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8501085 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
137271 |
auto[1] |
6262603 |
1 |
|
|
T24 |
138516 |
|
T25 |
32821 |
|
T1 |
50673 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2738442 |
1 |
|
|
T24 |
60276 |
|
T25 |
14182 |
|
T1 |
23596 |
auto[1] |
auto[0] |
auto[1] |
408141 |
1 |
|
|
T24 |
9536 |
|
T25 |
2336 |
|
T1 |
2892 |
auto[1] |
auto[1] |
auto[0] |
2714144 |
1 |
|
|
T24 |
59416 |
|
T25 |
14116 |
|
T1 |
21710 |
auto[1] |
auto[1] |
auto[1] |
401876 |
1 |
|
|
T24 |
9288 |
|
T25 |
2187 |
|
T1 |
2475 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8512103 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
134682 |
auto[1] |
6251585 |
1 |
|
|
T24 |
141105 |
|
T25 |
32274 |
|
T1 |
47162 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13953981 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
256498 |
auto[1] |
809707 |
1 |
|
|
T24 |
19289 |
|
T25 |
4348 |
|
T1 |
5014 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8502133 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
135882 |
auto[1] |
6261555 |
1 |
|
|
T24 |
139905 |
|
T25 |
31788 |
|
T1 |
46571 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2733794 |
1 |
|
|
T24 |
61499 |
|
T25 |
13550 |
|
T1 |
21682 |
auto[1] |
auto[0] |
auto[1] |
405999 |
1 |
|
|
T24 |
9659 |
|
T25 |
2152 |
|
T1 |
2737 |
auto[1] |
auto[1] |
auto[0] |
2718054 |
1 |
|
|
T24 |
59117 |
|
T25 |
13890 |
|
T1 |
19875 |
auto[1] |
auto[1] |
auto[1] |
403708 |
1 |
|
|
T24 |
9630 |
|
T25 |
2196 |
|
T1 |
2277 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8526851 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
137754 |
auto[1] |
6236837 |
1 |
|
|
T24 |
138033 |
|
T25 |
30766 |
|
T1 |
47765 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13959530 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
256550 |
auto[1] |
804158 |
1 |
|
|
T24 |
19237 |
|
T25 |
4149 |
|
T1 |
5294 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8536547 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
135739 |
auto[1] |
6227141 |
1 |
|
|
T24 |
140048 |
|
T25 |
30361 |
|
T1 |
49308 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2719267 |
1 |
|
|
T24 |
60343 |
|
T25 |
13321 |
|
T1 |
21581 |
auto[1] |
auto[0] |
auto[1] |
402938 |
1 |
|
|
T24 |
9587 |
|
T25 |
2010 |
|
T1 |
2556 |
auto[1] |
auto[1] |
auto[0] |
2703716 |
1 |
|
|
T24 |
60468 |
|
T25 |
12891 |
|
T1 |
22433 |
auto[1] |
auto[1] |
auto[1] |
401220 |
1 |
|
|
T24 |
9650 |
|
T25 |
2139 |
|
T1 |
2738 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8523587 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
140105 |
auto[1] |
6240101 |
1 |
|
|
T24 |
135682 |
|
T25 |
32945 |
|
T1 |
47901 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13956725 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
256727 |
auto[1] |
806963 |
1 |
|
|
T24 |
19060 |
|
T25 |
4404 |
|
T1 |
4700 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8523075 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
137470 |
auto[1] |
6240613 |
1 |
|
|
T24 |
138317 |
|
T25 |
31438 |
|
T1 |
46205 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2716120 |
1 |
|
|
T24 |
60718 |
|
T25 |
12871 |
|
T1 |
20769 |
auto[1] |
auto[0] |
auto[1] |
402710 |
1 |
|
|
T24 |
9793 |
|
T25 |
2029 |
|
T1 |
2314 |
auto[1] |
auto[1] |
auto[0] |
2717530 |
1 |
|
|
T24 |
58539 |
|
T25 |
14163 |
|
T1 |
20736 |
auto[1] |
auto[1] |
auto[1] |
404253 |
1 |
|
|
T24 |
9267 |
|
T25 |
2375 |
|
T1 |
2386 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8521863 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
141173 |
auto[1] |
6241825 |
1 |
|
|
T24 |
134614 |
|
T25 |
30243 |
|
T1 |
45815 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13955577 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
256551 |
auto[1] |
808111 |
1 |
|
|
T24 |
19236 |
|
T25 |
4191 |
|
T1 |
5085 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8506728 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
135598 |
auto[1] |
6256960 |
1 |
|
|
T24 |
140189 |
|
T25 |
30881 |
|
T1 |
47696 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2736211 |
1 |
|
|
T24 |
62504 |
|
T25 |
13571 |
|
T1 |
22816 |
auto[1] |
auto[0] |
auto[1] |
407293 |
1 |
|
|
T24 |
10172 |
|
T25 |
2057 |
|
T1 |
2800 |
auto[1] |
auto[1] |
auto[0] |
2712638 |
1 |
|
|
T24 |
58449 |
|
T25 |
13119 |
|
T1 |
19795 |
auto[1] |
auto[1] |
auto[1] |
400818 |
1 |
|
|
T24 |
9064 |
|
T25 |
2134 |
|
T1 |
2285 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8493383 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
139337 |
auto[1] |
6270305 |
1 |
|
|
T24 |
136450 |
|
T25 |
29038 |
|
T1 |
47116 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13958200 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
257449 |
auto[1] |
805488 |
1 |
|
|
T24 |
18338 |
|
T25 |
3985 |
|
T1 |
5044 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8525927 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
141365 |
auto[1] |
6237761 |
1 |
|
|
T24 |
134422 |
|
T25 |
29351 |
|
T1 |
47918 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2699727 |
1 |
|
|
T24 |
59427 |
|
T25 |
13640 |
|
T1 |
22115 |
auto[1] |
auto[0] |
auto[1] |
400259 |
1 |
|
|
T24 |
9641 |
|
T25 |
2118 |
|
T1 |
2563 |
auto[1] |
auto[1] |
auto[0] |
2732546 |
1 |
|
|
T24 |
56657 |
|
T25 |
11726 |
|
T1 |
20759 |
auto[1] |
auto[1] |
auto[1] |
405229 |
1 |
|
|
T24 |
8697 |
|
T25 |
1867 |
|
T1 |
2481 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8511297 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
139982 |
auto[1] |
6252391 |
1 |
|
|
T24 |
135805 |
|
T25 |
30654 |
|
T1 |
47557 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13957817 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
256670 |
auto[1] |
805871 |
1 |
|
|
T24 |
19117 |
|
T25 |
4027 |
|
T1 |
5133 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8523284 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
136827 |
auto[1] |
6240404 |
1 |
|
|
T24 |
138960 |
|
T25 |
29304 |
|
T1 |
47964 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2711511 |
1 |
|
|
T24 |
59773 |
|
T25 |
12813 |
|
T1 |
21947 |
auto[1] |
auto[0] |
auto[1] |
401503 |
1 |
|
|
T24 |
9565 |
|
T25 |
1986 |
|
T1 |
2598 |
auto[1] |
auto[1] |
auto[0] |
2723022 |
1 |
|
|
T24 |
60070 |
|
T25 |
12464 |
|
T1 |
20884 |
auto[1] |
auto[1] |
auto[1] |
404368 |
1 |
|
|
T24 |
9552 |
|
T25 |
2041 |
|
T1 |
2535 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8493865 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
129687 |
auto[1] |
6269823 |
1 |
|
|
T24 |
146100 |
|
T25 |
30949 |
|
T1 |
48952 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13960306 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
257168 |
auto[1] |
803382 |
1 |
|
|
T24 |
18619 |
|
T25 |
4332 |
|
T1 |
4883 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8531311 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
138288 |
auto[1] |
6232377 |
1 |
|
|
T24 |
137499 |
|
T25 |
31455 |
|
T1 |
46329 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2704028 |
1 |
|
|
T24 |
55427 |
|
T25 |
13506 |
|
T1 |
20017 |
auto[1] |
auto[0] |
auto[1] |
399528 |
1 |
|
|
T24 |
8465 |
|
T25 |
2183 |
|
T1 |
2261 |
auto[1] |
auto[1] |
auto[0] |
2724967 |
1 |
|
|
T24 |
63453 |
|
T25 |
13617 |
|
T1 |
21429 |
auto[1] |
auto[1] |
auto[1] |
403854 |
1 |
|
|
T24 |
10154 |
|
T25 |
2149 |
|
T1 |
2622 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8539314 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
139428 |
auto[1] |
6224374 |
1 |
|
|
T24 |
136359 |
|
T25 |
28859 |
|
T1 |
47100 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13956389 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
256120 |
auto[1] |
807299 |
1 |
|
|
T24 |
19667 |
|
T25 |
4286 |
|
T1 |
5586 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8512046 |
1 |
|
|
T22 |
137 |
|
T23 |
235 |
|
T24 |
133980 |
auto[1] |
6251642 |
1 |
|
|
T24 |
141807 |
|
T25 |
31188 |
|
T1 |
50781 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2742867 |
1 |
|
|
T24 |
60896 |
|
T25 |
14348 |
|
T1 |
22886 |
auto[1] |
auto[0] |
auto[1] |
406326 |
1 |
|
|
T24 |
9829 |
|
T25 |
2231 |
|
T1 |
2880 |
auto[1] |
auto[1] |
auto[0] |
2701476 |
1 |
|
|
T24 |
61244 |
|
T25 |
12554 |
|
T1 |
22309 |
auto[1] |
auto[1] |
auto[1] |
400973 |
1 |
|
|
T24 |
9838 |
|
T25 |
2055 |
|
T1 |
2706 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |