Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 947
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T767 /workspace/coverage/cover_reg_top/28.gpio_intr_test.525183104 Jul 13 04:43:16 PM PDT 24 Jul 13 04:43:18 PM PDT 24 27724000 ps
T768 /workspace/coverage/cover_reg_top/46.gpio_intr_test.3102810584 Jul 13 04:43:28 PM PDT 24 Jul 13 04:43:32 PM PDT 24 27534213 ps
T769 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.4289126914 Jul 13 04:43:07 PM PDT 24 Jul 13 04:43:08 PM PDT 24 40221961 ps
T770 /workspace/coverage/cover_reg_top/39.gpio_intr_test.2912516613 Jul 13 04:43:26 PM PDT 24 Jul 13 04:43:28 PM PDT 24 18501840 ps
T85 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.53251001 Jul 13 04:43:04 PM PDT 24 Jul 13 04:43:06 PM PDT 24 28246049 ps
T771 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1431414238 Jul 13 04:43:18 PM PDT 24 Jul 13 04:43:21 PM PDT 24 50208322 ps
T99 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2045745047 Jul 13 04:43:13 PM PDT 24 Jul 13 04:43:14 PM PDT 24 221972951 ps
T772 /workspace/coverage/cover_reg_top/2.gpio_intr_test.1762322292 Jul 13 04:42:55 PM PDT 24 Jul 13 04:42:58 PM PDT 24 12634297 ps
T773 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2269387841 Jul 13 04:42:57 PM PDT 24 Jul 13 04:43:01 PM PDT 24 46510941 ps
T42 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1322665866 Jul 13 04:43:16 PM PDT 24 Jul 13 04:43:18 PM PDT 24 107364817 ps
T774 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1043456302 Jul 13 04:43:23 PM PDT 24 Jul 13 04:43:25 PM PDT 24 49692424 ps
T775 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1599015040 Jul 13 04:42:59 PM PDT 24 Jul 13 04:43:03 PM PDT 24 227537189 ps
T776 /workspace/coverage/cover_reg_top/21.gpio_intr_test.2668615754 Jul 13 04:43:16 PM PDT 24 Jul 13 04:43:18 PM PDT 24 23319591 ps
T777 /workspace/coverage/cover_reg_top/47.gpio_intr_test.529546210 Jul 13 04:43:28 PM PDT 24 Jul 13 04:43:32 PM PDT 24 33262964 ps
T778 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1103639356 Jul 13 04:43:18 PM PDT 24 Jul 13 04:43:21 PM PDT 24 57214316 ps
T779 /workspace/coverage/cover_reg_top/49.gpio_intr_test.2762292494 Jul 13 04:43:26 PM PDT 24 Jul 13 04:43:28 PM PDT 24 182224586 ps
T780 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2656353632 Jul 13 04:42:55 PM PDT 24 Jul 13 04:42:56 PM PDT 24 24154366 ps
T100 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.971557365 Jul 13 04:42:55 PM PDT 24 Jul 13 04:42:57 PM PDT 24 118618546 ps
T781 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.4286755458 Jul 13 04:42:56 PM PDT 24 Jul 13 04:42:58 PM PDT 24 17243495 ps
T782 /workspace/coverage/cover_reg_top/22.gpio_intr_test.615776805 Jul 13 04:43:16 PM PDT 24 Jul 13 04:43:17 PM PDT 24 13811938 ps
T101 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1008119346 Jul 13 04:43:16 PM PDT 24 Jul 13 04:43:17 PM PDT 24 18347367 ps
T87 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1743220037 Jul 13 04:42:49 PM PDT 24 Jul 13 04:42:50 PM PDT 24 28274420 ps
T783 /workspace/coverage/cover_reg_top/36.gpio_intr_test.2882531006 Jul 13 04:43:26 PM PDT 24 Jul 13 04:43:28 PM PDT 24 17612125 ps
T784 /workspace/coverage/cover_reg_top/35.gpio_intr_test.1239977027 Jul 13 04:43:28 PM PDT 24 Jul 13 04:43:31 PM PDT 24 30549047 ps
T785 /workspace/coverage/cover_reg_top/33.gpio_intr_test.1372794995 Jul 13 04:43:28 PM PDT 24 Jul 13 04:43:32 PM PDT 24 30177838 ps
T786 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3402020720 Jul 13 04:42:55 PM PDT 24 Jul 13 04:42:57 PM PDT 24 24303261 ps
T787 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3349297553 Jul 13 04:42:55 PM PDT 24 Jul 13 04:42:58 PM PDT 24 30176114 ps
T788 /workspace/coverage/cover_reg_top/16.gpio_intr_test.2501482172 Jul 13 04:43:18 PM PDT 24 Jul 13 04:43:20 PM PDT 24 14338374 ps
T789 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.449041562 Jul 13 04:43:09 PM PDT 24 Jul 13 04:43:10 PM PDT 24 15116723 ps
T43 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1581722318 Jul 13 04:43:03 PM PDT 24 Jul 13 04:43:05 PM PDT 24 71681960 ps
T114 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2366091229 Jul 13 04:43:00 PM PDT 24 Jul 13 04:43:02 PM PDT 24 240846970 ps
T790 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1674367073 Jul 13 04:43:04 PM PDT 24 Jul 13 04:43:06 PM PDT 24 112050246 ps
T791 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1942071482 Jul 13 04:42:54 PM PDT 24 Jul 13 04:42:56 PM PDT 24 1133626557 ps
T792 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3546159312 Jul 13 04:43:17 PM PDT 24 Jul 13 04:43:22 PM PDT 24 129502453 ps
T793 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3439416933 Jul 13 04:43:15 PM PDT 24 Jul 13 04:43:17 PM PDT 24 36444583 ps
T794 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1516118548 Jul 13 04:42:53 PM PDT 24 Jul 13 04:42:54 PM PDT 24 15409524 ps
T795 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3188379054 Jul 13 04:43:12 PM PDT 24 Jul 13 04:43:13 PM PDT 24 32343925 ps
T796 /workspace/coverage/cover_reg_top/14.gpio_intr_test.1765754846 Jul 13 04:43:03 PM PDT 24 Jul 13 04:43:05 PM PDT 24 23244742 ps
T797 /workspace/coverage/cover_reg_top/44.gpio_intr_test.2886128850 Jul 13 04:43:27 PM PDT 24 Jul 13 04:43:30 PM PDT 24 59656086 ps
T798 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.112536502 Jul 13 04:43:02 PM PDT 24 Jul 13 04:43:04 PM PDT 24 123411516 ps
T799 /workspace/coverage/cover_reg_top/45.gpio_intr_test.2376139273 Jul 13 04:43:25 PM PDT 24 Jul 13 04:43:26 PM PDT 24 13140487 ps
T45 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1014145453 Jul 13 04:43:03 PM PDT 24 Jul 13 04:43:05 PM PDT 24 161599726 ps
T800 /workspace/coverage/cover_reg_top/31.gpio_intr_test.2656904614 Jul 13 04:43:28 PM PDT 24 Jul 13 04:43:31 PM PDT 24 18368765 ps
T113 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2959729161 Jul 13 04:43:24 PM PDT 24 Jul 13 04:43:25 PM PDT 24 107355311 ps
T801 /workspace/coverage/cover_reg_top/42.gpio_intr_test.3984096185 Jul 13 04:43:26 PM PDT 24 Jul 13 04:43:29 PM PDT 24 20624032 ps
T802 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1723003078 Jul 13 04:43:10 PM PDT 24 Jul 13 04:43:11 PM PDT 24 79697126 ps
T803 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2893161944 Jul 13 04:42:55 PM PDT 24 Jul 13 04:42:56 PM PDT 24 11625437 ps
T804 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2459492400 Jul 13 04:42:55 PM PDT 24 Jul 13 04:42:59 PM PDT 24 47126405 ps
T805 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3324724495 Jul 13 04:42:57 PM PDT 24 Jul 13 04:42:59 PM PDT 24 21570012 ps
T806 /workspace/coverage/cover_reg_top/9.gpio_intr_test.967955138 Jul 13 04:43:08 PM PDT 24 Jul 13 04:43:09 PM PDT 24 45495307 ps
T807 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1974975789 Jul 13 04:42:55 PM PDT 24 Jul 13 04:42:57 PM PDT 24 159408673 ps
T808 /workspace/coverage/cover_reg_top/29.gpio_intr_test.2199928852 Jul 13 04:43:18 PM PDT 24 Jul 13 04:43:21 PM PDT 24 13099905 ps
T41 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.4210425155 Jul 13 04:43:11 PM PDT 24 Jul 13 04:43:13 PM PDT 24 108597826 ps
T809 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1663390537 Jul 13 04:43:00 PM PDT 24 Jul 13 04:43:02 PM PDT 24 30084638 ps
T810 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1122116148 Jul 13 04:42:58 PM PDT 24 Jul 13 04:43:00 PM PDT 24 15932730 ps
T811 /workspace/coverage/cover_reg_top/23.gpio_intr_test.3986761080 Jul 13 04:43:16 PM PDT 24 Jul 13 04:43:18 PM PDT 24 38339824 ps
T812 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1630675327 Jul 13 04:43:15 PM PDT 24 Jul 13 04:43:16 PM PDT 24 28531709 ps
T813 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.929330839 Jul 13 04:44:25 PM PDT 24 Jul 13 04:44:29 PM PDT 24 305257302 ps
T814 /workspace/coverage/cover_reg_top/43.gpio_intr_test.2266396578 Jul 13 04:43:26 PM PDT 24 Jul 13 04:43:29 PM PDT 24 46215272 ps
T815 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1843909340 Jul 13 04:42:46 PM PDT 24 Jul 13 04:42:47 PM PDT 24 151310593 ps
T816 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1378163069 Jul 13 04:43:10 PM PDT 24 Jul 13 04:43:11 PM PDT 24 15829924 ps
T817 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.901461405 Jul 13 04:43:02 PM PDT 24 Jul 13 04:43:04 PM PDT 24 501703696 ps
T818 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1613075755 Jul 13 04:42:58 PM PDT 24 Jul 13 04:43:00 PM PDT 24 56266306 ps
T819 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.290344203 Jul 13 04:43:17 PM PDT 24 Jul 13 04:43:19 PM PDT 24 54415729 ps
T820 /workspace/coverage/cover_reg_top/3.gpio_intr_test.2311884623 Jul 13 04:42:56 PM PDT 24 Jul 13 04:42:58 PM PDT 24 22375681 ps
T821 /workspace/coverage/cover_reg_top/8.gpio_intr_test.283226734 Jul 13 04:43:04 PM PDT 24 Jul 13 04:43:05 PM PDT 24 13250068 ps
T822 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2542563576 Jul 13 04:42:55 PM PDT 24 Jul 13 04:42:56 PM PDT 24 57212174 ps
T823 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3372424580 Jul 13 04:42:55 PM PDT 24 Jul 13 04:42:57 PM PDT 24 394806128 ps
T824 /workspace/coverage/cover_reg_top/24.gpio_intr_test.4264411043 Jul 13 04:43:17 PM PDT 24 Jul 13 04:43:20 PM PDT 24 38100963 ps
T825 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1995208331 Jul 13 04:42:53 PM PDT 24 Jul 13 04:42:56 PM PDT 24 1209602339 ps
T826 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1116321680 Jul 13 04:43:03 PM PDT 24 Jul 13 04:43:05 PM PDT 24 38506077 ps
T91 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1083606482 Jul 13 04:43:02 PM PDT 24 Jul 13 04:43:04 PM PDT 24 24399080 ps
T827 /workspace/coverage/cover_reg_top/25.gpio_intr_test.3288202448 Jul 13 04:43:16 PM PDT 24 Jul 13 04:43:18 PM PDT 24 14092127 ps
T92 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1148819536 Jul 13 04:42:57 PM PDT 24 Jul 13 04:42:59 PM PDT 24 21317727 ps
T88 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.346451236 Jul 13 04:42:57 PM PDT 24 Jul 13 04:42:59 PM PDT 24 15479343 ps
T828 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3902506529 Jul 13 04:42:55 PM PDT 24 Jul 13 04:42:59 PM PDT 24 84355034 ps
T829 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.44820503 Jul 13 04:43:14 PM PDT 24 Jul 13 04:43:16 PM PDT 24 58691947 ps
T830 /workspace/coverage/cover_reg_top/19.gpio_intr_test.647187274 Jul 13 04:43:17 PM PDT 24 Jul 13 04:43:20 PM PDT 24 61997416 ps
T831 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2712327477 Jul 13 04:42:54 PM PDT 24 Jul 13 04:42:56 PM PDT 24 147708648 ps
T832 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.498404537 Jul 13 04:43:17 PM PDT 24 Jul 13 04:43:19 PM PDT 24 51060980 ps
T833 /workspace/coverage/cover_reg_top/7.gpio_intr_test.2050863964 Jul 13 04:42:56 PM PDT 24 Jul 13 04:42:58 PM PDT 24 18790642 ps
T834 /workspace/coverage/cover_reg_top/11.gpio_intr_test.4217748251 Jul 13 04:43:12 PM PDT 24 Jul 13 04:43:13 PM PDT 24 14539253 ps
T835 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.4207120928 Jul 13 04:43:02 PM PDT 24 Jul 13 04:43:03 PM PDT 24 13984164 ps
T836 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2223201863 Jul 13 04:42:58 PM PDT 24 Jul 13 04:43:00 PM PDT 24 49038717 ps
T837 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.875566138 Jul 13 04:43:17 PM PDT 24 Jul 13 04:43:20 PM PDT 24 93786576 ps
T838 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1718215263 Jul 13 04:42:56 PM PDT 24 Jul 13 04:42:58 PM PDT 24 69979642 ps
T839 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.870105242 Jul 13 04:43:04 PM PDT 24 Jul 13 04:43:06 PM PDT 24 123838686 ps
T89 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.315039813 Jul 13 04:42:56 PM PDT 24 Jul 13 04:42:59 PM PDT 24 111678226 ps
T840 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3013856551 Jul 13 04:43:00 PM PDT 24 Jul 13 04:43:02 PM PDT 24 168205342 ps
T841 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1276392926 Jul 13 04:43:18 PM PDT 24 Jul 13 04:43:22 PM PDT 24 94808508 ps
T90 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.796642413 Jul 13 04:43:00 PM PDT 24 Jul 13 04:43:03 PM PDT 24 260663057 ps
T842 /workspace/coverage/cover_reg_top/18.gpio_intr_test.1827183413 Jul 13 04:43:19 PM PDT 24 Jul 13 04:43:21 PM PDT 24 28224253 ps
T843 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.495068817 Jul 13 04:43:18 PM PDT 24 Jul 13 04:43:21 PM PDT 24 15510062 ps
T844 /workspace/coverage/cover_reg_top/5.gpio_intr_test.4048466337 Jul 13 04:42:56 PM PDT 24 Jul 13 04:42:58 PM PDT 24 14084926 ps
T845 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2670435624 Jul 13 04:43:15 PM PDT 24 Jul 13 04:43:16 PM PDT 24 43096676 ps
T846 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.292293215 Jul 13 04:42:54 PM PDT 24 Jul 13 04:42:56 PM PDT 24 116116902 ps
T847 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.885403474 Jul 13 04:43:24 PM PDT 24 Jul 13 04:43:25 PM PDT 24 19066261 ps
T848 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3898324348 Jul 13 05:52:39 PM PDT 24 Jul 13 05:52:41 PM PDT 24 59300605 ps
T849 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2175967245 Jul 13 05:52:31 PM PDT 24 Jul 13 05:52:34 PM PDT 24 135903292 ps
T850 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4064817340 Jul 13 05:52:30 PM PDT 24 Jul 13 05:52:33 PM PDT 24 60710091 ps
T851 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1428424262 Jul 13 05:52:44 PM PDT 24 Jul 13 05:52:45 PM PDT 24 294423662 ps
T852 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4165694342 Jul 13 05:52:31 PM PDT 24 Jul 13 05:52:33 PM PDT 24 59480132 ps
T853 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.468971038 Jul 13 05:52:22 PM PDT 24 Jul 13 05:52:24 PM PDT 24 440898490 ps
T854 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2549300710 Jul 13 05:52:30 PM PDT 24 Jul 13 05:52:33 PM PDT 24 57253076 ps
T855 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2656964345 Jul 13 05:52:16 PM PDT 24 Jul 13 05:52:17 PM PDT 24 47595341 ps
T856 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2953023519 Jul 13 05:52:30 PM PDT 24 Jul 13 05:52:33 PM PDT 24 63558447 ps
T857 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1941291746 Jul 13 05:52:37 PM PDT 24 Jul 13 05:52:39 PM PDT 24 31459995 ps
T858 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2441620004 Jul 13 05:52:16 PM PDT 24 Jul 13 05:52:18 PM PDT 24 211455932 ps
T859 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3194682452 Jul 13 05:52:23 PM PDT 24 Jul 13 05:52:25 PM PDT 24 38790298 ps
T860 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3971999161 Jul 13 05:52:30 PM PDT 24 Jul 13 05:52:33 PM PDT 24 62827682 ps
T861 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2260721900 Jul 13 05:52:26 PM PDT 24 Jul 13 05:52:28 PM PDT 24 43986185 ps
T862 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1187872382 Jul 13 05:52:17 PM PDT 24 Jul 13 05:52:20 PM PDT 24 63703218 ps
T863 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3358270591 Jul 13 05:52:25 PM PDT 24 Jul 13 05:52:27 PM PDT 24 216931607 ps
T864 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3381115659 Jul 13 05:52:30 PM PDT 24 Jul 13 05:52:33 PM PDT 24 660582249 ps
T865 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.407756075 Jul 13 05:52:39 PM PDT 24 Jul 13 05:52:41 PM PDT 24 161871182 ps
T866 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1595423090 Jul 13 05:52:25 PM PDT 24 Jul 13 05:52:27 PM PDT 24 79846067 ps
T867 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.377726935 Jul 13 05:52:17 PM PDT 24 Jul 13 05:52:21 PM PDT 24 50929623 ps
T868 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1707186835 Jul 13 05:52:16 PM PDT 24 Jul 13 05:52:17 PM PDT 24 45176476 ps
T869 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.249930331 Jul 13 05:52:17 PM PDT 24 Jul 13 05:52:21 PM PDT 24 367000110 ps
T870 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1310887456 Jul 13 05:52:24 PM PDT 24 Jul 13 05:52:27 PM PDT 24 172041344 ps
T871 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.184418331 Jul 13 05:52:17 PM PDT 24 Jul 13 05:52:21 PM PDT 24 193255011 ps
T872 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3758899166 Jul 13 05:52:18 PM PDT 24 Jul 13 05:52:21 PM PDT 24 409027924 ps
T873 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1611344 Jul 13 05:52:31 PM PDT 24 Jul 13 05:52:33 PM PDT 24 116806167 ps
T874 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3463187423 Jul 13 05:52:37 PM PDT 24 Jul 13 05:52:39 PM PDT 24 133980465 ps
T875 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.60732533 Jul 13 05:52:18 PM PDT 24 Jul 13 05:52:21 PM PDT 24 176244198 ps
T876 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2090014018 Jul 13 05:52:30 PM PDT 24 Jul 13 05:52:33 PM PDT 24 90954218 ps
T877 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1474253139 Jul 13 05:52:28 PM PDT 24 Jul 13 05:52:30 PM PDT 24 33173386 ps
T878 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1519535484 Jul 13 05:52:20 PM PDT 24 Jul 13 05:52:23 PM PDT 24 67550774 ps
T879 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3094349269 Jul 13 05:52:16 PM PDT 24 Jul 13 05:52:17 PM PDT 24 126072002 ps
T880 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.581287564 Jul 13 05:52:19 PM PDT 24 Jul 13 05:52:22 PM PDT 24 70292089 ps
T881 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4075062501 Jul 13 05:52:22 PM PDT 24 Jul 13 05:52:24 PM PDT 24 163224786 ps
T882 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2236641983 Jul 13 05:52:41 PM PDT 24 Jul 13 05:52:43 PM PDT 24 48734364 ps
T883 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.19295012 Jul 13 05:52:21 PM PDT 24 Jul 13 05:52:23 PM PDT 24 168062223 ps
T884 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3784859077 Jul 13 05:52:18 PM PDT 24 Jul 13 05:52:21 PM PDT 24 517534943 ps
T885 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1223708931 Jul 13 05:52:39 PM PDT 24 Jul 13 05:52:41 PM PDT 24 280837397 ps
T886 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2321162829 Jul 13 05:52:17 PM PDT 24 Jul 13 05:52:21 PM PDT 24 104326396 ps
T887 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1961847006 Jul 13 05:52:17 PM PDT 24 Jul 13 05:52:20 PM PDT 24 156436524 ps
T888 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3650184316 Jul 13 05:52:21 PM PDT 24 Jul 13 05:52:23 PM PDT 24 172998495 ps
T889 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1717059045 Jul 13 05:52:25 PM PDT 24 Jul 13 05:52:27 PM PDT 24 37830859 ps
T890 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1812106201 Jul 13 05:52:38 PM PDT 24 Jul 13 05:52:39 PM PDT 24 179358670 ps
T891 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4067460648 Jul 13 05:52:38 PM PDT 24 Jul 13 05:52:40 PM PDT 24 110827263 ps
T892 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2987959130 Jul 13 05:52:22 PM PDT 24 Jul 13 05:52:24 PM PDT 24 64269225 ps
T893 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1142220241 Jul 13 05:52:18 PM PDT 24 Jul 13 05:52:21 PM PDT 24 58853037 ps
T894 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1239543144 Jul 13 05:52:31 PM PDT 24 Jul 13 05:52:34 PM PDT 24 87892118 ps
T895 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1695785049 Jul 13 05:52:28 PM PDT 24 Jul 13 05:52:30 PM PDT 24 187731373 ps
T896 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1371716688 Jul 13 05:52:30 PM PDT 24 Jul 13 05:52:33 PM PDT 24 35090183 ps
T897 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1002572728 Jul 13 05:52:17 PM PDT 24 Jul 13 05:52:21 PM PDT 24 162729439 ps
T898 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.700620714 Jul 13 05:52:20 PM PDT 24 Jul 13 05:52:23 PM PDT 24 86376153 ps
T899 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3709435447 Jul 13 05:52:21 PM PDT 24 Jul 13 05:52:24 PM PDT 24 46669210 ps
T900 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2465510690 Jul 13 05:52:27 PM PDT 24 Jul 13 05:52:30 PM PDT 24 28482907 ps
T901 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2819342249 Jul 13 05:52:38 PM PDT 24 Jul 13 05:52:40 PM PDT 24 40532779 ps
T902 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.535606442 Jul 13 05:52:16 PM PDT 24 Jul 13 05:52:18 PM PDT 24 394722346 ps
T903 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2953765866 Jul 13 05:52:39 PM PDT 24 Jul 13 05:52:41 PM PDT 24 42282603 ps
T904 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2698831526 Jul 13 05:52:17 PM PDT 24 Jul 13 05:52:20 PM PDT 24 355069365 ps
T905 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1210394909 Jul 13 05:52:24 PM PDT 24 Jul 13 05:52:25 PM PDT 24 62369944 ps
T906 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2381967735 Jul 13 05:52:39 PM PDT 24 Jul 13 05:52:41 PM PDT 24 85363571 ps
T907 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.796840094 Jul 13 05:52:29 PM PDT 24 Jul 13 05:52:31 PM PDT 24 46521456 ps
T908 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.447896864 Jul 13 05:52:38 PM PDT 24 Jul 13 05:52:39 PM PDT 24 25643450 ps
T909 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.668943440 Jul 13 05:52:28 PM PDT 24 Jul 13 05:52:30 PM PDT 24 300833379 ps
T910 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4008687726 Jul 13 05:52:17 PM PDT 24 Jul 13 05:52:19 PM PDT 24 229945742 ps
T911 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.976743429 Jul 13 05:52:09 PM PDT 24 Jul 13 05:52:11 PM PDT 24 31335846 ps
T912 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1441766676 Jul 13 05:52:18 PM PDT 24 Jul 13 05:52:21 PM PDT 24 102784000 ps
T913 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.506090086 Jul 13 05:52:16 PM PDT 24 Jul 13 05:52:18 PM PDT 24 190060809 ps
T914 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.4045974981 Jul 13 05:52:18 PM PDT 24 Jul 13 05:52:21 PM PDT 24 49839736 ps
T915 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.31616732 Jul 13 05:52:19 PM PDT 24 Jul 13 05:52:22 PM PDT 24 44211403 ps
T916 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2476922565 Jul 13 05:52:22 PM PDT 24 Jul 13 05:52:24 PM PDT 24 197689077 ps
T917 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.54490323 Jul 13 05:52:18 PM PDT 24 Jul 13 05:52:21 PM PDT 24 73620248 ps
T918 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1364791002 Jul 13 05:52:16 PM PDT 24 Jul 13 05:52:18 PM PDT 24 61092092 ps
T919 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.185324551 Jul 13 05:52:29 PM PDT 24 Jul 13 05:52:31 PM PDT 24 33745802 ps
T920 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2342583255 Jul 13 05:52:24 PM PDT 24 Jul 13 05:52:25 PM PDT 24 101579108 ps
T921 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3431031921 Jul 13 05:52:27 PM PDT 24 Jul 13 05:52:29 PM PDT 24 119734647 ps
T922 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.344311587 Jul 13 05:52:17 PM PDT 24 Jul 13 05:52:20 PM PDT 24 74191053 ps
T923 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2444292108 Jul 13 05:52:16 PM PDT 24 Jul 13 05:52:19 PM PDT 24 124654048 ps
T924 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2561542558 Jul 13 05:52:20 PM PDT 24 Jul 13 05:52:22 PM PDT 24 123813889 ps
T925 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4130943230 Jul 13 05:52:38 PM PDT 24 Jul 13 05:52:40 PM PDT 24 287745667 ps
T926 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.856638496 Jul 13 05:52:12 PM PDT 24 Jul 13 05:52:14 PM PDT 24 202260725 ps
T927 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3500209033 Jul 13 05:52:30 PM PDT 24 Jul 13 05:52:33 PM PDT 24 48518336 ps
T928 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3904917132 Jul 13 05:52:31 PM PDT 24 Jul 13 05:52:34 PM PDT 24 158234105 ps
T929 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4114891885 Jul 13 05:52:19 PM PDT 24 Jul 13 05:52:22 PM PDT 24 25559152 ps
T930 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2563281736 Jul 13 05:52:18 PM PDT 24 Jul 13 05:52:21 PM PDT 24 55221107 ps
T931 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1920667293 Jul 13 05:52:30 PM PDT 24 Jul 13 05:52:33 PM PDT 24 284840258 ps
T932 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3545773114 Jul 13 05:52:25 PM PDT 24 Jul 13 05:52:27 PM PDT 24 519610551 ps
T933 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2172751177 Jul 13 05:52:11 PM PDT 24 Jul 13 05:52:13 PM PDT 24 106666415 ps
T934 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.529095061 Jul 13 05:52:29 PM PDT 24 Jul 13 05:52:30 PM PDT 24 168811850 ps
T935 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3357369524 Jul 13 05:52:22 PM PDT 24 Jul 13 05:52:24 PM PDT 24 72671167 ps
T936 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1548607471 Jul 13 05:52:18 PM PDT 24 Jul 13 05:52:21 PM PDT 24 53929570 ps
T937 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2515217849 Jul 13 05:52:16 PM PDT 24 Jul 13 05:52:19 PM PDT 24 46501412 ps
T938 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1421486001 Jul 13 05:52:25 PM PDT 24 Jul 13 05:52:27 PM PDT 24 72602807 ps
T939 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1739553894 Jul 13 05:52:20 PM PDT 24 Jul 13 05:52:22 PM PDT 24 58854950 ps
T940 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3669615441 Jul 13 05:52:17 PM PDT 24 Jul 13 05:52:21 PM PDT 24 1084144524 ps
T941 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1224272072 Jul 13 05:52:28 PM PDT 24 Jul 13 05:52:30 PM PDT 24 221206276 ps
T942 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1026637529 Jul 13 05:52:32 PM PDT 24 Jul 13 05:52:35 PM PDT 24 80464437 ps
T943 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2296801502 Jul 13 05:52:20 PM PDT 24 Jul 13 05:52:23 PM PDT 24 588405389 ps
T944 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.122760912 Jul 13 05:52:17 PM PDT 24 Jul 13 05:52:21 PM PDT 24 50539238 ps
T945 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2039140966 Jul 13 05:52:16 PM PDT 24 Jul 13 05:52:19 PM PDT 24 670375829 ps
T946 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3921079823 Jul 13 05:52:07 PM PDT 24 Jul 13 05:52:09 PM PDT 24 277318540 ps
T947 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3962677788 Jul 13 05:52:18 PM PDT 24 Jul 13 05:52:21 PM PDT 24 143172786 ps

Test location /workspace/coverage/default/32.gpio_stress_all.3315777628
Short name T1
Test name
Test status
Simulation time 51648261773 ps
CPU time 222.32 seconds
Started Jul 13 04:49:38 PM PDT 24
Finished Jul 13 04:53:22 PM PDT 24
Peak memory 198776 kb
Host smart-c2a75981-24bd-4afa-9d65-4369f9fba579
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315777628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3315777628
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3550695956
Short name T12
Test name
Test status
Simulation time 868091239 ps
CPU time 3.4 seconds
Started Jul 13 04:48:47 PM PDT 24
Finished Jul 13 04:48:54 PM PDT 24
Peak memory 198788 kb
Host smart-47f3b207-c733-4ced-bb1e-c8e402fa0002
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550695956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3550695956
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.71708733
Short name T24
Test name
Test status
Simulation time 104240596029 ps
CPU time 985.54 seconds
Started Jul 13 04:48:24 PM PDT 24
Finished Jul 13 05:04:52 PM PDT 24
Peak memory 198916 kb
Host smart-7279b724-45fa-41e3-b0ee-91190672d915
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=71708733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.71708733
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.3420686245
Short name T34
Test name
Test status
Simulation time 583984351 ps
CPU time 0.82 seconds
Started Jul 13 04:48:42 PM PDT 24
Finished Jul 13 04:48:45 PM PDT 24
Peak memory 214120 kb
Host smart-6cd739c8-b947-4fc1-af54-4146c4aac9a0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420686245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.3420686245
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1546071954
Short name T81
Test name
Test status
Simulation time 173344403 ps
CPU time 0.85 seconds
Started Jul 13 04:42:55 PM PDT 24
Finished Jul 13 04:42:58 PM PDT 24
Peak memory 196556 kb
Host smart-4115ac18-8f83-450f-942b-6d326e36c523
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546071954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1546071954
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3603596257
Short name T33
Test name
Test status
Simulation time 164831866 ps
CPU time 1.21 seconds
Started Jul 13 04:43:09 PM PDT 24
Finished Jul 13 04:43:10 PM PDT 24
Peak memory 198160 kb
Host smart-c3ecdac8-a971-49fb-82e9-ae1a25e6699e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603596257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.3603596257
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/20.gpio_alert_test.685392775
Short name T223
Test name
Test status
Simulation time 34996919 ps
CPU time 0.55 seconds
Started Jul 13 04:49:07 PM PDT 24
Finished Jul 13 04:49:08 PM PDT 24
Peak memory 194848 kb
Host smart-a0575d45-657e-49df-8cb3-1016f86c71ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685392775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.685392775
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2502877348
Short name T80
Test name
Test status
Simulation time 91344763 ps
CPU time 0.64 seconds
Started Jul 13 04:43:05 PM PDT 24
Finished Jul 13 04:43:06 PM PDT 24
Peak memory 195776 kb
Host smart-1805737c-765e-403e-8cf6-08af12d3339d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502877348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2502877348
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2556389740
Short name T94
Test name
Test status
Simulation time 40644353 ps
CPU time 0.87 seconds
Started Jul 13 04:43:05 PM PDT 24
Finished Jul 13 04:43:07 PM PDT 24
Peak memory 197640 kb
Host smart-a827199d-ba0e-4ddb-bb51-7982d3455000
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556389740 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2556389740
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3372424580
Short name T823
Test name
Test status
Simulation time 394806128 ps
CPU time 1.39 seconds
Started Jul 13 04:42:55 PM PDT 24
Finished Jul 13 04:42:57 PM PDT 24
Peak memory 198628 kb
Host smart-4badb788-42b5-4ecc-8ab4-13ab1942eef1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372424580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3372424580
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1743220037
Short name T87
Test name
Test status
Simulation time 28274420 ps
CPU time 0.74 seconds
Started Jul 13 04:42:49 PM PDT 24
Finished Jul 13 04:42:50 PM PDT 24
Peak memory 195988 kb
Host smart-1214116a-3a9a-47bc-be6a-20038f50b33a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743220037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1743220037
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1599015040
Short name T775
Test name
Test status
Simulation time 227537189 ps
CPU time 2.61 seconds
Started Jul 13 04:42:59 PM PDT 24
Finished Jul 13 04:43:03 PM PDT 24
Peak memory 198552 kb
Host smart-66c05184-9d9a-47db-a012-7b9bd74dcf45
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599015040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1599015040
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3721423231
Short name T750
Test name
Test status
Simulation time 33895422 ps
CPU time 0.68 seconds
Started Jul 13 04:42:54 PM PDT 24
Finished Jul 13 04:42:55 PM PDT 24
Peak memory 195224 kb
Host smart-90168719-3ef3-403f-a4f3-7e8fca9b4a22
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721423231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3721423231
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1270585216
Short name T733
Test name
Test status
Simulation time 59710156 ps
CPU time 0.88 seconds
Started Jul 13 04:42:47 PM PDT 24
Finished Jul 13 04:42:49 PM PDT 24
Peak memory 198808 kb
Host smart-20bc0a9c-1653-47ab-bf46-44208df3f7c7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270585216 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1270585216
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2045723506
Short name T83
Test name
Test status
Simulation time 25714126 ps
CPU time 0.64 seconds
Started Jul 13 04:42:47 PM PDT 24
Finished Jul 13 04:42:48 PM PDT 24
Peak memory 195284 kb
Host smart-46a309cb-f87d-4e11-b4fb-15a51e24a861
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045723506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2045723506
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3043236365
Short name T761
Test name
Test status
Simulation time 78751023 ps
CPU time 0.57 seconds
Started Jul 13 04:42:43 PM PDT 24
Finished Jul 13 04:42:44 PM PDT 24
Peak memory 194292 kb
Host smart-c7e20a7d-5eb2-41f5-86ad-3374bbcb88ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043236365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3043236365
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1843909340
Short name T815
Test name
Test status
Simulation time 151310593 ps
CPU time 0.65 seconds
Started Jul 13 04:42:46 PM PDT 24
Finished Jul 13 04:42:47 PM PDT 24
Peak memory 195348 kb
Host smart-fb189dca-9e97-443e-bd8d-d7ba9af53bfd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843909340 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1843909340
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2749210709
Short name T747
Test name
Test status
Simulation time 262197717 ps
CPU time 2.76 seconds
Started Jul 13 04:42:47 PM PDT 24
Finished Jul 13 04:42:50 PM PDT 24
Peak memory 198592 kb
Host smart-5c087236-5814-4ee9-93af-b6fe8aac2775
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749210709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2749210709
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.523414357
Short name T30
Test name
Test status
Simulation time 128703795 ps
CPU time 1.49 seconds
Started Jul 13 04:42:47 PM PDT 24
Finished Jul 13 04:42:49 PM PDT 24
Peak memory 198596 kb
Host smart-f8c14b10-7f90-4ce5-89cb-ba915eaf34ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523414357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.gpio_tl_intg_err.523414357
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.43937404
Short name T757
Test name
Test status
Simulation time 634122277 ps
CPU time 1.45 seconds
Started Jul 13 04:42:59 PM PDT 24
Finished Jul 13 04:43:01 PM PDT 24
Peak memory 197768 kb
Host smart-6ab67cb3-faf8-4826-95de-1cb2201dbcc3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43937404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.43937404
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1516118548
Short name T794
Test name
Test status
Simulation time 15409524 ps
CPU time 0.61 seconds
Started Jul 13 04:42:53 PM PDT 24
Finished Jul 13 04:42:54 PM PDT 24
Peak memory 194972 kb
Host smart-3fd49ea5-3da5-4b56-b14e-db2223610652
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516118548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.1516118548
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3349297553
Short name T787
Test name
Test status
Simulation time 30176114 ps
CPU time 0.8 seconds
Started Jul 13 04:42:55 PM PDT 24
Finished Jul 13 04:42:58 PM PDT 24
Peak memory 198360 kb
Host smart-8351e9ca-b418-4e51-855f-2ddaa72968a3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349297553 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3349297553
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.4207120928
Short name T835
Test name
Test status
Simulation time 13984164 ps
CPU time 0.65 seconds
Started Jul 13 04:43:02 PM PDT 24
Finished Jul 13 04:43:03 PM PDT 24
Peak memory 195888 kb
Host smart-1174a7a9-09d2-4100-bcdb-388549a69124
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207120928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.4207120928
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.4120024354
Short name T727
Test name
Test status
Simulation time 23386482 ps
CPU time 0.62 seconds
Started Jul 13 04:42:57 PM PDT 24
Finished Jul 13 04:43:00 PM PDT 24
Peak memory 194288 kb
Host smart-ed88f24e-a426-46d0-9f60-37d27266e637
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120024354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.4120024354
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1718215263
Short name T838
Test name
Test status
Simulation time 69979642 ps
CPU time 0.86 seconds
Started Jul 13 04:42:56 PM PDT 24
Finished Jul 13 04:42:58 PM PDT 24
Peak memory 196836 kb
Host smart-d4540eda-557e-43cf-b4c0-4dcadc33208e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718215263 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1718215263
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1995208331
Short name T825
Test name
Test status
Simulation time 1209602339 ps
CPU time 2.94 seconds
Started Jul 13 04:42:53 PM PDT 24
Finished Jul 13 04:42:56 PM PDT 24
Peak memory 198584 kb
Host smart-25300820-8ec4-4325-9524-cb805ed31d31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995208331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1995208331
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1532665912
Short name T47
Test name
Test status
Simulation time 59392615 ps
CPU time 0.88 seconds
Started Jul 13 04:42:57 PM PDT 24
Finished Jul 13 04:42:59 PM PDT 24
Peak memory 197704 kb
Host smart-c772a600-e2ce-463b-b471-dc7c54927c36
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532665912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1532665912
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1674367073
Short name T790
Test name
Test status
Simulation time 112050246 ps
CPU time 1.29 seconds
Started Jul 13 04:43:04 PM PDT 24
Finished Jul 13 04:43:06 PM PDT 24
Peak memory 198656 kb
Host smart-743ce9b1-9110-4a15-9e99-1d8a71daa828
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674367073 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.1674367073
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.1404601122
Short name T726
Test name
Test status
Simulation time 79424614 ps
CPU time 0.62 seconds
Started Jul 13 04:43:11 PM PDT 24
Finished Jul 13 04:43:12 PM PDT 24
Peak memory 194288 kb
Host smart-fd679b1c-dd35-4bb1-a666-f94d454bf382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404601122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1404601122
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.44820503
Short name T829
Test name
Test status
Simulation time 58691947 ps
CPU time 0.75 seconds
Started Jul 13 04:43:14 PM PDT 24
Finished Jul 13 04:43:16 PM PDT 24
Peak memory 196504 kb
Host smart-3ffc4e95-532a-4057-aaf8-d24ce4af7711
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44820503 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.gpio_same_csr_outstanding.44820503
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2670435624
Short name T845
Test name
Test status
Simulation time 43096676 ps
CPU time 1.07 seconds
Started Jul 13 04:43:15 PM PDT 24
Finished Jul 13 04:43:16 PM PDT 24
Peak memory 198372 kb
Host smart-58b126ad-8188-4d0c-9cdd-22900a55db71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670435624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2670435624
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.4074164311
Short name T32
Test name
Test status
Simulation time 125121349 ps
CPU time 1.49 seconds
Started Jul 13 04:43:05 PM PDT 24
Finished Jul 13 04:43:08 PM PDT 24
Peak memory 198704 kb
Host smart-e18a7f4f-bff6-4e1c-a7db-572d630eea91
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074164311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.4074164311
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.112536502
Short name T798
Test name
Test status
Simulation time 123411516 ps
CPU time 1.03 seconds
Started Jul 13 04:43:02 PM PDT 24
Finished Jul 13 04:43:04 PM PDT 24
Peak memory 198480 kb
Host smart-175a2b2b-0476-4cb2-a817-89fa411e31eb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112536502 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.112536502
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.53251001
Short name T85
Test name
Test status
Simulation time 28246049 ps
CPU time 0.63 seconds
Started Jul 13 04:43:04 PM PDT 24
Finished Jul 13 04:43:06 PM PDT 24
Peak memory 195268 kb
Host smart-4066629f-dc22-454c-a728-a6107e0d3065
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53251001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_
csr_rw.53251001
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.4217748251
Short name T834
Test name
Test status
Simulation time 14539253 ps
CPU time 0.64 seconds
Started Jul 13 04:43:12 PM PDT 24
Finished Jul 13 04:43:13 PM PDT 24
Peak memory 194292 kb
Host smart-2e9a219a-8eb6-44b8-9e48-4a238fac2f29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217748251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.4217748251
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1723003078
Short name T802
Test name
Test status
Simulation time 79697126 ps
CPU time 0.85 seconds
Started Jul 13 04:43:10 PM PDT 24
Finished Jul 13 04:43:11 PM PDT 24
Peak memory 196688 kb
Host smart-57aa736d-01dc-45c2-8c35-1b0c16bfe4d2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723003078 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1723003078
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.4089873233
Short name T764
Test name
Test status
Simulation time 198651518 ps
CPU time 1.68 seconds
Started Jul 13 04:43:02 PM PDT 24
Finished Jul 13 04:43:04 PM PDT 24
Peak memory 198556 kb
Host smart-eff10c4e-f236-4a32-b554-4ba8b04ec421
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089873233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.4089873233
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1581722318
Short name T43
Test name
Test status
Simulation time 71681960 ps
CPU time 1.18 seconds
Started Jul 13 04:43:03 PM PDT 24
Finished Jul 13 04:43:05 PM PDT 24
Peak memory 198556 kb
Host smart-49d6092b-a666-4563-8e21-d47a32983561
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581722318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.1581722318
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3188379054
Short name T795
Test name
Test status
Simulation time 32343925 ps
CPU time 0.89 seconds
Started Jul 13 04:43:12 PM PDT 24
Finished Jul 13 04:43:13 PM PDT 24
Peak memory 198480 kb
Host smart-d9f6db5d-df45-45bd-b5a4-c5404c28d73d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188379054 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3188379054
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.497643058
Short name T112
Test name
Test status
Simulation time 13473554 ps
CPU time 0.59 seconds
Started Jul 13 04:43:04 PM PDT 24
Finished Jul 13 04:43:06 PM PDT 24
Peak memory 194280 kb
Host smart-7d897308-1af1-4d35-8a80-fe3b9bac5eaf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497643058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.497643058
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.2117372860
Short name T759
Test name
Test status
Simulation time 12658013 ps
CPU time 0.61 seconds
Started Jul 13 04:43:03 PM PDT 24
Finished Jul 13 04:43:04 PM PDT 24
Peak memory 194224 kb
Host smart-fb3e8407-0df3-4eee-8e39-6081552a96a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117372860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.2117372860
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1305183212
Short name T742
Test name
Test status
Simulation time 1400180064 ps
CPU time 3.43 seconds
Started Jul 13 04:43:06 PM PDT 24
Finished Jul 13 04:43:10 PM PDT 24
Peak memory 198616 kb
Host smart-033d23bf-b8cc-45d8-a482-c997a427b75b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305183212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1305183212
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.901461405
Short name T817
Test name
Test status
Simulation time 501703696 ps
CPU time 1.19 seconds
Started Jul 13 04:43:02 PM PDT 24
Finished Jul 13 04:43:04 PM PDT 24
Peak memory 198668 kb
Host smart-632ae646-1560-4773-8a29-1d8ae423e2c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901461405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.901461405
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.4289126914
Short name T769
Test name
Test status
Simulation time 40221961 ps
CPU time 0.96 seconds
Started Jul 13 04:43:07 PM PDT 24
Finished Jul 13 04:43:08 PM PDT 24
Peak memory 198572 kb
Host smart-812422ab-5dcb-459d-8940-c53acf2c9f89
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289126914 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.4289126914
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.536612616
Short name T82
Test name
Test status
Simulation time 14071208 ps
CPU time 0.62 seconds
Started Jul 13 04:43:02 PM PDT 24
Finished Jul 13 04:43:03 PM PDT 24
Peak memory 193840 kb
Host smart-413ebb5f-bbfc-4898-8f6a-bb48497cc03f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536612616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio
_csr_rw.536612616
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1238783853
Short name T729
Test name
Test status
Simulation time 49695538 ps
CPU time 0.6 seconds
Started Jul 13 04:43:09 PM PDT 24
Finished Jul 13 04:43:10 PM PDT 24
Peak memory 194912 kb
Host smart-27fd7d2b-a7da-49eb-839b-22bf88458174
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238783853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1238783853
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3463719879
Short name T93
Test name
Test status
Simulation time 21042305 ps
CPU time 0.89 seconds
Started Jul 13 04:43:10 PM PDT 24
Finished Jul 13 04:43:11 PM PDT 24
Peak memory 198224 kb
Host smart-d879b9a2-b304-4aac-b141-08395485a3a1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463719879 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3463719879
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.46897404
Short name T765
Test name
Test status
Simulation time 50938880 ps
CPU time 1.18 seconds
Started Jul 13 04:43:05 PM PDT 24
Finished Jul 13 04:43:07 PM PDT 24
Peak memory 198636 kb
Host smart-55072fc2-d2d2-497f-bb83-a462a2a4c161
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46897404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.46897404
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1839139517
Short name T732
Test name
Test status
Simulation time 307311920 ps
CPU time 0.88 seconds
Started Jul 13 04:43:14 PM PDT 24
Finished Jul 13 04:43:15 PM PDT 24
Peak memory 198480 kb
Host smart-ca18af67-e8a4-4273-a6fc-7428addaac5f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839139517 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1839139517
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1083606482
Short name T91
Test name
Test status
Simulation time 24399080 ps
CPU time 0.6 seconds
Started Jul 13 04:43:02 PM PDT 24
Finished Jul 13 04:43:04 PM PDT 24
Peak memory 194312 kb
Host smart-ddd50010-316c-4bdc-8e37-80a10b99b238
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083606482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.1083606482
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1765754846
Short name T796
Test name
Test status
Simulation time 23244742 ps
CPU time 0.59 seconds
Started Jul 13 04:43:03 PM PDT 24
Finished Jul 13 04:43:05 PM PDT 24
Peak memory 194240 kb
Host smart-406d0864-b63c-491d-af8c-29f6ddb0d4d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765754846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1765754846
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1775116386
Short name T95
Test name
Test status
Simulation time 36753220 ps
CPU time 0.91 seconds
Started Jul 13 04:43:04 PM PDT 24
Finished Jul 13 04:43:06 PM PDT 24
Peak memory 197488 kb
Host smart-62159d2f-b66b-43b2-aabc-e01e0cbf7a43
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775116386 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.1775116386
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2381688220
Short name T735
Test name
Test status
Simulation time 1279080520 ps
CPU time 1.85 seconds
Started Jul 13 04:43:05 PM PDT 24
Finished Jul 13 04:43:08 PM PDT 24
Peak memory 198620 kb
Host smart-85b62daa-c1c9-458b-b208-5f2bbb675fdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381688220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2381688220
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.4210425155
Short name T41
Test name
Test status
Simulation time 108597826 ps
CPU time 1.4 seconds
Started Jul 13 04:43:11 PM PDT 24
Finished Jul 13 04:43:13 PM PDT 24
Peak memory 198588 kb
Host smart-4ca83948-9956-40bd-a15d-343129c4cf4d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210425155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.4210425155
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1236297165
Short name T752
Test name
Test status
Simulation time 19631024 ps
CPU time 0.72 seconds
Started Jul 13 04:43:18 PM PDT 24
Finished Jul 13 04:43:21 PM PDT 24
Peak memory 192044 kb
Host smart-fe9ea0db-d99a-4c23-a369-b1a98d741d45
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236297165 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1236297165
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1378163069
Short name T816
Test name
Test status
Simulation time 15829924 ps
CPU time 0.6 seconds
Started Jul 13 04:43:10 PM PDT 24
Finished Jul 13 04:43:11 PM PDT 24
Peak memory 195752 kb
Host smart-5f4c4dd2-1520-43d8-bee6-65a2f94a7d04
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378163069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1378163069
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.1603533923
Short name T749
Test name
Test status
Simulation time 14407507 ps
CPU time 0.63 seconds
Started Jul 13 04:43:19 PM PDT 24
Finished Jul 13 04:43:21 PM PDT 24
Peak memory 194932 kb
Host smart-d67bf509-532c-42d8-b03c-b0b477ea5980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603533923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.1603533923
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.885403474
Short name T847
Test name
Test status
Simulation time 19066261 ps
CPU time 0.71 seconds
Started Jul 13 04:43:24 PM PDT 24
Finished Jul 13 04:43:25 PM PDT 24
Peak memory 195692 kb
Host smart-ba57fd6d-49b6-4392-ba31-5b853be5381d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885403474 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.gpio_same_csr_outstanding.885403474
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.4178647770
Short name T766
Test name
Test status
Simulation time 321308135 ps
CPU time 1.84 seconds
Started Jul 13 04:43:16 PM PDT 24
Finished Jul 13 04:43:19 PM PDT 24
Peak memory 198636 kb
Host smart-8719b307-f311-423f-ba7f-143d90ec4e63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178647770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.4178647770
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1322665866
Short name T42
Test name
Test status
Simulation time 107364817 ps
CPU time 1.37 seconds
Started Jul 13 04:43:16 PM PDT 24
Finished Jul 13 04:43:18 PM PDT 24
Peak memory 198616 kb
Host smart-d6cddb40-d33a-4965-aafa-3c47a87ff54b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322665866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.1322665866
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1431414238
Short name T771
Test name
Test status
Simulation time 50208322 ps
CPU time 0.8 seconds
Started Jul 13 04:43:18 PM PDT 24
Finished Jul 13 04:43:21 PM PDT 24
Peak memory 198424 kb
Host smart-0c45dcbe-ad30-4dcc-bb62-28b6b458344e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431414238 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1431414238
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.974150936
Short name T79
Test name
Test status
Simulation time 35552679 ps
CPU time 0.62 seconds
Started Jul 13 04:43:17 PM PDT 24
Finished Jul 13 04:43:19 PM PDT 24
Peak memory 194932 kb
Host smart-ee2f7a76-1c4f-415f-863a-ba88136b759b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974150936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.974150936
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.2501482172
Short name T788
Test name
Test status
Simulation time 14338374 ps
CPU time 0.6 seconds
Started Jul 13 04:43:18 PM PDT 24
Finished Jul 13 04:43:20 PM PDT 24
Peak memory 194228 kb
Host smart-1c3e32b2-8981-4f46-aaeb-c0f91d03ed6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501482172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.2501482172
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.498404537
Short name T832
Test name
Test status
Simulation time 51060980 ps
CPU time 0.68 seconds
Started Jul 13 04:43:17 PM PDT 24
Finished Jul 13 04:43:19 PM PDT 24
Peak memory 195444 kb
Host smart-982b4874-9b3b-42a1-bdd1-5865090b1c3f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498404537 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.498404537
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1043456302
Short name T774
Test name
Test status
Simulation time 49692424 ps
CPU time 1.18 seconds
Started Jul 13 04:43:23 PM PDT 24
Finished Jul 13 04:43:25 PM PDT 24
Peak memory 198820 kb
Host smart-3e2e3e67-636f-4c49-8909-10ae4237214c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043456302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1043456302
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2959729161
Short name T113
Test name
Test status
Simulation time 107355311 ps
CPU time 0.95 seconds
Started Jul 13 04:43:24 PM PDT 24
Finished Jul 13 04:43:25 PM PDT 24
Peak memory 197892 kb
Host smart-6db11842-c84f-4a7b-aaac-a8edd8c68ca3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959729161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2959729161
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3439416933
Short name T793
Test name
Test status
Simulation time 36444583 ps
CPU time 1.01 seconds
Started Jul 13 04:43:15 PM PDT 24
Finished Jul 13 04:43:17 PM PDT 24
Peak memory 198480 kb
Host smart-6cb41aec-aa1f-478a-a6fe-52b8ab9ebc19
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439416933 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3439416933
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.459983738
Short name T75
Test name
Test status
Simulation time 15615153 ps
CPU time 0.67 seconds
Started Jul 13 04:43:16 PM PDT 24
Finished Jul 13 04:43:17 PM PDT 24
Peak memory 194972 kb
Host smart-84f619da-7b38-4294-8a36-8f99f2066183
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459983738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.459983738
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.2324982001
Short name T751
Test name
Test status
Simulation time 17762463 ps
CPU time 0.66 seconds
Started Jul 13 04:43:16 PM PDT 24
Finished Jul 13 04:43:17 PM PDT 24
Peak memory 194252 kb
Host smart-aa930bcf-55ba-4024-af00-00811f407069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324982001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2324982001
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1167923472
Short name T98
Test name
Test status
Simulation time 92074688 ps
CPU time 0.91 seconds
Started Jul 13 04:43:17 PM PDT 24
Finished Jul 13 04:43:20 PM PDT 24
Peak memory 196780 kb
Host smart-43e69ce8-7765-4874-848c-42bea75551d0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167923472 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.1167923472
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1276392926
Short name T841
Test name
Test status
Simulation time 94808508 ps
CPU time 2.21 seconds
Started Jul 13 04:43:18 PM PDT 24
Finished Jul 13 04:43:22 PM PDT 24
Peak memory 198616 kb
Host smart-b9bc4895-8784-4658-bf7d-d4a1f968d017
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276392926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1276392926
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3498957712
Short name T31
Test name
Test status
Simulation time 75584585 ps
CPU time 0.93 seconds
Started Jul 13 04:43:18 PM PDT 24
Finished Jul 13 04:43:20 PM PDT 24
Peak memory 198100 kb
Host smart-a861cb3a-6392-41d2-9c76-24b3f895f30b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498957712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.3498957712
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.875566138
Short name T837
Test name
Test status
Simulation time 93786576 ps
CPU time 0.72 seconds
Started Jul 13 04:43:17 PM PDT 24
Finished Jul 13 04:43:20 PM PDT 24
Peak memory 192108 kb
Host smart-9073c88c-ecba-446f-9934-a175b2859eb3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875566138 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.875566138
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.290344203
Short name T819
Test name
Test status
Simulation time 54415729 ps
CPU time 0.61 seconds
Started Jul 13 04:43:17 PM PDT 24
Finished Jul 13 04:43:19 PM PDT 24
Peak memory 195232 kb
Host smart-bada95ce-ee2a-48a2-960c-82145c77cfe0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290344203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio
_csr_rw.290344203
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.1827183413
Short name T842
Test name
Test status
Simulation time 28224253 ps
CPU time 0.59 seconds
Started Jul 13 04:43:19 PM PDT 24
Finished Jul 13 04:43:21 PM PDT 24
Peak memory 194200 kb
Host smart-40c7c04d-7025-431d-aff5-79df2600bc90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827183413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1827183413
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1008119346
Short name T101
Test name
Test status
Simulation time 18347367 ps
CPU time 0.69 seconds
Started Jul 13 04:43:16 PM PDT 24
Finished Jul 13 04:43:17 PM PDT 24
Peak memory 196132 kb
Host smart-caf1e31d-a5be-44ca-80a9-1858a995044b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008119346 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1008119346
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.929330839
Short name T813
Test name
Test status
Simulation time 305257302 ps
CPU time 2.9 seconds
Started Jul 13 04:44:25 PM PDT 24
Finished Jul 13 04:44:29 PM PDT 24
Peak memory 197760 kb
Host smart-bcffb7f3-729f-427a-8298-8039f5c56e80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929330839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.929330839
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1103639356
Short name T778
Test name
Test status
Simulation time 57214316 ps
CPU time 0.89 seconds
Started Jul 13 04:43:18 PM PDT 24
Finished Jul 13 04:43:21 PM PDT 24
Peak memory 197680 kb
Host smart-33613ca4-1709-4c8a-91fb-c2f6ee83c530
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103639356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1103639356
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.495068817
Short name T843
Test name
Test status
Simulation time 15510062 ps
CPU time 0.67 seconds
Started Jul 13 04:43:18 PM PDT 24
Finished Jul 13 04:43:21 PM PDT 24
Peak memory 197172 kb
Host smart-b7790db3-3e3b-4e96-9bbb-740599db8c55
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495068817 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.495068817
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3697726179
Short name T748
Test name
Test status
Simulation time 55142412 ps
CPU time 0.61 seconds
Started Jul 13 04:43:16 PM PDT 24
Finished Jul 13 04:43:17 PM PDT 24
Peak memory 195000 kb
Host smart-983b7e2e-9b2b-42da-98c5-e10151cf0eb0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697726179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.3697726179
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.647187274
Short name T830
Test name
Test status
Simulation time 61997416 ps
CPU time 0.65 seconds
Started Jul 13 04:43:17 PM PDT 24
Finished Jul 13 04:43:20 PM PDT 24
Peak memory 194896 kb
Host smart-9f8d0c30-7d2b-4cba-a500-48f0554fe373
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647187274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.647187274
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1630675327
Short name T812
Test name
Test status
Simulation time 28531709 ps
CPU time 0.76 seconds
Started Jul 13 04:43:15 PM PDT 24
Finished Jul 13 04:43:16 PM PDT 24
Peak memory 196552 kb
Host smart-e8681bae-3c17-4ac3-840c-b4c9b7e961d0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630675327 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1630675327
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3546159312
Short name T792
Test name
Test status
Simulation time 129502453 ps
CPU time 2.8 seconds
Started Jul 13 04:43:17 PM PDT 24
Finished Jul 13 04:43:22 PM PDT 24
Peak memory 198584 kb
Host smart-c8e68c9f-565f-4ead-99cf-ef82efffb594
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546159312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3546159312
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.808104226
Short name T40
Test name
Test status
Simulation time 133148379 ps
CPU time 1.51 seconds
Started Jul 13 04:43:17 PM PDT 24
Finished Jul 13 04:43:20 PM PDT 24
Peak memory 198608 kb
Host smart-4785e408-2eb6-4f8e-9bf5-f1c801468aa6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808104226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.gpio_tl_intg_err.808104226
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.315039813
Short name T89
Test name
Test status
Simulation time 111678226 ps
CPU time 0.85 seconds
Started Jul 13 04:42:56 PM PDT 24
Finished Jul 13 04:42:59 PM PDT 24
Peak memory 197268 kb
Host smart-8cb21743-a22f-4bef-a5f0-8bc312a80690
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315039813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.315039813
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.796642413
Short name T90
Test name
Test status
Simulation time 260663057 ps
CPU time 2.4 seconds
Started Jul 13 04:43:00 PM PDT 24
Finished Jul 13 04:43:03 PM PDT 24
Peak memory 197252 kb
Host smart-a779558d-c898-4bf3-8e09-4534a96cff3b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796642413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.796642413
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2542563576
Short name T822
Test name
Test status
Simulation time 57212174 ps
CPU time 0.68 seconds
Started Jul 13 04:42:55 PM PDT 24
Finished Jul 13 04:42:56 PM PDT 24
Peak memory 194988 kb
Host smart-a1d1a6d1-dcec-4258-a6fa-cd578918abfb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542563576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.2542563576
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1974975789
Short name T807
Test name
Test status
Simulation time 159408673 ps
CPU time 1.03 seconds
Started Jul 13 04:42:55 PM PDT 24
Finished Jul 13 04:42:57 PM PDT 24
Peak memory 198492 kb
Host smart-d97cbfa0-cdcb-4510-a828-1ac299ef6c7d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974975789 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1974975789
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3324724495
Short name T805
Test name
Test status
Simulation time 21570012 ps
CPU time 0.61 seconds
Started Jul 13 04:42:57 PM PDT 24
Finished Jul 13 04:42:59 PM PDT 24
Peak memory 195112 kb
Host smart-f7ac596c-3fca-4cba-8ce6-9b7d18359aaa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324724495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.3324724495
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1762322292
Short name T772
Test name
Test status
Simulation time 12634297 ps
CPU time 0.64 seconds
Started Jul 13 04:42:55 PM PDT 24
Finished Jul 13 04:42:58 PM PDT 24
Peak memory 194268 kb
Host smart-fdab202d-9a5a-49a7-baa9-47642059489c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762322292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1762322292
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.548119820
Short name T97
Test name
Test status
Simulation time 199890379 ps
CPU time 0.84 seconds
Started Jul 13 04:43:00 PM PDT 24
Finished Jul 13 04:43:01 PM PDT 24
Peak memory 196856 kb
Host smart-b1ce02a6-39ba-4333-beff-7fe9a75a0eae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548119820 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.gpio_same_csr_outstanding.548119820
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2269387841
Short name T773
Test name
Test status
Simulation time 46510941 ps
CPU time 2.5 seconds
Started Jul 13 04:42:57 PM PDT 24
Finished Jul 13 04:43:01 PM PDT 24
Peak memory 198636 kb
Host smart-47ba436a-c9fe-4a06-9dde-e56c8b45a3a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269387841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2269387841
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.292293215
Short name T846
Test name
Test status
Simulation time 116116902 ps
CPU time 1.52 seconds
Started Jul 13 04:42:54 PM PDT 24
Finished Jul 13 04:42:56 PM PDT 24
Peak memory 198632 kb
Host smart-3e64531d-2533-4280-a736-f8a75eccbd4c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292293215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.292293215
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.1611044148
Short name T753
Test name
Test status
Simulation time 13585982 ps
CPU time 0.67 seconds
Started Jul 13 04:43:23 PM PDT 24
Finished Jul 13 04:43:24 PM PDT 24
Peak memory 194652 kb
Host smart-8b74a65e-f511-4607-aaaf-e2560c9b40c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611044148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.1611044148
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2668615754
Short name T776
Test name
Test status
Simulation time 23319591 ps
CPU time 0.61 seconds
Started Jul 13 04:43:16 PM PDT 24
Finished Jul 13 04:43:18 PM PDT 24
Peak memory 194212 kb
Host smart-307f4121-68dc-4238-b61f-4cca1528a400
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668615754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2668615754
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.615776805
Short name T782
Test name
Test status
Simulation time 13811938 ps
CPU time 0.62 seconds
Started Jul 13 04:43:16 PM PDT 24
Finished Jul 13 04:43:17 PM PDT 24
Peak memory 194268 kb
Host smart-3b586c60-826a-4007-8a59-4583e7e6320b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615776805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.615776805
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.3986761080
Short name T811
Test name
Test status
Simulation time 38339824 ps
CPU time 0.63 seconds
Started Jul 13 04:43:16 PM PDT 24
Finished Jul 13 04:43:18 PM PDT 24
Peak memory 194268 kb
Host smart-08dcad3f-8502-481b-978e-76d2b77d8277
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986761080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3986761080
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.4264411043
Short name T824
Test name
Test status
Simulation time 38100963 ps
CPU time 0.58 seconds
Started Jul 13 04:43:17 PM PDT 24
Finished Jul 13 04:43:20 PM PDT 24
Peak memory 194896 kb
Host smart-ad5ab5d2-46c9-4a8c-b523-4630babb0cfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264411043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.4264411043
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.3288202448
Short name T827
Test name
Test status
Simulation time 14092127 ps
CPU time 0.6 seconds
Started Jul 13 04:43:16 PM PDT 24
Finished Jul 13 04:43:18 PM PDT 24
Peak memory 194868 kb
Host smart-7249ca11-3bb3-4457-bf12-a3e21da20a64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288202448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3288202448
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.563293337
Short name T755
Test name
Test status
Simulation time 34921671 ps
CPU time 0.58 seconds
Started Jul 13 04:43:18 PM PDT 24
Finished Jul 13 04:43:20 PM PDT 24
Peak memory 194228 kb
Host smart-918ec8a8-b3cd-4606-a807-7953cc8cc84d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563293337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.563293337
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.4138092479
Short name T738
Test name
Test status
Simulation time 17765904 ps
CPU time 0.66 seconds
Started Jul 13 04:43:17 PM PDT 24
Finished Jul 13 04:43:20 PM PDT 24
Peak memory 194976 kb
Host smart-6469f065-3d83-4a34-9660-05cb035e3c17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138092479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.4138092479
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.525183104
Short name T767
Test name
Test status
Simulation time 27724000 ps
CPU time 0.6 seconds
Started Jul 13 04:43:16 PM PDT 24
Finished Jul 13 04:43:18 PM PDT 24
Peak memory 194316 kb
Host smart-e22a786d-523a-4d80-8aef-a876634ad6de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525183104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.525183104
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2199928852
Short name T808
Test name
Test status
Simulation time 13099905 ps
CPU time 0.62 seconds
Started Jul 13 04:43:18 PM PDT 24
Finished Jul 13 04:43:21 PM PDT 24
Peak memory 194280 kb
Host smart-92fde698-1af4-459b-a25d-833e55034f66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199928852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2199928852
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.870105242
Short name T839
Test name
Test status
Simulation time 123838686 ps
CPU time 0.87 seconds
Started Jul 13 04:43:04 PM PDT 24
Finished Jul 13 04:43:06 PM PDT 24
Peak memory 196896 kb
Host smart-983b93ae-6e09-4da6-9c1a-75f9603a1c02
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870105242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.870105242
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2234557321
Short name T86
Test name
Test status
Simulation time 126332292 ps
CPU time 1.44 seconds
Started Jul 13 04:42:55 PM PDT 24
Finished Jul 13 04:42:58 PM PDT 24
Peak memory 197452 kb
Host smart-565a1b47-e07a-4576-87db-afa426cc4c6b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234557321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2234557321
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.4286755458
Short name T781
Test name
Test status
Simulation time 17243495 ps
CPU time 0.72 seconds
Started Jul 13 04:42:56 PM PDT 24
Finished Jul 13 04:42:58 PM PDT 24
Peak memory 195308 kb
Host smart-205b848b-e65e-4b9c-b19b-b26e2e3f20b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286755458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.4286755458
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3018346854
Short name T760
Test name
Test status
Simulation time 122473701 ps
CPU time 1.56 seconds
Started Jul 13 04:42:59 PM PDT 24
Finished Jul 13 04:43:01 PM PDT 24
Peak memory 198660 kb
Host smart-c537408f-a93e-4aae-bfad-5a3e16a96823
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018346854 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3018346854
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2223201863
Short name T836
Test name
Test status
Simulation time 49038717 ps
CPU time 0.66 seconds
Started Jul 13 04:42:58 PM PDT 24
Finished Jul 13 04:43:00 PM PDT 24
Peak memory 195820 kb
Host smart-c6969016-4704-4153-b7df-e417f22b468c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223201863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2223201863
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2311884623
Short name T820
Test name
Test status
Simulation time 22375681 ps
CPU time 0.63 seconds
Started Jul 13 04:42:56 PM PDT 24
Finished Jul 13 04:42:58 PM PDT 24
Peak memory 194232 kb
Host smart-3d86a1ef-9274-45a1-a74d-3742c8b30d30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311884623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2311884623
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2710456915
Short name T78
Test name
Test status
Simulation time 19019877 ps
CPU time 0.65 seconds
Started Jul 13 04:42:54 PM PDT 24
Finished Jul 13 04:42:55 PM PDT 24
Peak memory 195220 kb
Host smart-4c6b5dff-25c1-4ec0-ae45-f16bb201fec3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710456915 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.2710456915
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3902506529
Short name T828
Test name
Test status
Simulation time 84355034 ps
CPU time 2.27 seconds
Started Jul 13 04:42:55 PM PDT 24
Finished Jul 13 04:42:59 PM PDT 24
Peak memory 198632 kb
Host smart-43b30dcd-7d66-456a-890e-da5117a7f7c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902506529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3902506529
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2366091229
Short name T114
Test name
Test status
Simulation time 240846970 ps
CPU time 1.46 seconds
Started Jul 13 04:43:00 PM PDT 24
Finished Jul 13 04:43:02 PM PDT 24
Peak memory 198596 kb
Host smart-460277ce-14b8-4443-8b28-3b174ccfda2e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366091229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.2366091229
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.843098801
Short name T744
Test name
Test status
Simulation time 59384656 ps
CPU time 0.62 seconds
Started Jul 13 04:43:18 PM PDT 24
Finished Jul 13 04:43:20 PM PDT 24
Peak memory 194252 kb
Host smart-d1a3f341-51a2-452b-b3b6-405e8e12170c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843098801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.843098801
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2656904614
Short name T800
Test name
Test status
Simulation time 18368765 ps
CPU time 0.64 seconds
Started Jul 13 04:43:28 PM PDT 24
Finished Jul 13 04:43:31 PM PDT 24
Peak memory 194940 kb
Host smart-af12a477-4d32-441d-9963-714b89a5afd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656904614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2656904614
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1959517342
Short name T728
Test name
Test status
Simulation time 58124427 ps
CPU time 0.62 seconds
Started Jul 13 04:43:26 PM PDT 24
Finished Jul 13 04:43:28 PM PDT 24
Peak memory 194164 kb
Host smart-96cc745c-6702-4278-9b9a-1339cf1aac97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959517342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1959517342
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1372794995
Short name T785
Test name
Test status
Simulation time 30177838 ps
CPU time 0.62 seconds
Started Jul 13 04:43:28 PM PDT 24
Finished Jul 13 04:43:32 PM PDT 24
Peak memory 194188 kb
Host smart-41116c6c-6945-460c-824f-7e25562809bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372794995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1372794995
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.3150041004
Short name T754
Test name
Test status
Simulation time 20395724 ps
CPU time 0.58 seconds
Started Jul 13 04:43:31 PM PDT 24
Finished Jul 13 04:43:33 PM PDT 24
Peak memory 194232 kb
Host smart-0b27a42a-0085-4915-acca-247a3b47b848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150041004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3150041004
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1239977027
Short name T784
Test name
Test status
Simulation time 30549047 ps
CPU time 0.59 seconds
Started Jul 13 04:43:28 PM PDT 24
Finished Jul 13 04:43:31 PM PDT 24
Peak memory 194256 kb
Host smart-b62bce5d-a5c2-4454-8176-c5d8c65e461d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239977027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1239977027
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2882531006
Short name T783
Test name
Test status
Simulation time 17612125 ps
CPU time 0.62 seconds
Started Jul 13 04:43:26 PM PDT 24
Finished Jul 13 04:43:28 PM PDT 24
Peak memory 194340 kb
Host smart-e80b7a9b-bdfc-48ff-8b11-a5d1d48b8343
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882531006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2882531006
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1632581231
Short name T758
Test name
Test status
Simulation time 10698884 ps
CPU time 0.6 seconds
Started Jul 13 04:43:26 PM PDT 24
Finished Jul 13 04:43:28 PM PDT 24
Peak memory 194228 kb
Host smart-814dfa70-a060-4693-8263-b2c9e5b8fedb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632581231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1632581231
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2065428195
Short name T730
Test name
Test status
Simulation time 45543388 ps
CPU time 0.57 seconds
Started Jul 13 04:44:49 PM PDT 24
Finished Jul 13 04:44:51 PM PDT 24
Peak memory 194408 kb
Host smart-7a68b4b0-94ff-469e-8c0c-bfb9c713a5d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065428195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2065428195
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.2912516613
Short name T770
Test name
Test status
Simulation time 18501840 ps
CPU time 0.63 seconds
Started Jul 13 04:43:26 PM PDT 24
Finished Jul 13 04:43:28 PM PDT 24
Peak memory 194280 kb
Host smart-eda27739-0cf2-4761-bf1f-49662ba90df1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912516613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.2912516613
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.4163925118
Short name T77
Test name
Test status
Simulation time 80575007 ps
CPU time 0.76 seconds
Started Jul 13 04:42:56 PM PDT 24
Finished Jul 13 04:42:58 PM PDT 24
Peak memory 196824 kb
Host smart-a8766985-8b69-487f-add4-1ba530ea8dc4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163925118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.4163925118
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2088829485
Short name T741
Test name
Test status
Simulation time 800991886 ps
CPU time 1.51 seconds
Started Jul 13 04:42:55 PM PDT 24
Finished Jul 13 04:42:58 PM PDT 24
Peak memory 198580 kb
Host smart-31aa233d-615d-4d51-b9bb-b53a766a8d9b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088829485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2088829485
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.346451236
Short name T88
Test name
Test status
Simulation time 15479343 ps
CPU time 0.62 seconds
Started Jul 13 04:42:57 PM PDT 24
Finished Jul 13 04:42:59 PM PDT 24
Peak memory 194920 kb
Host smart-0c3d6b88-352c-4edc-9506-4e6e3ec462e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346451236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.346451236
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3013856551
Short name T840
Test name
Test status
Simulation time 168205342 ps
CPU time 1.2 seconds
Started Jul 13 04:43:00 PM PDT 24
Finished Jul 13 04:43:02 PM PDT 24
Peak memory 198976 kb
Host smart-0c06fe58-b416-437f-b641-878a56206409
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013856551 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3013856551
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2656353632
Short name T780
Test name
Test status
Simulation time 24154366 ps
CPU time 0.64 seconds
Started Jul 13 04:42:55 PM PDT 24
Finished Jul 13 04:42:56 PM PDT 24
Peak memory 195920 kb
Host smart-01e51f38-e481-4587-abb2-be2f14d2c181
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656353632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2656353632
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.2572364591
Short name T734
Test name
Test status
Simulation time 37360502 ps
CPU time 0.66 seconds
Started Jul 13 04:42:59 PM PDT 24
Finished Jul 13 04:43:01 PM PDT 24
Peak memory 195000 kb
Host smart-f8d75dc2-444e-4ddc-a7f4-ad368755bd4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572364591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2572364591
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3370424237
Short name T96
Test name
Test status
Simulation time 50334346 ps
CPU time 0.71 seconds
Started Jul 13 04:42:56 PM PDT 24
Finished Jul 13 04:42:58 PM PDT 24
Peak memory 195276 kb
Host smart-71413f4c-2812-4fed-95a9-92149a58db2f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370424237 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.3370424237
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.481550474
Short name T762
Test name
Test status
Simulation time 100848582 ps
CPU time 2.77 seconds
Started Jul 13 04:42:56 PM PDT 24
Finished Jul 13 04:43:01 PM PDT 24
Peak memory 198464 kb
Host smart-30103283-cd41-4228-8962-e88d4af53839
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481550474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.481550474
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.711803736
Short name T746
Test name
Test status
Simulation time 57721033 ps
CPU time 0.59 seconds
Started Jul 13 04:43:29 PM PDT 24
Finished Jul 13 04:43:32 PM PDT 24
Peak memory 194260 kb
Host smart-bc06e6d9-b787-417b-b2a0-4c500f101e85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711803736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.711803736
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.866433137
Short name T743
Test name
Test status
Simulation time 39504878 ps
CPU time 0.6 seconds
Started Jul 13 04:43:27 PM PDT 24
Finished Jul 13 04:43:29 PM PDT 24
Peak memory 194252 kb
Host smart-f1060057-3006-416f-a2b2-427466f9de38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866433137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.866433137
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3984096185
Short name T801
Test name
Test status
Simulation time 20624032 ps
CPU time 0.62 seconds
Started Jul 13 04:43:26 PM PDT 24
Finished Jul 13 04:43:29 PM PDT 24
Peak memory 194312 kb
Host smart-1a3d004e-a31c-4004-a0a1-928213f7db8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984096185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3984096185
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2266396578
Short name T814
Test name
Test status
Simulation time 46215272 ps
CPU time 0.59 seconds
Started Jul 13 04:43:26 PM PDT 24
Finished Jul 13 04:43:29 PM PDT 24
Peak memory 194192 kb
Host smart-e1e7f67a-3a1c-49d6-afc4-3dd7f5f2e48d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266396578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2266396578
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.2886128850
Short name T797
Test name
Test status
Simulation time 59656086 ps
CPU time 0.65 seconds
Started Jul 13 04:43:27 PM PDT 24
Finished Jul 13 04:43:30 PM PDT 24
Peak memory 194324 kb
Host smart-5dcba432-8221-4d92-a2cf-77539a8ca09a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886128850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.2886128850
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2376139273
Short name T799
Test name
Test status
Simulation time 13140487 ps
CPU time 0.62 seconds
Started Jul 13 04:43:25 PM PDT 24
Finished Jul 13 04:43:26 PM PDT 24
Peak memory 194260 kb
Host smart-498643e7-0a35-410e-ad8b-ac0171046177
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376139273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2376139273
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.3102810584
Short name T768
Test name
Test status
Simulation time 27534213 ps
CPU time 0.62 seconds
Started Jul 13 04:43:28 PM PDT 24
Finished Jul 13 04:43:32 PM PDT 24
Peak memory 194248 kb
Host smart-6826ea99-7248-46bf-9ffd-f608c0b1e909
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102810584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.3102810584
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.529546210
Short name T777
Test name
Test status
Simulation time 33262964 ps
CPU time 0.64 seconds
Started Jul 13 04:43:28 PM PDT 24
Finished Jul 13 04:43:32 PM PDT 24
Peak memory 194876 kb
Host smart-0701ba0f-36fc-4dc7-bd30-3a923b721611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529546210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.529546210
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3130593143
Short name T740
Test name
Test status
Simulation time 11996576 ps
CPU time 0.63 seconds
Started Jul 13 04:43:27 PM PDT 24
Finished Jul 13 04:43:30 PM PDT 24
Peak memory 194252 kb
Host smart-1a79ed5d-8746-4f99-8d85-d7dc683a7511
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130593143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3130593143
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2762292494
Short name T779
Test name
Test status
Simulation time 182224586 ps
CPU time 0.62 seconds
Started Jul 13 04:43:26 PM PDT 24
Finished Jul 13 04:43:28 PM PDT 24
Peak memory 194960 kb
Host smart-57f347c3-93c2-44a7-8e0d-72cc54739f78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762292494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2762292494
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1448652364
Short name T736
Test name
Test status
Simulation time 23669054 ps
CPU time 1.15 seconds
Started Jul 13 04:42:56 PM PDT 24
Finished Jul 13 04:42:59 PM PDT 24
Peak memory 198648 kb
Host smart-f519061e-fb0f-49ee-b20f-eb2ca53144f1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448652364 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1448652364
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2893161944
Short name T803
Test name
Test status
Simulation time 11625437 ps
CPU time 0.63 seconds
Started Jul 13 04:42:55 PM PDT 24
Finished Jul 13 04:42:56 PM PDT 24
Peak memory 195456 kb
Host smart-fa76ddd8-70fa-431f-a547-2ef044b67cf9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893161944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.2893161944
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.4048466337
Short name T844
Test name
Test status
Simulation time 14084926 ps
CPU time 0.67 seconds
Started Jul 13 04:42:56 PM PDT 24
Finished Jul 13 04:42:58 PM PDT 24
Peak memory 194960 kb
Host smart-91020b05-3d7f-4322-a149-a25daa646457
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048466337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.4048466337
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2712327477
Short name T831
Test name
Test status
Simulation time 147708648 ps
CPU time 0.87 seconds
Started Jul 13 04:42:54 PM PDT 24
Finished Jul 13 04:42:56 PM PDT 24
Peak memory 196972 kb
Host smart-788352b4-a9e4-466d-88f0-0836c757b0aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712327477 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.2712327477
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3297105324
Short name T756
Test name
Test status
Simulation time 803206126 ps
CPU time 1.22 seconds
Started Jul 13 04:42:56 PM PDT 24
Finished Jul 13 04:42:59 PM PDT 24
Peak memory 198616 kb
Host smart-44312e81-6ad1-480d-98b7-c36f5ed9a8e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297105324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3297105324
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1942071482
Short name T791
Test name
Test status
Simulation time 1133626557 ps
CPU time 1.16 seconds
Started Jul 13 04:42:54 PM PDT 24
Finished Jul 13 04:42:56 PM PDT 24
Peak memory 198600 kb
Host smart-ecbf12f9-34dd-4e18-8ded-e386ce60fc8d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942071482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.1942071482
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3402020720
Short name T786
Test name
Test status
Simulation time 24303261 ps
CPU time 0.78 seconds
Started Jul 13 04:42:55 PM PDT 24
Finished Jul 13 04:42:57 PM PDT 24
Peak memory 198508 kb
Host smart-ff2deab6-f824-4a5e-97f9-0d6aaf306041
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402020720 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.3402020720
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3100138515
Short name T84
Test name
Test status
Simulation time 11375275 ps
CPU time 0.57 seconds
Started Jul 13 04:42:55 PM PDT 24
Finished Jul 13 04:42:58 PM PDT 24
Peak memory 193816 kb
Host smart-2853591c-ee34-4a8c-bff9-0594c0a814ec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100138515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3100138515
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3812538058
Short name T725
Test name
Test status
Simulation time 25206324 ps
CPU time 0.58 seconds
Started Jul 13 04:42:55 PM PDT 24
Finished Jul 13 04:42:56 PM PDT 24
Peak memory 194252 kb
Host smart-ea1f09fe-a3eb-4eba-aee0-653225d24d60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812538058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3812538058
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.971557365
Short name T100
Test name
Test status
Simulation time 118618546 ps
CPU time 0.82 seconds
Started Jul 13 04:42:55 PM PDT 24
Finished Jul 13 04:42:57 PM PDT 24
Peak memory 197560 kb
Host smart-3619fb57-01b1-4b35-b7d9-83d5c397b5ab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971557365 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.971557365
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2459492400
Short name T804
Test name
Test status
Simulation time 47126405 ps
CPU time 2.38 seconds
Started Jul 13 04:42:55 PM PDT 24
Finished Jul 13 04:42:59 PM PDT 24
Peak memory 198632 kb
Host smart-7a1aa400-aaab-48e2-a695-a8762a29cf41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459492400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2459492400
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1014145453
Short name T45
Test name
Test status
Simulation time 161599726 ps
CPU time 0.87 seconds
Started Jul 13 04:43:03 PM PDT 24
Finished Jul 13 04:43:05 PM PDT 24
Peak memory 197748 kb
Host smart-f65a4dec-8587-4e9e-a425-3772461fec1d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014145453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1014145453
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1122116148
Short name T810
Test name
Test status
Simulation time 15932730 ps
CPU time 0.66 seconds
Started Jul 13 04:42:58 PM PDT 24
Finished Jul 13 04:43:00 PM PDT 24
Peak memory 197840 kb
Host smart-41e633d7-9ab4-4571-886d-7e7fca83f338
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122116148 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1122116148
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1148819536
Short name T92
Test name
Test status
Simulation time 21317727 ps
CPU time 0.61 seconds
Started Jul 13 04:42:57 PM PDT 24
Finished Jul 13 04:42:59 PM PDT 24
Peak memory 194964 kb
Host smart-0099a3d9-8110-42bb-b484-8a88d179492e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148819536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1148819536
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2050863964
Short name T833
Test name
Test status
Simulation time 18790642 ps
CPU time 0.63 seconds
Started Jul 13 04:42:56 PM PDT 24
Finished Jul 13 04:42:58 PM PDT 24
Peak memory 194960 kb
Host smart-ce94dcb0-4c38-4fff-b89a-9ce7208a857a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050863964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2050863964
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1663390537
Short name T809
Test name
Test status
Simulation time 30084638 ps
CPU time 0.83 seconds
Started Jul 13 04:43:00 PM PDT 24
Finished Jul 13 04:43:02 PM PDT 24
Peak memory 197364 kb
Host smart-14a17380-92bb-4f20-a711-408da95f7382
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663390537 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1663390537
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1103016345
Short name T739
Test name
Test status
Simulation time 130243541 ps
CPU time 2.99 seconds
Started Jul 13 04:42:58 PM PDT 24
Finished Jul 13 04:43:02 PM PDT 24
Peak memory 198624 kb
Host smart-b869c458-c87e-4cdd-b3df-ee991a340f38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103016345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.1103016345
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1613075755
Short name T818
Test name
Test status
Simulation time 56266306 ps
CPU time 0.91 seconds
Started Jul 13 04:42:58 PM PDT 24
Finished Jul 13 04:43:00 PM PDT 24
Peak memory 198148 kb
Host smart-bd124b61-4e6b-4760-b6bc-e82d5fae5c28
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613075755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1613075755
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1807427835
Short name T731
Test name
Test status
Simulation time 28654709 ps
CPU time 0.85 seconds
Started Jul 13 04:43:05 PM PDT 24
Finished Jul 13 04:43:07 PM PDT 24
Peak memory 198492 kb
Host smart-a647458c-993c-4355-adf1-44ecce71b351
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807427835 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.1807427835
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1228643118
Short name T76
Test name
Test status
Simulation time 15421773 ps
CPU time 0.68 seconds
Started Jul 13 04:43:02 PM PDT 24
Finished Jul 13 04:43:03 PM PDT 24
Peak memory 195284 kb
Host smart-94705a92-48ca-493c-ac5d-8b44b63db26b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228643118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.1228643118
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.283226734
Short name T821
Test name
Test status
Simulation time 13250068 ps
CPU time 0.59 seconds
Started Jul 13 04:43:04 PM PDT 24
Finished Jul 13 04:43:05 PM PDT 24
Peak memory 194252 kb
Host smart-a5bc4c28-c802-45c3-8d4a-590e6bda3c48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283226734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.283226734
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1116321680
Short name T826
Test name
Test status
Simulation time 38506077 ps
CPU time 0.7 seconds
Started Jul 13 04:43:03 PM PDT 24
Finished Jul 13 04:43:05 PM PDT 24
Peak memory 195412 kb
Host smart-c2adfcab-2180-47b9-b290-d4b0cd7870d2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116321680 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1116321680
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.4194523201
Short name T737
Test name
Test status
Simulation time 379487667 ps
CPU time 2.24 seconds
Started Jul 13 04:43:04 PM PDT 24
Finished Jul 13 04:43:08 PM PDT 24
Peak memory 198504 kb
Host smart-57efc38e-a3b9-4673-a675-4a3d44b483e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194523201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.4194523201
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1372813434
Short name T44
Test name
Test status
Simulation time 346388602 ps
CPU time 1.48 seconds
Started Jul 13 04:43:03 PM PDT 24
Finished Jul 13 04:43:05 PM PDT 24
Peak memory 198640 kb
Host smart-4c3d87ea-63e7-45d8-afe6-160bd3ac4b97
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372813434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1372813434
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.4159249690
Short name T745
Test name
Test status
Simulation time 24653523 ps
CPU time 0.81 seconds
Started Jul 13 04:43:02 PM PDT 24
Finished Jul 13 04:43:03 PM PDT 24
Peak memory 198504 kb
Host smart-4c3ed7da-4934-42b9-bd79-7a6e368ee158
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159249690 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.4159249690
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.449041562
Short name T789
Test name
Test status
Simulation time 15116723 ps
CPU time 0.64 seconds
Started Jul 13 04:43:09 PM PDT 24
Finished Jul 13 04:43:10 PM PDT 24
Peak memory 195176 kb
Host smart-0d1f673f-1f28-477e-b600-eaef3f764688
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449041562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_
csr_rw.449041562
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.967955138
Short name T806
Test name
Test status
Simulation time 45495307 ps
CPU time 0.6 seconds
Started Jul 13 04:43:08 PM PDT 24
Finished Jul 13 04:43:09 PM PDT 24
Peak memory 194252 kb
Host smart-cc294726-d00b-48e3-9a8b-cac9f4cbc154
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967955138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.967955138
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2045745047
Short name T99
Test name
Test status
Simulation time 221972951 ps
CPU time 0.93 seconds
Started Jul 13 04:43:13 PM PDT 24
Finished Jul 13 04:43:14 PM PDT 24
Peak memory 196752 kb
Host smart-4db69242-0354-4864-82be-6d623b9a29f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045745047 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2045745047
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3071304259
Short name T763
Test name
Test status
Simulation time 812488430 ps
CPU time 1.99 seconds
Started Jul 13 04:43:05 PM PDT 24
Finished Jul 13 04:43:08 PM PDT 24
Peak memory 198596 kb
Host smart-f50711d6-8de0-4b88-a756-dfdeb3fa2fc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071304259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3071304259
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3222877038
Short name T46
Test name
Test status
Simulation time 120377378 ps
CPU time 1.56 seconds
Started Jul 13 04:43:03 PM PDT 24
Finished Jul 13 04:43:05 PM PDT 24
Peak memory 198604 kb
Host smart-d829300a-31b1-4ba3-943d-9d3a52e16072
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222877038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3222877038
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.303850248
Short name T161
Test name
Test status
Simulation time 44810983 ps
CPU time 0.56 seconds
Started Jul 13 04:48:22 PM PDT 24
Finished Jul 13 04:48:25 PM PDT 24
Peak memory 194148 kb
Host smart-1eb9a615-3861-46c9-8c20-2ef13fece75a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303850248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.303850248
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3648107578
Short name T456
Test name
Test status
Simulation time 125845895 ps
CPU time 0.79 seconds
Started Jul 13 04:48:28 PM PDT 24
Finished Jul 13 04:48:31 PM PDT 24
Peak memory 195900 kb
Host smart-42b7e2e0-e6e9-499f-aefa-4e63cf3ff25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648107578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3648107578
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3032975832
Short name T120
Test name
Test status
Simulation time 667181254 ps
CPU time 10.86 seconds
Started Jul 13 04:48:23 PM PDT 24
Finished Jul 13 04:48:36 PM PDT 24
Peak memory 198564 kb
Host smart-61de0d14-ff5e-4f68-b5f8-c898c2ab7c87
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032975832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3032975832
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.3154281670
Short name T140
Test name
Test status
Simulation time 189776013 ps
CPU time 0.75 seconds
Started Jul 13 04:48:26 PM PDT 24
Finished Jul 13 04:48:29 PM PDT 24
Peak memory 196456 kb
Host smart-ddfcbccf-c3cf-485e-8e94-17a1d7aeed59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154281670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3154281670
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2182889539
Short name T202
Test name
Test status
Simulation time 20958695 ps
CPU time 0.77 seconds
Started Jul 13 04:48:25 PM PDT 24
Finished Jul 13 04:48:28 PM PDT 24
Peak memory 196128 kb
Host smart-1c0502a3-1b27-4171-8e15-647853f33f92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182889539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2182889539
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1150522701
Short name T651
Test name
Test status
Simulation time 93850485 ps
CPU time 3.5 seconds
Started Jul 13 04:48:23 PM PDT 24
Finished Jul 13 04:48:28 PM PDT 24
Peak memory 198600 kb
Host smart-e5e66016-2edd-462f-afa6-acb1d4f7fd7d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150522701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1150522701
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.4098184485
Short name T218
Test name
Test status
Simulation time 451813000 ps
CPU time 3.23 seconds
Started Jul 13 04:48:24 PM PDT 24
Finished Jul 13 04:48:30 PM PDT 24
Peak memory 197656 kb
Host smart-ffc599d5-4e15-49c5-acaa-a3f036a394a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098184485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
4098184485
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.777999476
Short name T328
Test name
Test status
Simulation time 46021270 ps
CPU time 1.13 seconds
Started Jul 13 04:48:18 PM PDT 24
Finished Jul 13 04:48:22 PM PDT 24
Peak memory 196388 kb
Host smart-973d0c96-c2ed-46a5-a8e2-b2581e1ed169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777999476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.777999476
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1419584280
Short name T718
Test name
Test status
Simulation time 113755290 ps
CPU time 0.71 seconds
Started Jul 13 04:48:23 PM PDT 24
Finished Jul 13 04:48:26 PM PDT 24
Peak memory 195648 kb
Host smart-a4fa5996-429f-4984-92ee-9d2f309944c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419584280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.1419584280
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.3721703756
Short name T358
Test name
Test status
Simulation time 265495614 ps
CPU time 3.29 seconds
Started Jul 13 04:48:23 PM PDT 24
Finished Jul 13 04:48:28 PM PDT 24
Peak memory 198640 kb
Host smart-f0775b07-9c75-4492-8a45-c9fc3f5ea30d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721703756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.3721703756
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.208568009
Short name T35
Test name
Test status
Simulation time 44026719 ps
CPU time 0.84 seconds
Started Jul 13 04:48:27 PM PDT 24
Finished Jul 13 04:48:30 PM PDT 24
Peak memory 214204 kb
Host smart-2fe83717-0bc5-4e0c-8a5b-d3483c4424a2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208568009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.208568009
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.2814144620
Short name T117
Test name
Test status
Simulation time 49928769 ps
CPU time 1.26 seconds
Started Jul 13 04:48:18 PM PDT 24
Finished Jul 13 04:48:22 PM PDT 24
Peak memory 197404 kb
Host smart-07818e91-465e-4d64-abe8-a976a2920ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814144620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.2814144620
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2246778946
Short name T314
Test name
Test status
Simulation time 41741130 ps
CPU time 0.93 seconds
Started Jul 13 04:48:19 PM PDT 24
Finished Jul 13 04:48:22 PM PDT 24
Peak memory 197032 kb
Host smart-6e66c106-579e-4038-89bd-e9716a167dad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246778946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2246778946
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1329645666
Short name T499
Test name
Test status
Simulation time 4072905051 ps
CPU time 124.91 seconds
Started Jul 13 04:48:33 PM PDT 24
Finished Jul 13 04:50:40 PM PDT 24
Peak memory 199056 kb
Host smart-468b774b-6ab7-4f13-b6f3-c523fb03b517
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329645666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1329645666
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2203300030
Short name T634
Test name
Test status
Simulation time 29475389 ps
CPU time 0.57 seconds
Started Jul 13 04:48:21 PM PDT 24
Finished Jul 13 04:48:24 PM PDT 24
Peak memory 194832 kb
Host smart-8603651b-d151-4df2-9f9a-8d38124d8f12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203300030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2203300030
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1917904729
Short name T594
Test name
Test status
Simulation time 316154713 ps
CPU time 0.64 seconds
Started Jul 13 04:48:24 PM PDT 24
Finished Jul 13 04:48:28 PM PDT 24
Peak memory 194636 kb
Host smart-949a71f5-adf3-4ea3-9858-99e833f8e81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917904729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1917904729
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.71528799
Short name T706
Test name
Test status
Simulation time 234348490 ps
CPU time 12.28 seconds
Started Jul 13 04:48:22 PM PDT 24
Finished Jul 13 04:48:36 PM PDT 24
Peak memory 198668 kb
Host smart-efb54320-cadf-411f-9743-0745ff617857
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71528799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress.71528799
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1035238273
Short name T371
Test name
Test status
Simulation time 65546632 ps
CPU time 0.66 seconds
Started Jul 13 04:48:21 PM PDT 24
Finished Jul 13 04:48:24 PM PDT 24
Peak memory 194868 kb
Host smart-98996857-d58b-4a08-8218-bb2a78305528
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035238273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1035238273
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.2859032668
Short name T538
Test name
Test status
Simulation time 384564756 ps
CPU time 1.2 seconds
Started Jul 13 04:48:25 PM PDT 24
Finished Jul 13 04:48:29 PM PDT 24
Peak memory 196364 kb
Host smart-9914e09b-7628-4a46-8537-e965863d34d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859032668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.2859032668
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2563301883
Short name T562
Test name
Test status
Simulation time 43612161 ps
CPU time 1.14 seconds
Started Jul 13 04:48:23 PM PDT 24
Finished Jul 13 04:48:27 PM PDT 24
Peak memory 196928 kb
Host smart-d7e2cc8b-fb8d-488d-a712-72b75dc70460
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563301883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2563301883
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2289559006
Short name T697
Test name
Test status
Simulation time 170678912 ps
CPU time 2.76 seconds
Started Jul 13 04:48:25 PM PDT 24
Finished Jul 13 04:48:31 PM PDT 24
Peak memory 198692 kb
Host smart-e4ce0888-7417-4c9e-afbe-98753b108464
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289559006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2289559006
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.213898905
Short name T26
Test name
Test status
Simulation time 24934789 ps
CPU time 0.91 seconds
Started Jul 13 04:48:24 PM PDT 24
Finished Jul 13 04:48:27 PM PDT 24
Peak memory 196468 kb
Host smart-23f75205-652b-4791-94db-be96681e6d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213898905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.213898905
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.457282016
Short name T305
Test name
Test status
Simulation time 30656213 ps
CPU time 1.1 seconds
Started Jul 13 04:48:27 PM PDT 24
Finished Jul 13 04:48:30 PM PDT 24
Peak memory 196756 kb
Host smart-9da41977-d308-4665-a0da-ea33fe588b34
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457282016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.457282016
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3620782632
Short name T522
Test name
Test status
Simulation time 446369648 ps
CPU time 5.41 seconds
Started Jul 13 04:48:24 PM PDT 24
Finished Jul 13 04:48:33 PM PDT 24
Peak memory 198604 kb
Host smart-c93ff9f3-679c-4ee1-98ab-a2c397604a42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620782632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.3620782632
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.1522538607
Short name T48
Test name
Test status
Simulation time 136758082 ps
CPU time 0.81 seconds
Started Jul 13 04:48:27 PM PDT 24
Finished Jul 13 04:48:30 PM PDT 24
Peak memory 214184 kb
Host smart-f39fdefd-d352-4f1e-ab7f-b10be2eab020
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522538607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.1522538607
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.3170064644
Short name T533
Test name
Test status
Simulation time 133758958 ps
CPU time 0.98 seconds
Started Jul 13 04:48:22 PM PDT 24
Finished Jul 13 04:48:25 PM PDT 24
Peak memory 197068 kb
Host smart-555e6b0d-8adb-4e27-b88f-73a1a91bd789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170064644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3170064644
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3321379352
Short name T151
Test name
Test status
Simulation time 89429989 ps
CPU time 1.11 seconds
Started Jul 13 04:48:22 PM PDT 24
Finished Jul 13 04:48:26 PM PDT 24
Peak memory 197160 kb
Host smart-255e2d4b-a1e3-4ec6-bd6b-94ac914db951
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321379352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3321379352
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.3223096230
Short name T225
Test name
Test status
Simulation time 4070903766 ps
CPU time 104.55 seconds
Started Jul 13 04:48:22 PM PDT 24
Finished Jul 13 04:50:09 PM PDT 24
Peak memory 198796 kb
Host smart-184c292a-54b9-4e6f-b0cf-74cf589584bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223096230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.3223096230
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.2499558437
Short name T457
Test name
Test status
Simulation time 23397845273 ps
CPU time 460.04 seconds
Started Jul 13 04:48:33 PM PDT 24
Finished Jul 13 04:56:16 PM PDT 24
Peak memory 199212 kb
Host smart-302787d2-dddb-44a2-93dd-1423fa5213f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2499558437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.2499558437
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3173534057
Short name T698
Test name
Test status
Simulation time 43319550 ps
CPU time 0.59 seconds
Started Jul 13 04:48:45 PM PDT 24
Finished Jul 13 04:48:49 PM PDT 24
Peak memory 195564 kb
Host smart-bcb05823-34c7-4c0f-a2fd-a4364d48e896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173534057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3173534057
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.3714464805
Short name T312
Test name
Test status
Simulation time 17434890 ps
CPU time 0.69 seconds
Started Jul 13 04:48:46 PM PDT 24
Finished Jul 13 04:48:50 PM PDT 24
Peak memory 194752 kb
Host smart-03cd33c0-8d0e-4a94-a5b8-a45913331a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714464805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.3714464805
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.108017954
Short name T27
Test name
Test status
Simulation time 431333954 ps
CPU time 14.64 seconds
Started Jul 13 04:48:45 PM PDT 24
Finished Jul 13 04:49:02 PM PDT 24
Peak memory 197612 kb
Host smart-dd75d428-9a36-4d09-a1fd-08a79b52415d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108017954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stres
s.108017954
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1348775874
Short name T332
Test name
Test status
Simulation time 86387956 ps
CPU time 0.87 seconds
Started Jul 13 04:48:49 PM PDT 24
Finished Jul 13 04:48:52 PM PDT 24
Peak memory 196616 kb
Host smart-ac24c848-1635-4ce1-9911-344d1de5e6bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348775874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1348775874
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.687057736
Short name T329
Test name
Test status
Simulation time 142017751 ps
CPU time 1.11 seconds
Started Jul 13 04:48:47 PM PDT 24
Finished Jul 13 04:48:52 PM PDT 24
Peak memory 196676 kb
Host smart-29d87dfd-5bfa-400f-b4a6-27c31d26096e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687057736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.687057736
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3007365983
Short name T678
Test name
Test status
Simulation time 299080292 ps
CPU time 2.89 seconds
Started Jul 13 04:48:44 PM PDT 24
Finished Jul 13 04:48:49 PM PDT 24
Peak memory 197648 kb
Host smart-7ade976b-e048-4eb0-91d4-e1d8427272f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007365983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3007365983
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3199793341
Short name T229
Test name
Test status
Simulation time 107414249 ps
CPU time 1.24 seconds
Started Jul 13 04:48:49 PM PDT 24
Finished Jul 13 04:48:53 PM PDT 24
Peak memory 197172 kb
Host smart-cb0b5f4b-bfac-4498-81b9-d67b307d645f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199793341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3199793341
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3626201166
Short name T11
Test name
Test status
Simulation time 33284646 ps
CPU time 1.19 seconds
Started Jul 13 04:48:47 PM PDT 24
Finished Jul 13 04:48:51 PM PDT 24
Peak memory 197668 kb
Host smart-b9b7866e-71f2-4d29-babb-4b3231808ce2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626201166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3626201166
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3698207199
Short name T270
Test name
Test status
Simulation time 465177460 ps
CPU time 4.87 seconds
Started Jul 13 04:48:44 PM PDT 24
Finished Jul 13 04:48:51 PM PDT 24
Peak memory 198564 kb
Host smart-303e5f30-a440-44fe-90cc-fa26e190807c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698207199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3698207199
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.843025845
Short name T217
Test name
Test status
Simulation time 45141459 ps
CPU time 0.87 seconds
Started Jul 13 04:48:45 PM PDT 24
Finished Jul 13 04:48:49 PM PDT 24
Peak memory 195880 kb
Host smart-265a787b-4a7a-4341-8a41-01e1a039bb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843025845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.843025845
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.2211433711
Short name T183
Test name
Test status
Simulation time 32767220 ps
CPU time 0.97 seconds
Started Jul 13 04:48:46 PM PDT 24
Finished Jul 13 04:48:51 PM PDT 24
Peak memory 196288 kb
Host smart-c12169a7-2d8c-4b77-aa54-9bfa0449cbf3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211433711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2211433711
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1714293889
Short name T228
Test name
Test status
Simulation time 13708896760 ps
CPU time 178.09 seconds
Started Jul 13 04:48:46 PM PDT 24
Finished Jul 13 04:51:48 PM PDT 24
Peak memory 198540 kb
Host smart-a9963410-f716-4019-9824-f0eb3642fac4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714293889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1714293889
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1577494338
Short name T714
Test name
Test status
Simulation time 1390529741975 ps
CPU time 1808.58 seconds
Started Jul 13 04:48:46 PM PDT 24
Finished Jul 13 05:18:58 PM PDT 24
Peak memory 198884 kb
Host smart-1207b1f6-68b0-4678-b4d6-0df2d18bcd40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1577494338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.1577494338
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.4279460662
Short name T278
Test name
Test status
Simulation time 10336934 ps
CPU time 0.57 seconds
Started Jul 13 04:48:45 PM PDT 24
Finished Jul 13 04:48:49 PM PDT 24
Peak memory 193416 kb
Host smart-e8e18154-d66a-425d-b06a-088ebebe89f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279460662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.4279460662
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3291088454
Short name T461
Test name
Test status
Simulation time 75430588 ps
CPU time 0.82 seconds
Started Jul 13 04:48:49 PM PDT 24
Finished Jul 13 04:48:52 PM PDT 24
Peak memory 195888 kb
Host smart-b8f9fcf9-117e-4087-a7f4-6e7c7539d930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291088454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3291088454
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1004754457
Short name T680
Test name
Test status
Simulation time 481411975 ps
CPU time 16 seconds
Started Jul 13 04:48:48 PM PDT 24
Finished Jul 13 04:49:07 PM PDT 24
Peak memory 197436 kb
Host smart-46459ed6-a4a5-4a3c-bd59-408eeaa50509
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004754457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1004754457
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2328860124
Short name T624
Test name
Test status
Simulation time 202059764 ps
CPU time 1.04 seconds
Started Jul 13 04:48:51 PM PDT 24
Finished Jul 13 04:48:53 PM PDT 24
Peak memory 197132 kb
Host smart-0ccd3d97-60fe-4990-affc-068abf4ed219
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328860124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2328860124
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.2768563030
Short name T609
Test name
Test status
Simulation time 181047191 ps
CPU time 1.36 seconds
Started Jul 13 04:48:47 PM PDT 24
Finished Jul 13 04:48:52 PM PDT 24
Peak memory 197644 kb
Host smart-410ee4fe-7175-4498-919b-b1771c1d20d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768563030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2768563030
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2542127798
Short name T606
Test name
Test status
Simulation time 185394790 ps
CPU time 3.64 seconds
Started Jul 13 04:48:48 PM PDT 24
Finished Jul 13 04:48:55 PM PDT 24
Peak memory 198632 kb
Host smart-1dac9f71-435c-4a26-9271-28bb3de88c93
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542127798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2542127798
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1726284762
Short name T516
Test name
Test status
Simulation time 113399206 ps
CPU time 2.18 seconds
Started Jul 13 04:48:46 PM PDT 24
Finished Jul 13 04:48:52 PM PDT 24
Peak memory 196492 kb
Host smart-5594e2cc-1563-4a48-a441-d72f0ccd480b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726284762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1726284762
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.3776150693
Short name T260
Test name
Test status
Simulation time 295680780 ps
CPU time 1.05 seconds
Started Jul 13 04:48:47 PM PDT 24
Finished Jul 13 04:48:52 PM PDT 24
Peak memory 197092 kb
Host smart-01b2b2fc-f654-4eb0-a044-384887e5509e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776150693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.3776150693
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2060763196
Short name T512
Test name
Test status
Simulation time 241209330 ps
CPU time 1.22 seconds
Started Jul 13 04:48:47 PM PDT 24
Finished Jul 13 04:48:52 PM PDT 24
Peak memory 197480 kb
Host smart-d2155390-a6d9-41bb-b44c-2704adfec9d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060763196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2060763196
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.714266999
Short name T657
Test name
Test status
Simulation time 808615492 ps
CPU time 3.71 seconds
Started Jul 13 04:48:46 PM PDT 24
Finished Jul 13 04:48:54 PM PDT 24
Peak memory 198404 kb
Host smart-219b6341-612a-41bc-96b5-d8e576eda6ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714266999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.714266999
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.2329830533
Short name T481
Test name
Test status
Simulation time 229668951 ps
CPU time 1.31 seconds
Started Jul 13 04:48:44 PM PDT 24
Finished Jul 13 04:48:48 PM PDT 24
Peak memory 198612 kb
Host smart-550ef22b-5c4e-48be-bbfd-76ede4cfe0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329830533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.2329830533
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2500927027
Short name T384
Test name
Test status
Simulation time 201531113 ps
CPU time 1.11 seconds
Started Jul 13 04:48:44 PM PDT 24
Finished Jul 13 04:48:47 PM PDT 24
Peak memory 196948 kb
Host smart-a40021e3-5b07-4ae3-b0ea-b95ac3baa6f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500927027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2500927027
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.385855479
Short name T373
Test name
Test status
Simulation time 21786059418 ps
CPU time 79.72 seconds
Started Jul 13 04:48:44 PM PDT 24
Finished Jul 13 04:50:07 PM PDT 24
Peak memory 198748 kb
Host smart-fc5e0a0c-8421-41b7-b0a8-95842cba4d4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385855479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.385855479
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.98838917
Short name T66
Test name
Test status
Simulation time 93456175503 ps
CPU time 1764.16 seconds
Started Jul 13 04:48:50 PM PDT 24
Finished Jul 13 05:18:16 PM PDT 24
Peak memory 198836 kb
Host smart-5c248b93-a413-43cb-ba62-a080f8ccaedc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=98838917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.98838917
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1353826121
Short name T380
Test name
Test status
Simulation time 24642549 ps
CPU time 0.59 seconds
Started Jul 13 04:48:57 PM PDT 24
Finished Jul 13 04:49:00 PM PDT 24
Peak memory 194564 kb
Host smart-9032a8fb-8981-4bb5-a326-4eab5d56c74d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353826121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1353826121
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.1835224891
Short name T719
Test name
Test status
Simulation time 46243487 ps
CPU time 0.86 seconds
Started Jul 13 04:48:55 PM PDT 24
Finished Jul 13 04:48:59 PM PDT 24
Peak memory 197008 kb
Host smart-30e80648-14de-4086-892e-22fda56238ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835224891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.1835224891
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.619428691
Short name T126
Test name
Test status
Simulation time 3295960461 ps
CPU time 21.02 seconds
Started Jul 13 04:48:55 PM PDT 24
Finished Jul 13 04:49:18 PM PDT 24
Peak memory 197488 kb
Host smart-e0f367b4-fa6c-4cf8-ba5c-31c949516234
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619428691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.619428691
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1622731253
Short name T304
Test name
Test status
Simulation time 87187651 ps
CPU time 1.07 seconds
Started Jul 13 04:48:53 PM PDT 24
Finished Jul 13 04:48:56 PM PDT 24
Peak memory 197336 kb
Host smart-1bf006c9-5597-4d93-be92-77c13559c5e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622731253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1622731253
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.665183014
Short name T427
Test name
Test status
Simulation time 68205773 ps
CPU time 0.84 seconds
Started Jul 13 04:48:52 PM PDT 24
Finished Jul 13 04:48:54 PM PDT 24
Peak memory 196732 kb
Host smart-2593d559-0c8e-4b19-952a-603d5ce0def2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665183014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.665183014
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1171989424
Short name T349
Test name
Test status
Simulation time 290672656 ps
CPU time 3.07 seconds
Started Jul 13 04:48:54 PM PDT 24
Finished Jul 13 04:49:00 PM PDT 24
Peak memory 198652 kb
Host smart-c9e871fc-ba62-496b-9c7e-d29272d8c3d3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171989424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1171989424
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.352542004
Short name T525
Test name
Test status
Simulation time 469124213 ps
CPU time 3.45 seconds
Started Jul 13 04:48:53 PM PDT 24
Finished Jul 13 04:48:58 PM PDT 24
Peak memory 198708 kb
Host smart-4ada303e-354a-488f-ba16-d8159e51162c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352542004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
352542004
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1501609202
Short name T388
Test name
Test status
Simulation time 88636793 ps
CPU time 0.99 seconds
Started Jul 13 04:48:47 PM PDT 24
Finished Jul 13 04:48:51 PM PDT 24
Peak memory 196512 kb
Host smart-b0b7378e-d2d3-4fee-92b0-5d92affecb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501609202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1501609202
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3240183254
Short name T630
Test name
Test status
Simulation time 66722851 ps
CPU time 1.24 seconds
Started Jul 13 04:48:48 PM PDT 24
Finished Jul 13 04:48:52 PM PDT 24
Peak memory 197676 kb
Host smart-6011bd1a-5e84-4e62-b9e2-4c7acaebbab0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240183254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3240183254
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.76839064
Short name T10
Test name
Test status
Simulation time 695076519 ps
CPU time 1.9 seconds
Started Jul 13 04:48:53 PM PDT 24
Finished Jul 13 04:48:57 PM PDT 24
Peak memory 198608 kb
Host smart-36f53ddb-9b7f-4e5b-ba6c-97cc0e9f4617
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76839064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand
om_long_reg_writes_reg_reads.76839064
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1909572978
Short name T403
Test name
Test status
Simulation time 195380981 ps
CPU time 0.88 seconds
Started Jul 13 04:48:47 PM PDT 24
Finished Jul 13 04:48:51 PM PDT 24
Peak memory 195892 kb
Host smart-77bc8b26-3b31-4a80-9212-2d89b882b48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909572978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1909572978
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1263559734
Short name T279
Test name
Test status
Simulation time 236234780 ps
CPU time 1.19 seconds
Started Jul 13 04:48:47 PM PDT 24
Finished Jul 13 04:48:51 PM PDT 24
Peak memory 196832 kb
Host smart-e46a9441-4751-4cec-8e8d-0679742c0446
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263559734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1263559734
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.1185095030
Short name T170
Test name
Test status
Simulation time 49742121630 ps
CPU time 160.57 seconds
Started Jul 13 04:48:55 PM PDT 24
Finished Jul 13 04:51:38 PM PDT 24
Peak memory 198792 kb
Host smart-237e7eb3-4721-4298-9673-6b0d79d4ac60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185095030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.1185095030
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.2680696939
Short name T494
Test name
Test status
Simulation time 49974582 ps
CPU time 0.58 seconds
Started Jul 13 04:48:55 PM PDT 24
Finished Jul 13 04:48:58 PM PDT 24
Peak memory 195576 kb
Host smart-50c54edf-a82c-4409-9450-52768058c896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680696939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.2680696939
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.4047287114
Short name T209
Test name
Test status
Simulation time 23216545 ps
CPU time 0.75 seconds
Started Jul 13 04:48:53 PM PDT 24
Finished Jul 13 04:48:55 PM PDT 24
Peak memory 195752 kb
Host smart-6574a262-1add-49d8-9bc1-f40e1b209394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047287114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.4047287114
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.432083513
Short name T434
Test name
Test status
Simulation time 1704430463 ps
CPU time 21.86 seconds
Started Jul 13 04:48:55 PM PDT 24
Finished Jul 13 04:49:19 PM PDT 24
Peak memory 197320 kb
Host smart-bc53dd4e-a47f-4cbf-9e87-1a1fa892486a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432083513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.432083513
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.3932202760
Short name T446
Test name
Test status
Simulation time 228830703 ps
CPU time 0.98 seconds
Started Jul 13 04:48:52 PM PDT 24
Finished Jul 13 04:48:55 PM PDT 24
Peak memory 197284 kb
Host smart-4114f81a-969e-46d6-925c-7a56a1048382
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932202760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3932202760
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3838780292
Short name T123
Test name
Test status
Simulation time 44667330 ps
CPU time 1.26 seconds
Started Jul 13 04:48:54 PM PDT 24
Finished Jul 13 04:48:58 PM PDT 24
Peak memory 196784 kb
Host smart-6a3b70a6-f2c7-46e9-bdd7-669cbf16e415
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838780292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3838780292
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1790056622
Short name T603
Test name
Test status
Simulation time 148220581 ps
CPU time 2.82 seconds
Started Jul 13 04:48:58 PM PDT 24
Finished Jul 13 04:49:02 PM PDT 24
Peak memory 196888 kb
Host smart-1a3ee71f-f274-420e-8117-8d770cf8bab9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790056622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1790056622
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.4163820512
Short name T597
Test name
Test status
Simulation time 254979464 ps
CPU time 3.46 seconds
Started Jul 13 04:48:54 PM PDT 24
Finished Jul 13 04:49:00 PM PDT 24
Peak memory 198688 kb
Host smart-940f85f9-0ff5-4d05-84ac-b258af46c200
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163820512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.4163820512
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.4025854763
Short name T460
Test name
Test status
Simulation time 52635723 ps
CPU time 1.05 seconds
Started Jul 13 04:48:52 PM PDT 24
Finished Jul 13 04:48:54 PM PDT 24
Peak memory 196712 kb
Host smart-66dc5a1b-5a2b-4b1a-9c44-a3cd6d48b713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025854763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.4025854763
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2671445057
Short name T298
Test name
Test status
Simulation time 23057503 ps
CPU time 0.73 seconds
Started Jul 13 04:48:56 PM PDT 24
Finished Jul 13 04:48:59 PM PDT 24
Peak memory 194812 kb
Host smart-d4555e76-1a64-4943-b7bb-285a79dc1d85
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671445057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2671445057
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.515591303
Short name T295
Test name
Test status
Simulation time 854045608 ps
CPU time 3.67 seconds
Started Jul 13 04:48:55 PM PDT 24
Finished Jul 13 04:49:01 PM PDT 24
Peak memory 198580 kb
Host smart-e8271c94-95ee-4f58-b6bb-f1d2a69b3168
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515591303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ran
dom_long_reg_writes_reg_reads.515591303
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2049208080
Short name T185
Test name
Test status
Simulation time 42936925 ps
CPU time 1 seconds
Started Jul 13 04:48:52 PM PDT 24
Finished Jul 13 04:48:55 PM PDT 24
Peak memory 196844 kb
Host smart-7c4539fe-6f09-441a-a63d-931c008ae9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049208080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2049208080
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.4115261080
Short name T343
Test name
Test status
Simulation time 69858831 ps
CPU time 1.2 seconds
Started Jul 13 04:48:52 PM PDT 24
Finished Jul 13 04:48:54 PM PDT 24
Peak memory 196076 kb
Host smart-a119baaa-ac8f-4e49-9006-2950348f7b37
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115261080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.4115261080
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.610648851
Short name T219
Test name
Test status
Simulation time 5205363068 ps
CPU time 138.26 seconds
Started Jul 13 04:48:57 PM PDT 24
Finished Jul 13 04:51:17 PM PDT 24
Peak memory 198788 kb
Host smart-ab000128-0d92-4908-956d-4fe466663a60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610648851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.610648851
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.1085874101
Short name T451
Test name
Test status
Simulation time 93574453841 ps
CPU time 1198.48 seconds
Started Jul 13 04:48:53 PM PDT 24
Finished Jul 13 05:08:54 PM PDT 24
Peak memory 198900 kb
Host smart-a58dd684-06e6-4332-bd11-9486eb6d14e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1085874101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.1085874101
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2112309155
Short name T510
Test name
Test status
Simulation time 24148511 ps
CPU time 0.59 seconds
Started Jul 13 04:48:53 PM PDT 24
Finished Jul 13 04:48:56 PM PDT 24
Peak memory 194652 kb
Host smart-67e25393-f1c0-4a95-a890-8c9f9c8e9339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112309155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2112309155
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.3714196042
Short name T152
Test name
Test status
Simulation time 32507316 ps
CPU time 0.79 seconds
Started Jul 13 04:48:54 PM PDT 24
Finished Jul 13 04:48:57 PM PDT 24
Peak memory 196764 kb
Host smart-85e148ae-77a5-4fe0-bc43-6e518f440ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714196042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.3714196042
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1865869806
Short name T129
Test name
Test status
Simulation time 4340637888 ps
CPU time 14.51 seconds
Started Jul 13 04:48:51 PM PDT 24
Finished Jul 13 04:49:07 PM PDT 24
Peak memory 196568 kb
Host smart-38ab9b48-531a-4d1f-b79d-3508d8549178
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865869806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1865869806
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.2863340239
Short name T582
Test name
Test status
Simulation time 20089553 ps
CPU time 0.66 seconds
Started Jul 13 04:48:53 PM PDT 24
Finished Jul 13 04:48:55 PM PDT 24
Peak memory 195940 kb
Host smart-a9e725f6-b8e3-4ed1-badc-59e1c9c52fe1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863340239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.2863340239
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2662321535
Short name T560
Test name
Test status
Simulation time 55909368 ps
CPU time 1.43 seconds
Started Jul 13 04:48:53 PM PDT 24
Finished Jul 13 04:48:57 PM PDT 24
Peak memory 197552 kb
Host smart-2a10e27d-405f-4aec-b481-c87fbba313ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662321535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2662321535
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.469684001
Short name T253
Test name
Test status
Simulation time 50890040 ps
CPU time 2.12 seconds
Started Jul 13 04:48:52 PM PDT 24
Finished Jul 13 04:48:56 PM PDT 24
Peak memory 198720 kb
Host smart-1de3d888-6976-43d6-bb93-3187cc39652f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469684001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.469684001
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1549457410
Short name T628
Test name
Test status
Simulation time 89922545 ps
CPU time 2.08 seconds
Started Jul 13 04:48:57 PM PDT 24
Finished Jul 13 04:49:01 PM PDT 24
Peak memory 196792 kb
Host smart-ee9b5cdc-5aa7-457b-a627-5c77a1db5050
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549457410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1549457410
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.1556267861
Short name T134
Test name
Test status
Simulation time 68532488 ps
CPU time 0.72 seconds
Started Jul 13 04:48:54 PM PDT 24
Finished Jul 13 04:48:57 PM PDT 24
Peak memory 194968 kb
Host smart-558521a5-c61a-43a2-90ad-59e3cfd66430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556267861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.1556267861
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.3061462479
Short name T277
Test name
Test status
Simulation time 38331678 ps
CPU time 0.89 seconds
Started Jul 13 04:48:57 PM PDT 24
Finished Jul 13 04:49:00 PM PDT 24
Peak memory 197208 kb
Host smart-77cac816-b6d5-40b3-9ba1-d250a1f2249f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061462479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.3061462479
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3949332014
Short name T605
Test name
Test status
Simulation time 1118777131 ps
CPU time 5.52 seconds
Started Jul 13 04:48:53 PM PDT 24
Finished Jul 13 04:49:00 PM PDT 24
Peak memory 198616 kb
Host smart-8f5fc154-99ad-4e3a-b902-00754bdb1506
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949332014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3949332014
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.3784291116
Short name T580
Test name
Test status
Simulation time 158295518 ps
CPU time 0.99 seconds
Started Jul 13 04:48:51 PM PDT 24
Finished Jul 13 04:48:54 PM PDT 24
Peak memory 196392 kb
Host smart-b968f216-9e59-4971-a675-2ff0d720cf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784291116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3784291116
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.166243170
Short name T146
Test name
Test status
Simulation time 115867164 ps
CPU time 1.15 seconds
Started Jul 13 04:48:53 PM PDT 24
Finished Jul 13 04:48:56 PM PDT 24
Peak memory 196188 kb
Host smart-c37f7f88-1a6c-4b41-94c3-f5b4e092c57e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166243170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.166243170
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.1203006040
Short name T227
Test name
Test status
Simulation time 25932530282 ps
CPU time 81.01 seconds
Started Jul 13 04:48:54 PM PDT 24
Finished Jul 13 04:50:17 PM PDT 24
Peak memory 198820 kb
Host smart-80fd10ac-d9d7-4bdd-bc6c-d26d050b7561
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203006040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.1203006040
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.3837438298
Short name T477
Test name
Test status
Simulation time 453198414466 ps
CPU time 770.33 seconds
Started Jul 13 04:48:56 PM PDT 24
Finished Jul 13 05:01:49 PM PDT 24
Peak memory 198796 kb
Host smart-96162495-1d2d-4be5-aae2-f01be0338a3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3837438298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.3837438298
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.659696011
Short name T273
Test name
Test status
Simulation time 11842727 ps
CPU time 0.6 seconds
Started Jul 13 04:49:01 PM PDT 24
Finished Jul 13 04:49:04 PM PDT 24
Peak memory 194748 kb
Host smart-325fc74e-5b91-4eb3-baf2-427fd3c48354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659696011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.659696011
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2845915590
Short name T307
Test name
Test status
Simulation time 28075914 ps
CPU time 0.9 seconds
Started Jul 13 04:48:53 PM PDT 24
Finished Jul 13 04:48:55 PM PDT 24
Peak memory 197004 kb
Host smart-04027264-cd92-42ab-ba6f-b67be009dd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845915590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2845915590
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.1070188556
Short name T293
Test name
Test status
Simulation time 2454053875 ps
CPU time 28.91 seconds
Started Jul 13 04:48:56 PM PDT 24
Finished Jul 13 04:49:27 PM PDT 24
Peak memory 197164 kb
Host smart-149c18b0-a44a-46ef-ae86-ef77a8bb885f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070188556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.1070188556
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3097949731
Short name T5
Test name
Test status
Simulation time 130186420 ps
CPU time 0.92 seconds
Started Jul 13 04:48:55 PM PDT 24
Finished Jul 13 04:48:58 PM PDT 24
Peak memory 197560 kb
Host smart-f1518573-33e2-4524-b939-edc130f368d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097949731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3097949731
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.1441092756
Short name T598
Test name
Test status
Simulation time 63325427 ps
CPU time 1.18 seconds
Started Jul 13 04:48:54 PM PDT 24
Finished Jul 13 04:48:57 PM PDT 24
Peak memory 196512 kb
Host smart-d7a44b8d-af2b-4427-87c0-e7f2e80b98d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441092756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.1441092756
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3946989463
Short name T180
Test name
Test status
Simulation time 418528032 ps
CPU time 2.83 seconds
Started Jul 13 04:48:54 PM PDT 24
Finished Jul 13 04:48:59 PM PDT 24
Peak memory 198712 kb
Host smart-ba615dea-b06e-473e-ab10-3426a72c7828
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946989463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3946989463
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.726533435
Short name T381
Test name
Test status
Simulation time 113490758 ps
CPU time 2.44 seconds
Started Jul 13 04:48:55 PM PDT 24
Finished Jul 13 04:49:00 PM PDT 24
Peak memory 198760 kb
Host smart-dced4b18-2544-4f35-bef6-9604fef88a28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726533435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.
726533435
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.4044231587
Short name T448
Test name
Test status
Simulation time 58447087 ps
CPU time 1.03 seconds
Started Jul 13 04:48:58 PM PDT 24
Finished Jul 13 04:49:00 PM PDT 24
Peak memory 196596 kb
Host smart-298f76ff-fdca-4d9f-af24-bd238f1d1cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044231587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.4044231587
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.1094685574
Short name T503
Test name
Test status
Simulation time 64284342 ps
CPU time 0.89 seconds
Started Jul 13 04:48:54 PM PDT 24
Finished Jul 13 04:48:58 PM PDT 24
Peak memory 196512 kb
Host smart-f6f3ed4f-489d-41a4-bd66-5cb2e8b3ea22
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094685574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.1094685574
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.684354926
Short name T418
Test name
Test status
Simulation time 54505114 ps
CPU time 1.18 seconds
Started Jul 13 04:48:55 PM PDT 24
Finished Jul 13 04:48:58 PM PDT 24
Peak memory 198620 kb
Host smart-36a9fe8b-fa4e-48e0-bb0a-8b2cab85e212
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684354926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.684354926
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.2629578093
Short name T394
Test name
Test status
Simulation time 51621650 ps
CPU time 1.43 seconds
Started Jul 13 04:48:56 PM PDT 24
Finished Jul 13 04:48:59 PM PDT 24
Peak memory 196136 kb
Host smart-20c9c931-5279-455a-9cf1-ca0889794d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629578093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.2629578093
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.769689213
Short name T308
Test name
Test status
Simulation time 59006760 ps
CPU time 1.23 seconds
Started Jul 13 04:48:54 PM PDT 24
Finished Jul 13 04:48:57 PM PDT 24
Peak memory 196508 kb
Host smart-dee25f85-143f-4060-94b3-7b37fc18a259
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769689213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.769689213
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3825023934
Short name T73
Test name
Test status
Simulation time 1290848548 ps
CPU time 32 seconds
Started Jul 13 04:49:02 PM PDT 24
Finished Jul 13 04:49:36 PM PDT 24
Peak memory 198564 kb
Host smart-3c54cb4a-db88-4135-aade-70bccc1bd1f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825023934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3825023934
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.378679286
Short name T331
Test name
Test status
Simulation time 119118325 ps
CPU time 0.61 seconds
Started Jul 13 04:49:02 PM PDT 24
Finished Jul 13 04:49:05 PM PDT 24
Peak memory 194876 kb
Host smart-84d5688f-9c95-47cd-9318-2e20dcb635a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378679286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.378679286
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.4216669779
Short name T641
Test name
Test status
Simulation time 151852234 ps
CPU time 0.82 seconds
Started Jul 13 04:48:59 PM PDT 24
Finished Jul 13 04:49:02 PM PDT 24
Peak memory 196056 kb
Host smart-727da90a-324a-4c8e-82ba-d2a303183aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216669779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.4216669779
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.809425485
Short name T488
Test name
Test status
Simulation time 1974084243 ps
CPU time 25.11 seconds
Started Jul 13 04:49:01 PM PDT 24
Finished Jul 13 04:49:28 PM PDT 24
Peak memory 198604 kb
Host smart-ad418246-8152-418f-b537-2fdf3effdeaf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809425485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stres
s.809425485
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.4126228917
Short name T513
Test name
Test status
Simulation time 26732049 ps
CPU time 0.69 seconds
Started Jul 13 04:48:59 PM PDT 24
Finished Jul 13 04:49:02 PM PDT 24
Peak memory 195196 kb
Host smart-aeec722f-d28e-4b5c-b57e-d2ce4e885854
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126228917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.4126228917
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1700008169
Short name T689
Test name
Test status
Simulation time 90618017 ps
CPU time 1.13 seconds
Started Jul 13 04:49:01 PM PDT 24
Finished Jul 13 04:49:04 PM PDT 24
Peak memory 196468 kb
Host smart-aa1fc4ee-09f4-4214-a5af-175337023d26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700008169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1700008169
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1613165133
Short name T548
Test name
Test status
Simulation time 186030763 ps
CPU time 2.16 seconds
Started Jul 13 04:49:01 PM PDT 24
Finished Jul 13 04:49:05 PM PDT 24
Peak memory 198700 kb
Host smart-ec9b3b1c-2c1a-467f-aadc-994d5b2e18b4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613165133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1613165133
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.3974531195
Short name T648
Test name
Test status
Simulation time 44712159 ps
CPU time 1.11 seconds
Started Jul 13 04:49:01 PM PDT 24
Finished Jul 13 04:49:04 PM PDT 24
Peak memory 196916 kb
Host smart-f5a9eb66-bb58-44d4-ada0-13a9bfa2e909
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974531195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.3974531195
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.280230420
Short name T441
Test name
Test status
Simulation time 168129956 ps
CPU time 1.01 seconds
Started Jul 13 04:49:00 PM PDT 24
Finished Jul 13 04:49:03 PM PDT 24
Peak memory 196616 kb
Host smart-8a089a7f-be33-44c7-9d84-d5f3c69b5ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280230420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.280230420
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.457483882
Short name T135
Test name
Test status
Simulation time 272675049 ps
CPU time 0.97 seconds
Started Jul 13 04:49:05 PM PDT 24
Finished Jul 13 04:49:07 PM PDT 24
Peak memory 196552 kb
Host smart-0a92bb72-68d2-4655-9c57-752d28421953
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457483882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.457483882
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.590562636
Short name T67
Test name
Test status
Simulation time 1441046518 ps
CPU time 4.03 seconds
Started Jul 13 04:49:07 PM PDT 24
Finished Jul 13 04:49:11 PM PDT 24
Peak memory 198456 kb
Host smart-7d1ac5d1-b4a3-4e05-91ef-cfc387484ca8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590562636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ran
dom_long_reg_writes_reg_reads.590562636
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2225102660
Short name T596
Test name
Test status
Simulation time 265853850 ps
CPU time 1.11 seconds
Started Jul 13 04:48:59 PM PDT 24
Finished Jul 13 04:49:02 PM PDT 24
Peak memory 196216 kb
Host smart-e15bcbd0-d122-48a9-a36d-e112342681ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225102660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2225102660
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1186876591
Short name T109
Test name
Test status
Simulation time 53189567 ps
CPU time 1.04 seconds
Started Jul 13 04:49:01 PM PDT 24
Finished Jul 13 04:49:05 PM PDT 24
Peak memory 196252 kb
Host smart-7e74ee05-caeb-4561-8d98-bdabc5de809a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186876591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1186876591
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.711413362
Short name T553
Test name
Test status
Simulation time 14375914325 ps
CPU time 207.51 seconds
Started Jul 13 04:49:00 PM PDT 24
Finished Jul 13 04:52:30 PM PDT 24
Peak memory 198808 kb
Host smart-b3a4bf22-54bf-41dd-98a2-166eb3fe035c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711413362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.711413362
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.2280434462
Short name T60
Test name
Test status
Simulation time 45894627863 ps
CPU time 735.65 seconds
Started Jul 13 04:49:01 PM PDT 24
Finished Jul 13 05:01:19 PM PDT 24
Peak memory 198932 kb
Host smart-da244728-ab58-4690-ba98-0ac230c8ee85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2280434462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.2280434462
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.2171347109
Short name T474
Test name
Test status
Simulation time 45295809 ps
CPU time 0.61 seconds
Started Jul 13 04:49:01 PM PDT 24
Finished Jul 13 04:49:04 PM PDT 24
Peak memory 195532 kb
Host smart-5036a096-3eb5-40af-83d4-9a26ffaa5eab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171347109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2171347109
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.592947458
Short name T72
Test name
Test status
Simulation time 563800382 ps
CPU time 0.86 seconds
Started Jul 13 04:49:01 PM PDT 24
Finished Jul 13 04:49:04 PM PDT 24
Peak memory 195980 kb
Host smart-5a0b9a6e-e209-43ca-8c16-006997a22eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592947458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.592947458
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.3937403778
Short name T405
Test name
Test status
Simulation time 1235527254 ps
CPU time 15.6 seconds
Started Jul 13 04:49:02 PM PDT 24
Finished Jul 13 04:49:19 PM PDT 24
Peak memory 197312 kb
Host smart-4cfb6d75-3629-4461-855c-010d46b6cf7a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937403778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.3937403778
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.3208087317
Short name T266
Test name
Test status
Simulation time 147619426 ps
CPU time 0.72 seconds
Started Jul 13 04:49:00 PM PDT 24
Finished Jul 13 04:49:03 PM PDT 24
Peak memory 196352 kb
Host smart-575f4e18-3f0c-4e67-82a4-7ea14e9d700a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208087317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.3208087317
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1816059529
Short name T415
Test name
Test status
Simulation time 79874610 ps
CPU time 1.29 seconds
Started Jul 13 04:49:02 PM PDT 24
Finished Jul 13 04:49:05 PM PDT 24
Peak memory 197364 kb
Host smart-edd88111-7f0e-49ab-84a8-71148af5dfbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816059529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1816059529
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1894281538
Short name T283
Test name
Test status
Simulation time 82693866 ps
CPU time 3.22 seconds
Started Jul 13 04:49:00 PM PDT 24
Finished Jul 13 04:49:05 PM PDT 24
Peak memory 198344 kb
Host smart-f3d486b2-d024-4d27-a70c-fbfa1a836eb5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894281538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1894281538
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1068016219
Short name T320
Test name
Test status
Simulation time 105764693 ps
CPU time 3.28 seconds
Started Jul 13 04:49:00 PM PDT 24
Finished Jul 13 04:49:05 PM PDT 24
Peak memory 197660 kb
Host smart-cc626d4d-35f3-4784-a12e-c2e0d33582ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068016219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1068016219
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.2037260707
Short name T695
Test name
Test status
Simulation time 95390695 ps
CPU time 0.62 seconds
Started Jul 13 04:49:07 PM PDT 24
Finished Jul 13 04:49:09 PM PDT 24
Peak memory 194704 kb
Host smart-3df04c92-da43-4d96-bab7-6b51722b5c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037260707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.2037260707
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1419431523
Short name T622
Test name
Test status
Simulation time 67993363 ps
CPU time 0.79 seconds
Started Jul 13 04:49:06 PM PDT 24
Finished Jul 13 04:49:07 PM PDT 24
Peak memory 196116 kb
Host smart-da197f3d-6926-4e68-972f-8caf5d1f8026
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419431523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.1419431523
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3143905620
Short name T235
Test name
Test status
Simulation time 1086308710 ps
CPU time 6.1 seconds
Started Jul 13 04:49:02 PM PDT 24
Finished Jul 13 04:49:10 PM PDT 24
Peak memory 198556 kb
Host smart-bd4e15e7-6578-46fe-8e5a-d7cbe2f1ce0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143905620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3143905620
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3987105729
Short name T301
Test name
Test status
Simulation time 177462368 ps
CPU time 1.26 seconds
Started Jul 13 04:49:01 PM PDT 24
Finished Jul 13 04:49:05 PM PDT 24
Peak memory 198596 kb
Host smart-d5ea962d-97ce-450f-a73a-45daaf960349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987105729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3987105729
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2140947439
Short name T265
Test name
Test status
Simulation time 56264886 ps
CPU time 0.83 seconds
Started Jul 13 04:49:01 PM PDT 24
Finished Jul 13 04:49:04 PM PDT 24
Peak memory 195776 kb
Host smart-c4b376e3-7a5d-41eb-b406-24224db34f13
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140947439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2140947439
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.4125235030
Short name T466
Test name
Test status
Simulation time 89230961059 ps
CPU time 155.47 seconds
Started Jul 13 04:49:03 PM PDT 24
Finished Jul 13 04:51:40 PM PDT 24
Peak memory 198712 kb
Host smart-cdd328cb-2400-454b-8f32-824a80fdd17c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125235030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.4125235030
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.1165362181
Short name T445
Test name
Test status
Simulation time 15835719 ps
CPU time 0.61 seconds
Started Jul 13 04:49:07 PM PDT 24
Finished Jul 13 04:49:08 PM PDT 24
Peak memory 194512 kb
Host smart-452c02fe-7030-44eb-aea3-741397d1b7b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165362181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.1165362181
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2110031616
Short name T292
Test name
Test status
Simulation time 42412829 ps
CPU time 0.81 seconds
Started Jul 13 04:49:01 PM PDT 24
Finished Jul 13 04:49:04 PM PDT 24
Peak memory 196100 kb
Host smart-358a3a92-18df-413a-9aae-87913b32a3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110031616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2110031616
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.505824875
Short name T226
Test name
Test status
Simulation time 2142782591 ps
CPU time 14.67 seconds
Started Jul 13 04:48:57 PM PDT 24
Finished Jul 13 04:49:14 PM PDT 24
Peak memory 197500 kb
Host smart-93a4a166-246d-4522-a3ed-0e278e883cde
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505824875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.505824875
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3634638676
Short name T356
Test name
Test status
Simulation time 19362581 ps
CPU time 0.65 seconds
Started Jul 13 04:48:59 PM PDT 24
Finished Jul 13 04:49:02 PM PDT 24
Peak memory 195160 kb
Host smart-c286eb92-7212-4739-8007-19f2510d8c91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634638676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3634638676
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.3725155409
Short name T205
Test name
Test status
Simulation time 273133018 ps
CPU time 1.29 seconds
Started Jul 13 04:49:01 PM PDT 24
Finished Jul 13 04:49:05 PM PDT 24
Peak memory 197756 kb
Host smart-2dc4f5b8-51cd-433c-a269-d38ae09ded34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725155409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.3725155409
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.835600799
Short name T654
Test name
Test status
Simulation time 291270255 ps
CPU time 3.2 seconds
Started Jul 13 04:48:59 PM PDT 24
Finished Jul 13 04:49:04 PM PDT 24
Peak memory 198652 kb
Host smart-12729c09-a652-44e0-8d4e-01be86922a61
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835600799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.gpio_intr_with_filter_rand_intr_event.835600799
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3505622898
Short name T353
Test name
Test status
Simulation time 214889248 ps
CPU time 1.59 seconds
Started Jul 13 04:49:01 PM PDT 24
Finished Jul 13 04:49:05 PM PDT 24
Peak memory 196440 kb
Host smart-df26fde2-defe-4948-a832-4383b8c5bdf6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505622898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3505622898
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.784992253
Short name T274
Test name
Test status
Simulation time 136359718 ps
CPU time 1.22 seconds
Started Jul 13 04:48:59 PM PDT 24
Finished Jul 13 04:49:02 PM PDT 24
Peak memory 196612 kb
Host smart-52a127a5-68cf-4f04-b70c-ac9b58da5f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784992253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.784992253
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.3441946470
Short name T673
Test name
Test status
Simulation time 196750440 ps
CPU time 1.07 seconds
Started Jul 13 04:49:00 PM PDT 24
Finished Jul 13 04:49:03 PM PDT 24
Peak memory 196464 kb
Host smart-8417c623-3ea9-4180-8e80-190e4908c6d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441946470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.3441946470
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.2727396967
Short name T646
Test name
Test status
Simulation time 381143079 ps
CPU time 1.82 seconds
Started Jul 13 04:49:02 PM PDT 24
Finished Jul 13 04:49:06 PM PDT 24
Peak memory 198552 kb
Host smart-b42dab35-6758-4341-b842-3f7a0c5f0e9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727396967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.2727396967
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.1410982420
Short name T587
Test name
Test status
Simulation time 65448786 ps
CPU time 1.03 seconds
Started Jul 13 04:49:03 PM PDT 24
Finished Jul 13 04:49:05 PM PDT 24
Peak memory 196752 kb
Host smart-7b7edfe5-2b64-4707-b82f-7d46924b9de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410982420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.1410982420
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3105688837
Short name T285
Test name
Test status
Simulation time 138859783 ps
CPU time 1.04 seconds
Started Jul 13 04:49:02 PM PDT 24
Finished Jul 13 04:49:05 PM PDT 24
Peak memory 196944 kb
Host smart-53cf69ca-71f0-4eac-b7c8-2209160b9a6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105688837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3105688837
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3587844820
Short name T558
Test name
Test status
Simulation time 4822024807 ps
CPU time 69.23 seconds
Started Jul 13 04:49:00 PM PDT 24
Finished Jul 13 04:50:11 PM PDT 24
Peak memory 198852 kb
Host smart-11c6cc7f-34ed-42c2-9ba7-d24ef1bf447e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587844820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3587844820
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.829814313
Short name T275
Test name
Test status
Simulation time 43352027 ps
CPU time 0.62 seconds
Started Jul 13 04:49:09 PM PDT 24
Finished Jul 13 04:49:10 PM PDT 24
Peak memory 195336 kb
Host smart-de861736-a175-48af-8cb9-b69676e789bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829814313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.829814313
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.2991084954
Short name T586
Test name
Test status
Simulation time 43358187 ps
CPU time 0.64 seconds
Started Jul 13 04:49:10 PM PDT 24
Finished Jul 13 04:49:12 PM PDT 24
Peak memory 194588 kb
Host smart-ef0a9ec1-ab60-4068-a986-b97bec87364e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991084954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.2991084954
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.3483511034
Short name T153
Test name
Test status
Simulation time 3841020681 ps
CPU time 27.29 seconds
Started Jul 13 04:49:12 PM PDT 24
Finished Jul 13 04:49:40 PM PDT 24
Peak memory 197588 kb
Host smart-eca13d6a-8c1a-44f0-86f6-7e5a3df5f426
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483511034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.3483511034
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3686121616
Short name T330
Test name
Test status
Simulation time 71235913 ps
CPU time 0.78 seconds
Started Jul 13 04:49:11 PM PDT 24
Finished Jul 13 04:49:14 PM PDT 24
Peak memory 196536 kb
Host smart-e15c5cdc-1295-44f3-a4a2-5d583a8eb0f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686121616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3686121616
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2005330980
Short name T544
Test name
Test status
Simulation time 41871025 ps
CPU time 0.94 seconds
Started Jul 13 04:49:08 PM PDT 24
Finished Jul 13 04:49:10 PM PDT 24
Peak memory 197116 kb
Host smart-49a469db-2a5b-4adc-aa4e-8ee625bf5c68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005330980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2005330980
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3122781953
Short name T688
Test name
Test status
Simulation time 91320585 ps
CPU time 3.58 seconds
Started Jul 13 04:49:09 PM PDT 24
Finished Jul 13 04:49:13 PM PDT 24
Peak memory 198688 kb
Host smart-60e42f5f-4610-44c9-bd31-c22acb700a16
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122781953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3122781953
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.2113085056
Short name T476
Test name
Test status
Simulation time 73589816 ps
CPU time 1.84 seconds
Started Jul 13 04:49:11 PM PDT 24
Finished Jul 13 04:49:14 PM PDT 24
Peak memory 197484 kb
Host smart-b589f9df-1a0b-42cf-aacf-6657fe9ca86d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113085056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.2113085056
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.404837281
Short name T660
Test name
Test status
Simulation time 65117875 ps
CPU time 1 seconds
Started Jul 13 04:49:10 PM PDT 24
Finished Jul 13 04:49:12 PM PDT 24
Peak memory 197284 kb
Host smart-c95cb83c-f511-4ef1-b285-64f47a0d06d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404837281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.404837281
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.666442589
Short name T195
Test name
Test status
Simulation time 31789999 ps
CPU time 1.2 seconds
Started Jul 13 04:49:09 PM PDT 24
Finished Jul 13 04:49:11 PM PDT 24
Peak memory 197668 kb
Host smart-3778a9f1-7ec3-471b-ae68-e7ae12decd76
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666442589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.666442589
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.4236563667
Short name T54
Test name
Test status
Simulation time 1096153201 ps
CPU time 5.15 seconds
Started Jul 13 04:49:10 PM PDT 24
Finished Jul 13 04:49:17 PM PDT 24
Peak memory 198604 kb
Host smart-ed7c4170-b5e2-4790-b119-277274f4bc38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236563667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.4236563667
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1743101852
Short name T679
Test name
Test status
Simulation time 108273266 ps
CPU time 0.98 seconds
Started Jul 13 04:49:03 PM PDT 24
Finished Jul 13 04:49:05 PM PDT 24
Peak memory 196296 kb
Host smart-6840f202-4da9-4e52-a8be-88672661c798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743101852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1743101852
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.650575910
Short name T211
Test name
Test status
Simulation time 427406332 ps
CPU time 1.3 seconds
Started Jul 13 04:49:10 PM PDT 24
Finished Jul 13 04:49:13 PM PDT 24
Peak memory 197736 kb
Host smart-cf4a61e4-c840-4b1a-8baa-b33e8fbf5f62
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650575910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.650575910
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3482104610
Short name T412
Test name
Test status
Simulation time 136767531973 ps
CPU time 176.33 seconds
Started Jul 13 04:49:11 PM PDT 24
Finished Jul 13 04:52:09 PM PDT 24
Peak memory 198760 kb
Host smart-06883482-2547-49b5-8d91-a3fabeb79d89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482104610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3482104610
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.10258575
Short name T347
Test name
Test status
Simulation time 75487587 ps
CPU time 0.59 seconds
Started Jul 13 04:48:23 PM PDT 24
Finished Jul 13 04:48:26 PM PDT 24
Peak memory 195336 kb
Host smart-4c867456-c5a1-4a9b-a132-43b183cad718
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10258575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.10258575
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.968299337
Short name T370
Test name
Test status
Simulation time 257942688 ps
CPU time 0.89 seconds
Started Jul 13 04:48:25 PM PDT 24
Finished Jul 13 04:48:29 PM PDT 24
Peak memory 196480 kb
Host smart-0c1123dd-3c66-4af0-b98c-169af8b50fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968299337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.968299337
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2344030618
Short name T289
Test name
Test status
Simulation time 691754221 ps
CPU time 17.53 seconds
Started Jul 13 04:48:27 PM PDT 24
Finished Jul 13 04:48:47 PM PDT 24
Peak memory 197416 kb
Host smart-9af7ea87-10f8-4853-bede-6a5f27bcb77e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344030618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2344030618
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.3904179415
Short name T636
Test name
Test status
Simulation time 240732135 ps
CPU time 0.82 seconds
Started Jul 13 04:48:21 PM PDT 24
Finished Jul 13 04:48:25 PM PDT 24
Peak memory 196400 kb
Host smart-fc2b0930-d28a-44ec-963f-ca2d226ebd3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904179415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.3904179415
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2195925725
Short name T539
Test name
Test status
Simulation time 426958923 ps
CPU time 1.06 seconds
Started Jul 13 04:48:22 PM PDT 24
Finished Jul 13 04:48:25 PM PDT 24
Peak memory 196740 kb
Host smart-ea5a3f4f-0160-4cbc-b7dd-034d5cdd6168
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195925725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2195925725
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.1714306612
Short name T659
Test name
Test status
Simulation time 609410823 ps
CPU time 2.37 seconds
Started Jul 13 04:48:33 PM PDT 24
Finished Jul 13 04:48:37 PM PDT 24
Peak memory 198948 kb
Host smart-d9f7b913-1a70-40d8-9d85-175b2c6e14a9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714306612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.1714306612
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3097183579
Short name T423
Test name
Test status
Simulation time 129308982 ps
CPU time 3.47 seconds
Started Jul 13 04:48:26 PM PDT 24
Finished Jul 13 04:48:31 PM PDT 24
Peak memory 197588 kb
Host smart-f7d72cd2-edca-4026-8672-bdf1babba9dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097183579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3097183579
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3900471805
Short name T479
Test name
Test status
Simulation time 45352783 ps
CPU time 0.81 seconds
Started Jul 13 04:48:33 PM PDT 24
Finished Jul 13 04:48:36 PM PDT 24
Peak memory 197556 kb
Host smart-d9202d17-cd31-4e5e-8ae4-7c23e981b29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900471805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3900471805
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3911076251
Short name T220
Test name
Test status
Simulation time 256742409 ps
CPU time 1.2 seconds
Started Jul 13 04:48:33 PM PDT 24
Finished Jul 13 04:48:36 PM PDT 24
Peak memory 197016 kb
Host smart-1d62c0bf-052f-4071-b4b1-06cfe057aa02
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911076251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.3911076251
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.4002631222
Short name T8
Test name
Test status
Simulation time 3472953546 ps
CPU time 6.09 seconds
Started Jul 13 04:48:25 PM PDT 24
Finished Jul 13 04:48:34 PM PDT 24
Peak memory 198640 kb
Host smart-1758d935-2eb2-4f1d-ab5e-2fcd466b5df2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002631222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.4002631222
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.4262240662
Short name T36
Test name
Test status
Simulation time 37048380 ps
CPU time 0.85 seconds
Started Jul 13 04:48:33 PM PDT 24
Finished Jul 13 04:48:36 PM PDT 24
Peak memory 214468 kb
Host smart-796fe37e-74b7-4235-a946-6c2210b4c5db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262240662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.4262240662
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1077010186
Short name T696
Test name
Test status
Simulation time 90479545 ps
CPU time 1.2 seconds
Started Jul 13 04:48:22 PM PDT 24
Finished Jul 13 04:48:25 PM PDT 24
Peak memory 196448 kb
Host smart-162b4bb9-73d3-4b67-a050-e4477150b7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077010186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1077010186
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.1777756250
Short name T118
Test name
Test status
Simulation time 118545200 ps
CPU time 0.98 seconds
Started Jul 13 04:48:24 PM PDT 24
Finished Jul 13 04:48:27 PM PDT 24
Peak memory 196364 kb
Host smart-156649da-833c-45d1-aabe-8562020ce0c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777756250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.1777756250
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.768273275
Short name T627
Test name
Test status
Simulation time 49501707811 ps
CPU time 141.4 seconds
Started Jul 13 04:48:33 PM PDT 24
Finished Jul 13 04:50:57 PM PDT 24
Peak memory 199104 kb
Host smart-b70cb801-67e6-4508-ae40-a6ae8aaf4d2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768273275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gp
io_stress_all.768273275
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.574999230
Short name T309
Test name
Test status
Simulation time 59161421 ps
CPU time 0.71 seconds
Started Jul 13 04:49:10 PM PDT 24
Finished Jul 13 04:49:12 PM PDT 24
Peak memory 195872 kb
Host smart-2564b213-dcd8-452d-8cf6-d39c300214a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574999230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.574999230
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.8254334
Short name T311
Test name
Test status
Simulation time 1652541580 ps
CPU time 17.71 seconds
Started Jul 13 04:49:12 PM PDT 24
Finished Jul 13 04:49:31 PM PDT 24
Peak memory 197360 kb
Host smart-36f65143-a130-447e-9e91-962271f5ba90
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8254334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_s
tress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stress.8254334
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.3609288319
Short name T207
Test name
Test status
Simulation time 28537739 ps
CPU time 0.73 seconds
Started Jul 13 04:49:15 PM PDT 24
Finished Jul 13 04:49:16 PM PDT 24
Peak memory 195288 kb
Host smart-79c7d6af-8485-4c51-818f-3e90c3ac97f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609288319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.3609288319
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.4282031831
Short name T519
Test name
Test status
Simulation time 683888264 ps
CPU time 1.12 seconds
Started Jul 13 04:49:10 PM PDT 24
Finished Jul 13 04:49:13 PM PDT 24
Peak memory 196700 kb
Host smart-df74e753-74cf-42d9-a66d-404df24ae1c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282031831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.4282031831
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3256845229
Short name T326
Test name
Test status
Simulation time 61315623 ps
CPU time 2.5 seconds
Started Jul 13 04:49:14 PM PDT 24
Finished Jul 13 04:49:17 PM PDT 24
Peak memory 198608 kb
Host smart-7676a738-ec54-4cd7-baa9-c6368b9910ab
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256845229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3256845229
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3038311591
Short name T523
Test name
Test status
Simulation time 123139824 ps
CPU time 1.19 seconds
Started Jul 13 04:49:09 PM PDT 24
Finished Jul 13 04:49:11 PM PDT 24
Peak memory 196372 kb
Host smart-27222c02-2560-4d17-ba95-5b2ae859d6fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038311591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3038311591
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1366515857
Short name T365
Test name
Test status
Simulation time 21292653 ps
CPU time 0.85 seconds
Started Jul 13 04:49:11 PM PDT 24
Finished Jul 13 04:49:13 PM PDT 24
Peak memory 197920 kb
Host smart-237617f9-5d0f-4b13-baa8-cb15a71d2b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366515857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1366515857
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3420652605
Short name T431
Test name
Test status
Simulation time 24299581 ps
CPU time 0.75 seconds
Started Jul 13 04:49:09 PM PDT 24
Finished Jul 13 04:49:11 PM PDT 24
Peak memory 196760 kb
Host smart-2a9ce07d-be60-41d6-a062-5f3dbea36c1a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420652605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3420652605
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2461365062
Short name T645
Test name
Test status
Simulation time 99958953 ps
CPU time 2.1 seconds
Started Jul 13 04:49:13 PM PDT 24
Finished Jul 13 04:49:16 PM PDT 24
Peak memory 198536 kb
Host smart-5a820610-b25d-46b2-8064-d78e3e4be587
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461365062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2461365062
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.446102867
Short name T160
Test name
Test status
Simulation time 145789824 ps
CPU time 1.11 seconds
Started Jul 13 04:49:12 PM PDT 24
Finished Jul 13 04:49:15 PM PDT 24
Peak memory 196168 kb
Host smart-596b70c1-c9a8-4677-8c59-332eb5b5a671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446102867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.446102867
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3594100916
Short name T685
Test name
Test status
Simulation time 45945283 ps
CPU time 1.07 seconds
Started Jul 13 04:49:09 PM PDT 24
Finished Jul 13 04:49:11 PM PDT 24
Peak memory 196256 kb
Host smart-a7ef1108-9b02-4282-95b0-82ff00324ab8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594100916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3594100916
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.3551537648
Short name T406
Test name
Test status
Simulation time 15445625465 ps
CPU time 102.84 seconds
Started Jul 13 04:49:09 PM PDT 24
Finished Jul 13 04:50:53 PM PDT 24
Peak memory 198704 kb
Host smart-416847b6-da7c-460c-a808-a2c507bf0a20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551537648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.3551537648
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.2369047579
Short name T389
Test name
Test status
Simulation time 24414849 ps
CPU time 0.58 seconds
Started Jul 13 04:49:13 PM PDT 24
Finished Jul 13 04:49:15 PM PDT 24
Peak memory 194612 kb
Host smart-6e0b5e51-bb31-46f1-a230-199a264356ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369047579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2369047579
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1594222074
Short name T28
Test name
Test status
Simulation time 71965878 ps
CPU time 0.91 seconds
Started Jul 13 04:49:10 PM PDT 24
Finished Jul 13 04:49:12 PM PDT 24
Peak memory 196564 kb
Host smart-dcd3ce5d-d8e2-42d2-af47-837991fc3be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594222074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1594222074
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2490941982
Short name T306
Test name
Test status
Simulation time 751414952 ps
CPU time 25.93 seconds
Started Jul 13 04:49:09 PM PDT 24
Finished Jul 13 04:49:35 PM PDT 24
Peak memory 198672 kb
Host smart-c629e439-dddb-4e2c-b80c-a559b7c8b0c7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490941982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2490941982
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.990882298
Short name T521
Test name
Test status
Simulation time 481843678 ps
CPU time 1.05 seconds
Started Jul 13 04:49:14 PM PDT 24
Finished Jul 13 04:49:16 PM PDT 24
Peak memory 197000 kb
Host smart-8d020933-1b27-42e4-9aea-daafea4db7fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990882298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.990882298
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.4039861873
Short name T158
Test name
Test status
Simulation time 158344392 ps
CPU time 1.17 seconds
Started Jul 13 04:49:13 PM PDT 24
Finished Jul 13 04:49:15 PM PDT 24
Peak memory 197092 kb
Host smart-fefdc68a-146f-49e3-8da4-c6f962f3ac59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039861873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.4039861873
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.600138570
Short name T181
Test name
Test status
Simulation time 26759102 ps
CPU time 1.15 seconds
Started Jul 13 04:49:11 PM PDT 24
Finished Jul 13 04:49:13 PM PDT 24
Peak memory 197760 kb
Host smart-e7abed06-5bbd-4698-bd28-df6ead2b2618
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600138570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.600138570
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.4274264209
Short name T614
Test name
Test status
Simulation time 627277573 ps
CPU time 3.1 seconds
Started Jul 13 04:49:11 PM PDT 24
Finished Jul 13 04:49:15 PM PDT 24
Peak memory 196488 kb
Host smart-1d3e8175-111d-482b-b702-a1cc1971d669
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274264209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.4274264209
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.4177590755
Short name T51
Test name
Test status
Simulation time 63753147 ps
CPU time 1.01 seconds
Started Jul 13 04:49:11 PM PDT 24
Finished Jul 13 04:49:14 PM PDT 24
Peak memory 197292 kb
Host smart-0c4f8a38-e9d0-46b9-b1d6-eccb6ff42ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177590755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.4177590755
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3758321762
Short name T141
Test name
Test status
Simulation time 33093690 ps
CPU time 1.09 seconds
Started Jul 13 04:49:10 PM PDT 24
Finished Jul 13 04:49:13 PM PDT 24
Peak memory 196508 kb
Host smart-ec5c2cbb-979b-4059-9c10-f5af583ec348
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758321762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3758321762
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3699891044
Short name T55
Test name
Test status
Simulation time 672819118 ps
CPU time 5.1 seconds
Started Jul 13 04:49:10 PM PDT 24
Finished Jul 13 04:49:16 PM PDT 24
Peak memory 198504 kb
Host smart-7fcdb386-e283-49ae-8bb4-ee2e7e9c5744
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699891044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.3699891044
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.944650544
Short name T549
Test name
Test status
Simulation time 47724171 ps
CPU time 1.01 seconds
Started Jul 13 04:49:10 PM PDT 24
Finished Jul 13 04:49:11 PM PDT 24
Peak memory 197204 kb
Host smart-044301a4-9c59-4173-aebc-dceb6bca0887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944650544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.944650544
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3468033770
Short name T221
Test name
Test status
Simulation time 70307715 ps
CPU time 1.08 seconds
Started Jul 13 04:49:10 PM PDT 24
Finished Jul 13 04:49:13 PM PDT 24
Peak memory 196240 kb
Host smart-1fcef1d2-1e41-4c90-8caa-1366375c9178
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468033770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3468033770
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.2483791699
Short name T650
Test name
Test status
Simulation time 24949119587 ps
CPU time 50.65 seconds
Started Jul 13 04:49:13 PM PDT 24
Finished Jul 13 04:50:05 PM PDT 24
Peak memory 198708 kb
Host smart-1cd647ce-84ce-4054-a164-6b32df90865a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483791699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.2483791699
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.930044596
Short name T611
Test name
Test status
Simulation time 198817104577 ps
CPU time 1220.39 seconds
Started Jul 13 04:49:08 PM PDT 24
Finished Jul 13 05:09:29 PM PDT 24
Peak memory 198872 kb
Host smart-260f27df-4785-42f3-8c13-b3b81ef830a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=930044596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.930044596
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.55803500
Short name T201
Test name
Test status
Simulation time 45153920 ps
CPU time 0.6 seconds
Started Jul 13 04:49:20 PM PDT 24
Finished Jul 13 04:49:23 PM PDT 24
Peak memory 194676 kb
Host smart-4729c284-2b0b-4d92-b6e3-5a71553a1eff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55803500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.55803500
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.106780348
Short name T52
Test name
Test status
Simulation time 188867589 ps
CPU time 0.73 seconds
Started Jul 13 04:49:08 PM PDT 24
Finished Jul 13 04:49:09 PM PDT 24
Peak memory 195852 kb
Host smart-5a592c0f-010e-41a2-bcc4-044cf391afc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106780348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.106780348
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.319299409
Short name T375
Test name
Test status
Simulation time 651740144 ps
CPU time 11.69 seconds
Started Jul 13 04:49:08 PM PDT 24
Finished Jul 13 04:49:20 PM PDT 24
Peak memory 197544 kb
Host smart-683e5354-254c-410d-b25e-ef86c6636c33
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319299409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.319299409
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2703414235
Short name T13
Test name
Test status
Simulation time 181032665 ps
CPU time 0.86 seconds
Started Jul 13 04:49:13 PM PDT 24
Finished Jul 13 04:49:15 PM PDT 24
Peak memory 197700 kb
Host smart-5704c997-d150-4286-908a-96ac7453cc71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703414235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2703414235
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1576967016
Short name T106
Test name
Test status
Simulation time 246728245 ps
CPU time 1.03 seconds
Started Jul 13 04:49:13 PM PDT 24
Finished Jul 13 04:49:15 PM PDT 24
Peak memory 197316 kb
Host smart-9521ea50-8df5-4936-8dc4-9484b94713d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576967016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1576967016
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.4238183933
Short name T495
Test name
Test status
Simulation time 109499838 ps
CPU time 2.26 seconds
Started Jul 13 04:49:11 PM PDT 24
Finished Jul 13 04:49:14 PM PDT 24
Peak memory 198684 kb
Host smart-3e21ab8b-3fab-435a-ab30-df658c108b6a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238183933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.4238183933
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3974993605
Short name T599
Test name
Test status
Simulation time 99005512 ps
CPU time 2.38 seconds
Started Jul 13 04:49:10 PM PDT 24
Finished Jul 13 04:49:14 PM PDT 24
Peak memory 197848 kb
Host smart-82cc9bf5-df35-4aea-a968-c6166f977d5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974993605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3974993605
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.2399791549
Short name T454
Test name
Test status
Simulation time 52987174 ps
CPU time 1.04 seconds
Started Jul 13 04:49:11 PM PDT 24
Finished Jul 13 04:49:14 PM PDT 24
Peak memory 196632 kb
Host smart-e126d684-88ce-467c-8412-4faded04c830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399791549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2399791549
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.903604604
Short name T672
Test name
Test status
Simulation time 68049895 ps
CPU time 0.68 seconds
Started Jul 13 04:49:11 PM PDT 24
Finished Jul 13 04:49:13 PM PDT 24
Peak memory 194756 kb
Host smart-a5f32f9f-cceb-4459-8dc5-dbcd41091736
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903604604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.903604604
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3144520630
Short name T655
Test name
Test status
Simulation time 4005626466 ps
CPU time 4.93 seconds
Started Jul 13 04:49:11 PM PDT 24
Finished Jul 13 04:49:18 PM PDT 24
Peak memory 198540 kb
Host smart-fbcb415b-994f-4d0a-9fa4-e9f5816ffefa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144520630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3144520630
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3457727158
Short name T458
Test name
Test status
Simulation time 50825311 ps
CPU time 1.14 seconds
Started Jul 13 04:49:09 PM PDT 24
Finished Jul 13 04:49:11 PM PDT 24
Peak memory 197164 kb
Host smart-0fe7e09e-98d3-4319-a750-c1d1ace032a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457727158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3457727158
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2988471611
Short name T236
Test name
Test status
Simulation time 264125345 ps
CPU time 1.23 seconds
Started Jul 13 04:49:10 PM PDT 24
Finished Jul 13 04:49:12 PM PDT 24
Peak memory 196528 kb
Host smart-be5e0d84-43e0-4e8e-843a-301b37b9b1a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988471611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2988471611
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.1092416565
Short name T204
Test name
Test status
Simulation time 14275725850 ps
CPU time 181.64 seconds
Started Jul 13 04:49:09 PM PDT 24
Finished Jul 13 04:52:12 PM PDT 24
Peak memory 198804 kb
Host smart-0d828572-5809-4bcf-8a74-f329280bbcfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092416565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.1092416565
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.2503054081
Short name T620
Test name
Test status
Simulation time 12682552 ps
CPU time 0.59 seconds
Started Jul 13 04:49:18 PM PDT 24
Finished Jul 13 04:49:20 PM PDT 24
Peak memory 194624 kb
Host smart-313d1578-a320-4dba-af9c-5d3191514b28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503054081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2503054081
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3751838038
Short name T576
Test name
Test status
Simulation time 133351804 ps
CPU time 0.84 seconds
Started Jul 13 04:49:23 PM PDT 24
Finished Jul 13 04:49:25 PM PDT 24
Peak memory 196724 kb
Host smart-d35594b8-3321-4050-a4ef-67f1643c6686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751838038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3751838038
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.312052885
Short name T316
Test name
Test status
Simulation time 860048882 ps
CPU time 10.71 seconds
Started Jul 13 04:49:18 PM PDT 24
Finished Jul 13 04:49:30 PM PDT 24
Peak memory 197572 kb
Host smart-3cec0392-1a01-42d4-8772-b425fb299510
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312052885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.312052885
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.344721947
Short name T505
Test name
Test status
Simulation time 84977292 ps
CPU time 1.02 seconds
Started Jul 13 04:49:20 PM PDT 24
Finished Jul 13 04:49:23 PM PDT 24
Peak memory 198380 kb
Host smart-72d8cb32-2e37-462e-815b-5e86303013d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344721947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.344721947
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.1705547191
Short name T638
Test name
Test status
Simulation time 37108622 ps
CPU time 1.16 seconds
Started Jul 13 04:49:20 PM PDT 24
Finished Jul 13 04:49:24 PM PDT 24
Peak memory 196684 kb
Host smart-336ed28a-7493-4a54-b578-54ec07238711
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705547191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.1705547191
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3635272784
Short name T50
Test name
Test status
Simulation time 66611932 ps
CPU time 2.49 seconds
Started Jul 13 04:49:19 PM PDT 24
Finished Jul 13 04:49:24 PM PDT 24
Peak memory 198760 kb
Host smart-e07a7593-e94a-430b-a088-ed4b03a5f868
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635272784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3635272784
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.1960192145
Short name T200
Test name
Test status
Simulation time 58455212 ps
CPU time 0.87 seconds
Started Jul 13 04:49:22 PM PDT 24
Finished Jul 13 04:49:24 PM PDT 24
Peak memory 195000 kb
Host smart-13566c66-2918-4ffa-bd4c-82a44e86aef6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960192145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.1960192145
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3280320269
Short name T215
Test name
Test status
Simulation time 25168404 ps
CPU time 0.93 seconds
Started Jul 13 04:49:19 PM PDT 24
Finished Jul 13 04:49:22 PM PDT 24
Peak memory 196596 kb
Host smart-3d6ef36e-be18-4a39-b17a-80c148ba4e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280320269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3280320269
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.886185364
Short name T262
Test name
Test status
Simulation time 36099582 ps
CPU time 0.86 seconds
Started Jul 13 04:49:21 PM PDT 24
Finished Jul 13 04:49:24 PM PDT 24
Peak memory 197084 kb
Host smart-ef08d85d-48fe-4d39-a12b-b5605ec4811e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886185364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup
_pulldown.886185364
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.2719592415
Short name T4
Test name
Test status
Simulation time 238934167 ps
CPU time 3.14 seconds
Started Jul 13 04:49:20 PM PDT 24
Finished Jul 13 04:49:25 PM PDT 24
Peak memory 198624 kb
Host smart-bd48a621-b6f1-4043-b882-d41cb92248fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719592415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.2719592415
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2439908251
Short name T377
Test name
Test status
Simulation time 148101353 ps
CPU time 0.97 seconds
Started Jul 13 04:49:20 PM PDT 24
Finished Jul 13 04:49:23 PM PDT 24
Peak memory 197012 kb
Host smart-e20b9be1-9cdd-4d34-a277-95be9b8ddc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439908251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2439908251
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3347800628
Short name T132
Test name
Test status
Simulation time 69965948 ps
CPU time 1.2 seconds
Started Jul 13 04:49:20 PM PDT 24
Finished Jul 13 04:49:23 PM PDT 24
Peak memory 197000 kb
Host smart-f5fc33a0-c888-4300-a634-91704077e5ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347800628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3347800628
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2881546995
Short name T452
Test name
Test status
Simulation time 41550476421 ps
CPU time 141.74 seconds
Started Jul 13 04:49:21 PM PDT 24
Finished Jul 13 04:51:45 PM PDT 24
Peak memory 198808 kb
Host smart-19085e5f-33c8-4ca2-a584-5b0c4292effc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881546995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2881546995
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.1421852357
Short name T664
Test name
Test status
Simulation time 124813142233 ps
CPU time 747.19 seconds
Started Jul 13 04:49:18 PM PDT 24
Finished Jul 13 05:01:46 PM PDT 24
Peak memory 198844 kb
Host smart-52d1e472-7f0a-4eac-9096-0ec7da94f8e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1421852357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.1421852357
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3358625859
Short name T567
Test name
Test status
Simulation time 10855055 ps
CPU time 0.58 seconds
Started Jul 13 04:49:18 PM PDT 24
Finished Jul 13 04:49:21 PM PDT 24
Peak memory 193356 kb
Host smart-c1a02a90-a117-4d97-bce8-73d8abbb7d4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358625859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3358625859
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.3450021558
Short name T398
Test name
Test status
Simulation time 35959378 ps
CPU time 0.85 seconds
Started Jul 13 04:49:17 PM PDT 24
Finished Jul 13 04:49:18 PM PDT 24
Peak memory 196588 kb
Host smart-1ecf8edc-ee29-4ce9-af82-757f302366e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450021558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.3450021558
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2883680427
Short name T700
Test name
Test status
Simulation time 376408847 ps
CPU time 5.39 seconds
Started Jul 13 04:49:18 PM PDT 24
Finished Jul 13 04:49:25 PM PDT 24
Peak memory 197800 kb
Host smart-ad625f88-0dbe-4fc1-bf33-f80b17ddd548
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883680427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2883680427
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.2713472576
Short name T137
Test name
Test status
Simulation time 40515800 ps
CPU time 0.8 seconds
Started Jul 13 04:49:16 PM PDT 24
Finished Jul 13 04:49:17 PM PDT 24
Peak memory 196404 kb
Host smart-3800d039-c515-454b-984c-f4ea84a71119
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713472576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.2713472576
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.2388995500
Short name T443
Test name
Test status
Simulation time 180999378 ps
CPU time 1.29 seconds
Started Jul 13 04:49:20 PM PDT 24
Finished Jul 13 04:49:24 PM PDT 24
Peak memory 197684 kb
Host smart-5438df97-d7c3-4fc5-87fb-23da953b2122
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388995500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.2388995500
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.126894272
Short name T116
Test name
Test status
Simulation time 52784392 ps
CPU time 1.44 seconds
Started Jul 13 04:49:17 PM PDT 24
Finished Jul 13 04:49:19 PM PDT 24
Peak memory 197340 kb
Host smart-216e4ff4-a3d9-4a3a-b493-31502fab8708
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126894272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.gpio_intr_with_filter_rand_intr_event.126894272
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.151173653
Short name T526
Test name
Test status
Simulation time 145972411 ps
CPU time 3.32 seconds
Started Jul 13 04:49:17 PM PDT 24
Finished Jul 13 04:49:22 PM PDT 24
Peak memory 197564 kb
Host smart-fbd68f9f-f6a1-4b6e-b030-9b2e0507a24f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151173653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
151173653
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1286472276
Short name T16
Test name
Test status
Simulation time 105730570 ps
CPU time 0.63 seconds
Started Jul 13 04:49:17 PM PDT 24
Finished Jul 13 04:49:19 PM PDT 24
Peak memory 194868 kb
Host smart-7823d0e1-38d4-4336-9bee-97a6bc2e6aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286472276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1286472276
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.948639185
Short name T156
Test name
Test status
Simulation time 61786032 ps
CPU time 1.16 seconds
Started Jul 13 04:49:17 PM PDT 24
Finished Jul 13 04:49:20 PM PDT 24
Peak memory 196624 kb
Host smart-67751eff-05e1-404c-be91-787efba2916b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948639185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.948639185
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.4051270797
Short name T354
Test name
Test status
Simulation time 263088839 ps
CPU time 4.4 seconds
Started Jul 13 04:49:20 PM PDT 24
Finished Jul 13 04:49:26 PM PDT 24
Peak memory 198296 kb
Host smart-54ebd062-2048-4d75-bacb-6ec08d508fcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051270797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.4051270797
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.914710510
Short name T429
Test name
Test status
Simulation time 256125417 ps
CPU time 1.15 seconds
Started Jul 13 04:49:18 PM PDT 24
Finished Jul 13 04:49:21 PM PDT 24
Peak memory 197152 kb
Host smart-c5b2e6d5-c538-4ac8-ba30-41356632f105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914710510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.914710510
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.1241737018
Short name T23
Test name
Test status
Simulation time 65881681 ps
CPU time 0.92 seconds
Started Jul 13 04:49:19 PM PDT 24
Finished Jul 13 04:49:22 PM PDT 24
Peak memory 197556 kb
Host smart-88ca7cbf-8a90-41e6-a654-f0ae62438933
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241737018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.1241737018
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.4187746956
Short name T485
Test name
Test status
Simulation time 20322272538 ps
CPU time 46.64 seconds
Started Jul 13 04:49:19 PM PDT 24
Finished Jul 13 04:50:07 PM PDT 24
Peak memory 198776 kb
Host smart-ad707423-00d3-4464-aaa2-7635620426c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187746956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.4187746956
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.3384899671
Short name T64
Test name
Test status
Simulation time 32097812929 ps
CPU time 835.48 seconds
Started Jul 13 04:49:18 PM PDT 24
Finished Jul 13 05:03:14 PM PDT 24
Peak memory 198792 kb
Host smart-bddfd2e4-bc5d-45e6-b1b6-8e12f5240023
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3384899671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.3384899671
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.381428443
Short name T407
Test name
Test status
Simulation time 192934832 ps
CPU time 0.57 seconds
Started Jul 13 04:49:21 PM PDT 24
Finished Jul 13 04:49:23 PM PDT 24
Peak memory 194840 kb
Host smart-7044a283-38bc-4b36-9bf4-f676e3ae2cbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381428443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.381428443
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.28650963
Short name T127
Test name
Test status
Simulation time 42564592 ps
CPU time 0.89 seconds
Started Jul 13 04:49:18 PM PDT 24
Finished Jul 13 04:49:21 PM PDT 24
Peak memory 195888 kb
Host smart-93473a45-1f69-4649-93ec-bf7a3c7309e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28650963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.28650963
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.4194636577
Short name T74
Test name
Test status
Simulation time 478868760 ps
CPU time 24.71 seconds
Started Jul 13 04:49:19 PM PDT 24
Finished Jul 13 04:49:45 PM PDT 24
Peak memory 198704 kb
Host smart-0b39a636-7fd7-4a30-b401-8a18b4c511d4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194636577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.4194636577
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.502431820
Short name T569
Test name
Test status
Simulation time 56624996 ps
CPU time 0.92 seconds
Started Jul 13 04:49:24 PM PDT 24
Finished Jul 13 04:49:26 PM PDT 24
Peak memory 196976 kb
Host smart-299a40b7-becb-4f51-8a95-cfb4b1cbd8c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502431820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.502431820
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.1845708843
Short name T124
Test name
Test status
Simulation time 51012279 ps
CPU time 0.9 seconds
Started Jul 13 04:49:22 PM PDT 24
Finished Jul 13 04:49:24 PM PDT 24
Peak memory 197172 kb
Host smart-ba9e4543-0f7e-4d72-8dad-b245c7825ca7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845708843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.1845708843
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.1807819162
Short name T284
Test name
Test status
Simulation time 463863241 ps
CPU time 2.97 seconds
Started Jul 13 04:49:20 PM PDT 24
Finished Jul 13 04:49:25 PM PDT 24
Peak memory 198400 kb
Host smart-44183a5f-ed08-4718-ac3b-2035e3a7f9b9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807819162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.1807819162
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.1910889278
Short name T159
Test name
Test status
Simulation time 599870917 ps
CPU time 3.14 seconds
Started Jul 13 04:49:18 PM PDT 24
Finished Jul 13 04:49:23 PM PDT 24
Peak memory 196540 kb
Host smart-cbbfd5d4-9f5e-44f1-aaa5-50831fb6054b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910889278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.1910889278
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.2294374192
Short name T238
Test name
Test status
Simulation time 151126554 ps
CPU time 0.84 seconds
Started Jul 13 04:49:20 PM PDT 24
Finished Jul 13 04:49:23 PM PDT 24
Peak memory 197472 kb
Host smart-f2e77e37-1fc9-43f2-bdb9-9b4eccc713f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294374192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.2294374192
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.1512284360
Short name T145
Test name
Test status
Simulation time 89038125 ps
CPU time 0.76 seconds
Started Jul 13 04:49:17 PM PDT 24
Finished Jul 13 04:49:19 PM PDT 24
Peak memory 196044 kb
Host smart-0dc3471e-a19b-4b47-b61c-4639783665ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512284360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.1512284360
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.725225424
Short name T136
Test name
Test status
Simulation time 76767437 ps
CPU time 1.06 seconds
Started Jul 13 04:49:20 PM PDT 24
Finished Jul 13 04:49:23 PM PDT 24
Peak memory 197124 kb
Host smart-3bdeca42-0e82-4395-830e-eec1e233b28f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725225424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ran
dom_long_reg_writes_reg_reads.725225424
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2661230840
Short name T475
Test name
Test status
Simulation time 48430489 ps
CPU time 0.94 seconds
Started Jul 13 04:49:19 PM PDT 24
Finished Jul 13 04:49:22 PM PDT 24
Peak memory 197636 kb
Host smart-645e7273-9e7b-4889-81d5-358f709fa58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661230840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2661230840
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3385292959
Short name T493
Test name
Test status
Simulation time 44981258 ps
CPU time 1.22 seconds
Started Jul 13 04:49:19 PM PDT 24
Finished Jul 13 04:49:23 PM PDT 24
Peak memory 196980 kb
Host smart-ebb25a6d-4014-4456-9c7e-66386282d2df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385292959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3385292959
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.684743309
Short name T720
Test name
Test status
Simulation time 6946372786 ps
CPU time 86.88 seconds
Started Jul 13 04:49:19 PM PDT 24
Finished Jul 13 04:50:48 PM PDT 24
Peak memory 198792 kb
Host smart-4794270b-77db-4007-b8f0-fbe242fbd262
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684743309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.684743309
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.597569469
Short name T378
Test name
Test status
Simulation time 459854821414 ps
CPU time 1569.08 seconds
Started Jul 13 04:49:17 PM PDT 24
Finished Jul 13 05:15:26 PM PDT 24
Peak memory 198888 kb
Host smart-4220f232-4830-4017-a938-65129adb45fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=597569469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.597569469
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.154957351
Short name T39
Test name
Test status
Simulation time 33620081 ps
CPU time 0.57 seconds
Started Jul 13 04:49:23 PM PDT 24
Finished Jul 13 04:49:25 PM PDT 24
Peak memory 195616 kb
Host smart-48d5a1fb-6d5a-4b18-9f1f-e4901ec0ff27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154957351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.154957351
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3784989711
Short name T345
Test name
Test status
Simulation time 164859636 ps
CPU time 0.88 seconds
Started Jul 13 04:49:21 PM PDT 24
Finished Jul 13 04:49:24 PM PDT 24
Peak memory 197068 kb
Host smart-d8657ac4-fd4b-44e7-99f7-47c407e5977d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784989711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3784989711
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2532475349
Short name T424
Test name
Test status
Simulation time 223505191 ps
CPU time 6.09 seconds
Started Jul 13 04:49:19 PM PDT 24
Finished Jul 13 04:49:27 PM PDT 24
Peak memory 197368 kb
Host smart-d0d49cb4-902c-4591-870e-e41ca6a9afe0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532475349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2532475349
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.1313438665
Short name T453
Test name
Test status
Simulation time 19960408 ps
CPU time 0.65 seconds
Started Jul 13 04:49:21 PM PDT 24
Finished Jul 13 04:49:23 PM PDT 24
Peak memory 195196 kb
Host smart-ebe43938-02f8-4140-ad46-ed679b9efdd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313438665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.1313438665
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.1109991603
Short name T449
Test name
Test status
Simulation time 78997862 ps
CPU time 1.38 seconds
Started Jul 13 04:49:21 PM PDT 24
Finished Jul 13 04:49:24 PM PDT 24
Peak memory 198744 kb
Host smart-343b9bb6-b30a-4274-9924-c2fcaeffc611
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109991603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.1109991603
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.2853888898
Short name T178
Test name
Test status
Simulation time 108820072 ps
CPU time 2.52 seconds
Started Jul 13 04:49:24 PM PDT 24
Finished Jul 13 04:49:27 PM PDT 24
Peak memory 199060 kb
Host smart-0619ec6e-3a67-4d97-ac37-433d84b3c297
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853888898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.2853888898
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3669069906
Short name T121
Test name
Test status
Simulation time 474817298 ps
CPU time 2.38 seconds
Started Jul 13 04:49:20 PM PDT 24
Finished Jul 13 04:49:25 PM PDT 24
Peak memory 197360 kb
Host smart-b003d123-a4cd-4d86-b0cf-92cd9e84f688
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669069906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3669069906
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2997676705
Short name T572
Test name
Test status
Simulation time 75638501 ps
CPU time 1.36 seconds
Started Jul 13 04:49:23 PM PDT 24
Finished Jul 13 04:49:26 PM PDT 24
Peak memory 197984 kb
Host smart-fc2557cf-8e23-4c1f-aceb-902f1137a5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997676705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2997676705
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3761845401
Short name T290
Test name
Test status
Simulation time 18363836 ps
CPU time 0.86 seconds
Started Jul 13 04:49:21 PM PDT 24
Finished Jul 13 04:49:23 PM PDT 24
Peak memory 196252 kb
Host smart-0c5da88f-c54b-400c-9301-ff708b2cb525
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761845401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3761845401
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3368613564
Short name T581
Test name
Test status
Simulation time 294599937 ps
CPU time 3.73 seconds
Started Jul 13 04:49:18 PM PDT 24
Finished Jul 13 04:49:24 PM PDT 24
Peak memory 198548 kb
Host smart-fd5e3275-53f8-40a2-8274-d6121bc8a124
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368613564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3368613564
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.275055512
Short name T387
Test name
Test status
Simulation time 357208617 ps
CPU time 1.12 seconds
Started Jul 13 04:49:19 PM PDT 24
Finished Jul 13 04:49:21 PM PDT 24
Peak memory 196880 kb
Host smart-fb449578-4c25-4496-b145-6932f39a4885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275055512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.275055512
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2961726425
Short name T691
Test name
Test status
Simulation time 59633703 ps
CPU time 0.91 seconds
Started Jul 13 04:49:19 PM PDT 24
Finished Jul 13 04:49:22 PM PDT 24
Peak memory 196904 kb
Host smart-f92fc427-9001-432c-917a-a5765090f17d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961726425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2961726425
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.4235834224
Short name T684
Test name
Test status
Simulation time 9360480924 ps
CPU time 129.83 seconds
Started Jul 13 04:49:19 PM PDT 24
Finished Jul 13 04:51:31 PM PDT 24
Peak memory 198712 kb
Host smart-54b2dfa5-6170-4486-844b-fe62dd809076
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235834224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.4235834224
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.1000489679
Short name T254
Test name
Test status
Simulation time 44177192 ps
CPU time 0.58 seconds
Started Jul 13 04:49:34 PM PDT 24
Finished Jul 13 04:49:35 PM PDT 24
Peak memory 195652 kb
Host smart-0b7721d9-7c04-4f85-99d0-1df9476d42c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000489679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1000489679
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2491199404
Short name T177
Test name
Test status
Simulation time 36633460 ps
CPU time 0.84 seconds
Started Jul 13 04:49:20 PM PDT 24
Finished Jul 13 04:49:23 PM PDT 24
Peak memory 196736 kb
Host smart-35fbe269-c41e-4fa1-a414-2c31f7cf6bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491199404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2491199404
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.291963802
Short name T193
Test name
Test status
Simulation time 482245205 ps
CPU time 15.55 seconds
Started Jul 13 04:49:31 PM PDT 24
Finished Jul 13 04:49:47 PM PDT 24
Peak memory 196940 kb
Host smart-87231c7e-c695-42af-b58f-e2c80ae6222d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291963802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stres
s.291963802
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.300978269
Short name T699
Test name
Test status
Simulation time 67307019 ps
CPU time 0.72 seconds
Started Jul 13 04:49:31 PM PDT 24
Finished Jul 13 04:49:32 PM PDT 24
Peak memory 197232 kb
Host smart-c6324ad2-79b7-408b-a4b4-a490eb175a15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300978269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.300978269
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.3496427707
Short name T556
Test name
Test status
Simulation time 97627053 ps
CPU time 1.35 seconds
Started Jul 13 04:49:35 PM PDT 24
Finished Jul 13 04:49:37 PM PDT 24
Peak memory 197780 kb
Host smart-36f1c972-6469-4cda-8597-294969b9994d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496427707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.3496427707
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.594463795
Short name T401
Test name
Test status
Simulation time 178229253 ps
CPU time 1.82 seconds
Started Jul 13 04:49:31 PM PDT 24
Finished Jul 13 04:49:33 PM PDT 24
Peak memory 198560 kb
Host smart-d3379258-f70f-4a89-a2b3-6a518995b319
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594463795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.gpio_intr_with_filter_rand_intr_event.594463795
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.759581187
Short name T346
Test name
Test status
Simulation time 238681551 ps
CPU time 2.38 seconds
Started Jul 13 04:49:29 PM PDT 24
Finished Jul 13 04:49:31 PM PDT 24
Peak memory 197668 kb
Host smart-3cce46ad-4a63-4542-8852-714fd9eacab4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759581187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.
759581187
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.1081984959
Short name T595
Test name
Test status
Simulation time 22267125 ps
CPU time 0.67 seconds
Started Jul 13 04:49:18 PM PDT 24
Finished Jul 13 04:49:20 PM PDT 24
Peak memory 194888 kb
Host smart-cc6fcc1f-9774-468b-a91a-d7ea4feab3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081984959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.1081984959
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.317673440
Short name T327
Test name
Test status
Simulation time 208667202 ps
CPU time 1.19 seconds
Started Jul 13 04:49:19 PM PDT 24
Finished Jul 13 04:49:21 PM PDT 24
Peak memory 197448 kb
Host smart-2e34f394-268d-4cc3-98be-c68fcd31b7c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317673440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup
_pulldown.317673440
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.433786474
Short name T465
Test name
Test status
Simulation time 382913480 ps
CPU time 4.87 seconds
Started Jul 13 04:49:32 PM PDT 24
Finished Jul 13 04:49:38 PM PDT 24
Peak memory 198664 kb
Host smart-7cb18455-648d-4f64-b44d-9b5401356ad1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433786474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ran
dom_long_reg_writes_reg_reads.433786474
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.3743974288
Short name T271
Test name
Test status
Simulation time 38204804 ps
CPU time 0.97 seconds
Started Jul 13 04:49:18 PM PDT 24
Finished Jul 13 04:49:21 PM PDT 24
Peak memory 197168 kb
Host smart-da1b52c4-1c2d-4dbc-a7ad-8e2f91921d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743974288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.3743974288
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2010939063
Short name T404
Test name
Test status
Simulation time 96657868 ps
CPU time 0.88 seconds
Started Jul 13 04:49:23 PM PDT 24
Finished Jul 13 04:49:25 PM PDT 24
Peak memory 196740 kb
Host smart-87d3c6e7-585c-49e7-a842-0898d72f9572
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010939063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2010939063
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3130763685
Short name T119
Test name
Test status
Simulation time 7994139762 ps
CPU time 100.3 seconds
Started Jul 13 04:49:31 PM PDT 24
Finished Jul 13 04:51:12 PM PDT 24
Peak memory 198788 kb
Host smart-029946dc-3df8-41cc-8ae8-11ee24a6e364
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130763685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3130763685
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3779356221
Short name T612
Test name
Test status
Simulation time 12539856 ps
CPU time 0.59 seconds
Started Jul 13 04:49:32 PM PDT 24
Finished Jul 13 04:49:34 PM PDT 24
Peak memory 194724 kb
Host smart-0c716db3-a359-4833-913d-a60f4649c6a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779356221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3779356221
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.2574779388
Short name T528
Test name
Test status
Simulation time 44640855 ps
CPU time 0.88 seconds
Started Jul 13 04:49:33 PM PDT 24
Finished Jul 13 04:49:35 PM PDT 24
Peak memory 196068 kb
Host smart-3fb3b50d-886f-4678-a4f2-884c580b90fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574779388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.2574779388
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.4226412533
Short name T143
Test name
Test status
Simulation time 224125214 ps
CPU time 11 seconds
Started Jul 13 04:49:36 PM PDT 24
Finished Jul 13 04:49:47 PM PDT 24
Peak memory 196140 kb
Host smart-305c7173-5661-4523-acde-45bd008bd07b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226412533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.4226412533
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.601134682
Short name T552
Test name
Test status
Simulation time 362728095 ps
CPU time 1.08 seconds
Started Jul 13 04:49:31 PM PDT 24
Finished Jul 13 04:49:33 PM PDT 24
Peak memory 197284 kb
Host smart-4b252594-78fd-4222-8175-e8a6f21a7e11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601134682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.601134682
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2853631350
Short name T421
Test name
Test status
Simulation time 211013574 ps
CPU time 1.36 seconds
Started Jul 13 04:49:34 PM PDT 24
Finished Jul 13 04:49:36 PM PDT 24
Peak memory 198008 kb
Host smart-afc6c97b-7a6f-4ce6-b8d2-41c89cb96ade
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853631350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2853631350
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.207357440
Short name T490
Test name
Test status
Simulation time 1313353609 ps
CPU time 3.04 seconds
Started Jul 13 04:49:33 PM PDT 24
Finished Jul 13 04:49:37 PM PDT 24
Peak memory 198200 kb
Host smart-1bb70917-67f1-4552-83f6-25472e75b57d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207357440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.207357440
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.4138136284
Short name T640
Test name
Test status
Simulation time 88430963 ps
CPU time 2.71 seconds
Started Jul 13 04:49:32 PM PDT 24
Finished Jul 13 04:49:35 PM PDT 24
Peak memory 198732 kb
Host smart-aaeeefea-ebea-49e0-a51d-29e8a6c50ba4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138136284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.4138136284
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.80990086
Short name T323
Test name
Test status
Simulation time 19703111 ps
CPU time 0.73 seconds
Started Jul 13 04:49:31 PM PDT 24
Finished Jul 13 04:49:32 PM PDT 24
Peak memory 195960 kb
Host smart-f27ccbb0-d0b4-4e5f-971e-18f1b14e876a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80990086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.80990086
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.473213289
Short name T374
Test name
Test status
Simulation time 111568826 ps
CPU time 0.74 seconds
Started Jul 13 04:49:29 PM PDT 24
Finished Jul 13 04:49:30 PM PDT 24
Peak memory 196068 kb
Host smart-fe43bee7-37cb-4ef5-9179-80d3af543f9f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473213289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.473213289
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3411628330
Short name T419
Test name
Test status
Simulation time 305307149 ps
CPU time 1.47 seconds
Started Jul 13 04:49:31 PM PDT 24
Finished Jul 13 04:49:32 PM PDT 24
Peak memory 198632 kb
Host smart-d5606c2b-951b-4d60-a0cb-6da915b6062e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411628330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3411628330
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.1537954613
Short name T303
Test name
Test status
Simulation time 54611755 ps
CPU time 1.38 seconds
Started Jul 13 04:49:32 PM PDT 24
Finished Jul 13 04:49:34 PM PDT 24
Peak memory 197000 kb
Host smart-4b970752-173f-4988-bcf5-6bb4f9f8d43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537954613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.1537954613
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2661020940
Short name T709
Test name
Test status
Simulation time 18473321 ps
CPU time 0.74 seconds
Started Jul 13 04:49:30 PM PDT 24
Finished Jul 13 04:49:31 PM PDT 24
Peak memory 195920 kb
Host smart-ab4cf08a-02ba-40aa-8f83-439f08b80f9b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661020940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2661020940
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2425976391
Short name T324
Test name
Test status
Simulation time 31175171005 ps
CPU time 191.94 seconds
Started Jul 13 04:49:36 PM PDT 24
Finished Jul 13 04:52:48 PM PDT 24
Peak memory 198816 kb
Host smart-693afb34-c93b-4e47-8b0f-fdaff487343f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425976391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2425976391
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.295597728
Short name T473
Test name
Test status
Simulation time 217201430592 ps
CPU time 1612.31 seconds
Started Jul 13 04:49:37 PM PDT 24
Finished Jul 13 05:16:31 PM PDT 24
Peak memory 198840 kb
Host smart-aad94c95-4ed9-4872-a5fb-4ff8b1fae143
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=295597728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.295597728
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.4234767736
Short name T212
Test name
Test status
Simulation time 14540763 ps
CPU time 0.59 seconds
Started Jul 13 04:49:37 PM PDT 24
Finished Jul 13 04:49:39 PM PDT 24
Peak memory 194460 kb
Host smart-90f62242-0359-43f6-b0f2-ccd545698e4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234767736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.4234767736
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.194173915
Short name T157
Test name
Test status
Simulation time 38333084 ps
CPU time 0.87 seconds
Started Jul 13 04:49:29 PM PDT 24
Finished Jul 13 04:49:31 PM PDT 24
Peak memory 197004 kb
Host smart-3988a7ee-4daa-4d6b-a7cd-40968f75db59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194173915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.194173915
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3353222884
Short name T661
Test name
Test status
Simulation time 523319941 ps
CPU time 18.33 seconds
Started Jul 13 04:49:33 PM PDT 24
Finished Jul 13 04:49:52 PM PDT 24
Peak memory 198560 kb
Host smart-79e31d40-f1b1-4544-aae3-57b40d1ce12c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353222884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3353222884
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2171276936
Short name T583
Test name
Test status
Simulation time 28567569 ps
CPU time 0.72 seconds
Started Jul 13 04:49:32 PM PDT 24
Finished Jul 13 04:49:34 PM PDT 24
Peak memory 195340 kb
Host smart-552af8d8-3273-49a6-a56f-75f7ea20e8b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171276936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2171276936
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2845019554
Short name T395
Test name
Test status
Simulation time 102120688 ps
CPU time 1.24 seconds
Started Jul 13 04:49:32 PM PDT 24
Finished Jul 13 04:49:35 PM PDT 24
Peak memory 196464 kb
Host smart-9ff1292f-acda-41d0-aa0c-c655b6ac4b38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845019554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2845019554
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.4263010310
Short name T68
Test name
Test status
Simulation time 110409271 ps
CPU time 2.23 seconds
Started Jul 13 04:49:32 PM PDT 24
Finished Jul 13 04:49:36 PM PDT 24
Peak memory 198616 kb
Host smart-36c95cd1-5765-4030-a511-2ada760673ea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263010310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.4263010310
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.2130165952
Short name T351
Test name
Test status
Simulation time 73576256 ps
CPU time 2.23 seconds
Started Jul 13 04:49:33 PM PDT 24
Finished Jul 13 04:49:36 PM PDT 24
Peak memory 197788 kb
Host smart-7a3ee907-79f5-4241-9904-5660b0819fd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130165952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.2130165952
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.3302915596
Short name T189
Test name
Test status
Simulation time 74764333 ps
CPU time 0.73 seconds
Started Jul 13 04:49:37 PM PDT 24
Finished Jul 13 04:49:39 PM PDT 24
Peak memory 195800 kb
Host smart-cbdb4303-b8b7-4ecc-b40e-3f70a3dbefa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302915596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.3302915596
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.1704738601
Short name T241
Test name
Test status
Simulation time 46328387 ps
CPU time 0.75 seconds
Started Jul 13 04:49:32 PM PDT 24
Finished Jul 13 04:49:33 PM PDT 24
Peak memory 195988 kb
Host smart-48df4c43-8ba1-498a-8afe-898b520a4805
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704738601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.1704738601
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2707807621
Short name T268
Test name
Test status
Simulation time 235400642 ps
CPU time 2.16 seconds
Started Jul 13 04:49:34 PM PDT 24
Finished Jul 13 04:49:37 PM PDT 24
Peak memory 198600 kb
Host smart-d7a20505-6915-456a-8c15-354603274952
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707807621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2707807621
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1084946801
Short name T258
Test name
Test status
Simulation time 58114688 ps
CPU time 0.94 seconds
Started Jul 13 04:49:31 PM PDT 24
Finished Jul 13 04:49:33 PM PDT 24
Peak memory 196136 kb
Host smart-cb9470b4-6001-4363-832e-42de13679e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084946801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1084946801
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.3663459340
Short name T256
Test name
Test status
Simulation time 149500073 ps
CPU time 0.94 seconds
Started Jul 13 04:49:30 PM PDT 24
Finished Jul 13 04:49:31 PM PDT 24
Peak memory 197004 kb
Host smart-6e148471-38e4-44f3-b57a-b54f0fc4ff20
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663459340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.3663459340
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.3332138643
Short name T492
Test name
Test status
Simulation time 17596550259 ps
CPU time 111.18 seconds
Started Jul 13 04:49:35 PM PDT 24
Finished Jul 13 04:51:27 PM PDT 24
Peak memory 198772 kb
Host smart-a56d9e85-4ed4-48f6-a387-dd6c93f114d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332138643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.3332138643
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.3013411332
Short name T652
Test name
Test status
Simulation time 37815060 ps
CPU time 0.6 seconds
Started Jul 13 04:48:29 PM PDT 24
Finished Jul 13 04:48:31 PM PDT 24
Peak memory 194752 kb
Host smart-af663965-a9fb-4eb4-96c1-f0372441200d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013411332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3013411332
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3969075095
Short name T147
Test name
Test status
Simulation time 171360079 ps
CPU time 1.01 seconds
Started Jul 13 04:48:30 PM PDT 24
Finished Jul 13 04:48:33 PM PDT 24
Peak memory 196480 kb
Host smart-3a94dd98-310b-4dbc-9281-281b3c1466f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969075095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3969075095
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.457431507
Short name T713
Test name
Test status
Simulation time 141423567 ps
CPU time 7.16 seconds
Started Jul 13 04:48:30 PM PDT 24
Finished Jul 13 04:48:40 PM PDT 24
Peak memory 198572 kb
Host smart-a56edc91-8a31-4079-8d55-cbab95dbfaac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457431507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.457431507
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.1206711674
Short name T222
Test name
Test status
Simulation time 621392503 ps
CPU time 0.77 seconds
Started Jul 13 04:48:29 PM PDT 24
Finished Jul 13 04:48:32 PM PDT 24
Peak memory 196588 kb
Host smart-288b81a5-92ee-4aaa-8e98-95b1b4998be8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206711674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.1206711674
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.790364468
Short name T529
Test name
Test status
Simulation time 134712621 ps
CPU time 0.85 seconds
Started Jul 13 04:48:32 PM PDT 24
Finished Jul 13 04:48:35 PM PDT 24
Peak memory 196748 kb
Host smart-e196ccb5-c631-48c5-94dd-49dffb3c0128
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790364468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.790364468
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.4135178700
Short name T649
Test name
Test status
Simulation time 80839125 ps
CPU time 1.91 seconds
Started Jul 13 04:48:33 PM PDT 24
Finished Jul 13 04:48:37 PM PDT 24
Peak memory 198600 kb
Host smart-816fce0e-0c5b-4a2f-a638-01aab7b89e21
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135178700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.4135178700
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1155747474
Short name T708
Test name
Test status
Simulation time 499048234 ps
CPU time 1.43 seconds
Started Jul 13 04:48:30 PM PDT 24
Finished Jul 13 04:48:34 PM PDT 24
Peak memory 197336 kb
Host smart-864456bd-4653-4955-a636-f65c8384381b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155747474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1155747474
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.4288484735
Short name T436
Test name
Test status
Simulation time 144258929 ps
CPU time 1.14 seconds
Started Jul 13 04:48:22 PM PDT 24
Finished Jul 13 04:48:26 PM PDT 24
Peak memory 198556 kb
Host smart-e64ad32c-9019-4812-a4c9-d7e7fe126403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288484735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.4288484735
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1525620967
Short name T138
Test name
Test status
Simulation time 113060182 ps
CPU time 1.05 seconds
Started Jul 13 04:48:34 PM PDT 24
Finished Jul 13 04:48:37 PM PDT 24
Peak memory 196828 kb
Host smart-79d28540-d42c-45c4-a23e-a7865e04ce1b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525620967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1525620967
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2530060409
Short name T710
Test name
Test status
Simulation time 145358616 ps
CPU time 2.08 seconds
Started Jul 13 04:48:42 PM PDT 24
Finished Jul 13 04:48:46 PM PDT 24
Peak memory 198584 kb
Host smart-1c28bbbc-474c-4f37-9caa-7d57fa11124e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530060409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2530060409
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_smoke.3694842053
Short name T647
Test name
Test status
Simulation time 1039505147 ps
CPU time 1.48 seconds
Started Jul 13 04:48:24 PM PDT 24
Finished Jul 13 04:48:28 PM PDT 24
Peak memory 197408 kb
Host smart-a5ba5f66-1553-4810-943a-e716c134e992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694842053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3694842053
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1608231216
Short name T372
Test name
Test status
Simulation time 58573788 ps
CPU time 1.15 seconds
Started Jul 13 04:48:23 PM PDT 24
Finished Jul 13 04:48:27 PM PDT 24
Peak memory 197088 kb
Host smart-6adb3c1b-f91c-42ba-acb0-1b49ccc0f90d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608231216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1608231216
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1767720942
Short name T439
Test name
Test status
Simulation time 16793161119 ps
CPU time 106.18 seconds
Started Jul 13 04:48:30 PM PDT 24
Finished Jul 13 04:50:18 PM PDT 24
Peak memory 198756 kb
Host smart-5acbe8dd-06d6-4ad2-822d-fde277be8ed0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767720942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1767720942
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1526476596
Short name T531
Test name
Test status
Simulation time 41924415 ps
CPU time 0.6 seconds
Started Jul 13 04:49:43 PM PDT 24
Finished Jul 13 04:49:46 PM PDT 24
Peak memory 194552 kb
Host smart-3fe1c24c-b6c8-4836-a82d-59a924d089ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526476596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1526476596
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.2512276550
Short name T432
Test name
Test status
Simulation time 24548645 ps
CPU time 0.89 seconds
Started Jul 13 04:49:33 PM PDT 24
Finished Jul 13 04:49:35 PM PDT 24
Peak memory 195588 kb
Host smart-e2590aaa-76b2-4a1c-96c1-8035d7169287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512276550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.2512276550
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.1458878981
Short name T686
Test name
Test status
Simulation time 637680110 ps
CPU time 20.79 seconds
Started Jul 13 04:49:36 PM PDT 24
Finished Jul 13 04:49:57 PM PDT 24
Peak memory 197744 kb
Host smart-e1ebd50a-1758-4f6d-acba-d393b3a181b3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458878981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.1458878981
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2816222961
Short name T179
Test name
Test status
Simulation time 21623807 ps
CPU time 0.64 seconds
Started Jul 13 04:49:32 PM PDT 24
Finished Jul 13 04:49:33 PM PDT 24
Peak memory 195016 kb
Host smart-3c486a73-7044-4b95-b506-bba1297cb9ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816222961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2816222961
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2990634651
Short name T286
Test name
Test status
Simulation time 49691996 ps
CPU time 1.39 seconds
Started Jul 13 04:49:33 PM PDT 24
Finished Jul 13 04:49:35 PM PDT 24
Peak memory 197596 kb
Host smart-338e8a36-0645-4644-bb43-227e65bbf96a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990634651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2990634651
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1057176931
Short name T184
Test name
Test status
Simulation time 56281350 ps
CPU time 2.25 seconds
Started Jul 13 04:49:37 PM PDT 24
Finished Jul 13 04:49:40 PM PDT 24
Peak memory 198580 kb
Host smart-bd3f3dba-a47e-4b57-96d3-0d1d7829d610
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057176931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1057176931
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2780595624
Short name T263
Test name
Test status
Simulation time 143504762 ps
CPU time 3.08 seconds
Started Jul 13 04:49:34 PM PDT 24
Finished Jul 13 04:49:38 PM PDT 24
Peak memory 198668 kb
Host smart-3508ce69-e40e-40c3-8584-9929cee72d1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780595624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2780595624
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1666638642
Short name T564
Test name
Test status
Simulation time 42919642 ps
CPU time 1.05 seconds
Started Jul 13 04:49:31 PM PDT 24
Finished Jul 13 04:49:33 PM PDT 24
Peak memory 196444 kb
Host smart-85561a98-cc97-42dc-ad66-7edbbc6ac9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666638642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1666638642
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.559834364
Short name T144
Test name
Test status
Simulation time 63057317 ps
CPU time 1.37 seconds
Started Jul 13 04:49:32 PM PDT 24
Finished Jul 13 04:49:35 PM PDT 24
Peak memory 197572 kb
Host smart-20ff1986-d21f-4237-9f33-ce787d7fe972
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559834364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup
_pulldown.559834364
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3488875866
Short name T2
Test name
Test status
Simulation time 499274995 ps
CPU time 3.64 seconds
Started Jul 13 04:49:32 PM PDT 24
Finished Jul 13 04:49:37 PM PDT 24
Peak memory 198608 kb
Host smart-cdb403f2-62b9-4958-a049-639949a18ebd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488875866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3488875866
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.68754572
Short name T237
Test name
Test status
Simulation time 36085131 ps
CPU time 0.9 seconds
Started Jul 13 04:49:31 PM PDT 24
Finished Jul 13 04:49:33 PM PDT 24
Peak memory 196012 kb
Host smart-3991cb83-5f07-4ed8-aab1-f2a5b089c97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68754572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.68754572
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1717096906
Short name T287
Test name
Test status
Simulation time 162300155 ps
CPU time 1.02 seconds
Started Jul 13 04:49:34 PM PDT 24
Finished Jul 13 04:49:36 PM PDT 24
Peak memory 198000 kb
Host smart-7fbf7b9f-f51d-4b74-98dd-f54e41e6f7d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717096906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1717096906
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.265305454
Short name T302
Test name
Test status
Simulation time 7503699007 ps
CPU time 105.32 seconds
Started Jul 13 04:49:38 PM PDT 24
Finished Jul 13 04:51:24 PM PDT 24
Peak memory 198792 kb
Host smart-6c11d282-110b-49c5-aa5f-a9a26da41a6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265305454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.g
pio_stress_all.265305454
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.1838996076
Short name T162
Test name
Test status
Simulation time 13818804 ps
CPU time 0.57 seconds
Started Jul 13 04:49:44 PM PDT 24
Finished Jul 13 04:49:46 PM PDT 24
Peak memory 194656 kb
Host smart-ff2c0d08-b7f7-4980-8ee0-25c18acc958e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838996076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.1838996076
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2924412289
Short name T110
Test name
Test status
Simulation time 66152534 ps
CPU time 0.81 seconds
Started Jul 13 04:49:39 PM PDT 24
Finished Jul 13 04:49:41 PM PDT 24
Peak memory 195896 kb
Host smart-b5f4bc7f-407e-4f6d-85d2-a9fbafe161b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924412289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2924412289
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1728512938
Short name T69
Test name
Test status
Simulation time 473323270 ps
CPU time 14.53 seconds
Started Jul 13 04:49:41 PM PDT 24
Finished Jul 13 04:49:58 PM PDT 24
Peak memory 198652 kb
Host smart-9b9193d3-4fdd-4e32-86fe-ce84b045f110
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728512938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1728512938
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.255234513
Short name T299
Test name
Test status
Simulation time 249272608 ps
CPU time 0.7 seconds
Started Jul 13 04:49:40 PM PDT 24
Finished Jul 13 04:49:42 PM PDT 24
Peak memory 195272 kb
Host smart-b05cec7f-42a9-4112-a97a-b1ea47f53e06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255234513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.255234513
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.720370070
Short name T542
Test name
Test status
Simulation time 90109814 ps
CPU time 1.33 seconds
Started Jul 13 04:49:40 PM PDT 24
Finished Jul 13 04:49:43 PM PDT 24
Peak memory 197584 kb
Host smart-b597674b-f7d7-4012-93d0-3ec77e055b5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720370070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.720370070
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.3933673206
Short name T164
Test name
Test status
Simulation time 703176094 ps
CPU time 3.25 seconds
Started Jul 13 04:49:40 PM PDT 24
Finished Jul 13 04:49:46 PM PDT 24
Peak memory 198388 kb
Host smart-e341c603-0aad-453a-a588-b4f347d007a9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933673206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.3933673206
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2096415875
Short name T420
Test name
Test status
Simulation time 129325041 ps
CPU time 1.66 seconds
Started Jul 13 04:49:41 PM PDT 24
Finished Jul 13 04:49:45 PM PDT 24
Peak memory 196840 kb
Host smart-4121dd89-a6a6-4278-a07e-f23612ed88df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096415875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2096415875
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.1692341448
Short name T282
Test name
Test status
Simulation time 19835496 ps
CPU time 0.83 seconds
Started Jul 13 04:49:41 PM PDT 24
Finished Jul 13 04:49:44 PM PDT 24
Peak memory 196096 kb
Host smart-f009a848-d7a4-4a50-8781-75e2f75fb7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692341448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.1692341448
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.4124236595
Short name T496
Test name
Test status
Simulation time 77180090 ps
CPU time 1.45 seconds
Started Jul 13 04:49:40 PM PDT 24
Finished Jul 13 04:49:43 PM PDT 24
Peak memory 197616 kb
Host smart-ff8dc334-82ce-40ef-9944-cd72900ada91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124236595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.4124236595
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3431045351
Short name T300
Test name
Test status
Simulation time 158436335 ps
CPU time 2.4 seconds
Started Jul 13 04:49:41 PM PDT 24
Finished Jul 13 04:49:45 PM PDT 24
Peak memory 198624 kb
Host smart-0d08ccd1-d02b-4711-8db6-260b108ce366
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431045351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3431045351
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.1453719229
Short name T610
Test name
Test status
Simulation time 84558269 ps
CPU time 1 seconds
Started Jul 13 04:49:40 PM PDT 24
Finished Jul 13 04:49:43 PM PDT 24
Peak memory 197200 kb
Host smart-16fafedb-db92-4bcf-b889-b759c287b1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453719229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1453719229
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3182620887
Short name T635
Test name
Test status
Simulation time 45557879 ps
CPU time 1.38 seconds
Started Jul 13 04:49:38 PM PDT 24
Finished Jul 13 04:49:41 PM PDT 24
Peak memory 197336 kb
Host smart-5bd94ddb-3a48-477b-8065-08e08db7aa15
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182620887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3182620887
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3041152798
Short name T584
Test name
Test status
Simulation time 17906745037 ps
CPU time 75.66 seconds
Started Jul 13 04:49:44 PM PDT 24
Finished Jul 13 04:51:02 PM PDT 24
Peak memory 198820 kb
Host smart-f9c76957-0591-4158-8da8-a2564db5f610
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041152798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3041152798
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.829141830
Short name T61
Test name
Test status
Simulation time 53603745765 ps
CPU time 823.89 seconds
Started Jul 13 04:49:40 PM PDT 24
Finished Jul 13 05:03:26 PM PDT 24
Peak memory 198952 kb
Host smart-73428af7-8b16-4838-b6af-808b86809903
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=829141830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.829141830
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3230562287
Short name T37
Test name
Test status
Simulation time 16292820 ps
CPU time 0.59 seconds
Started Jul 13 04:49:41 PM PDT 24
Finished Jul 13 04:49:44 PM PDT 24
Peak memory 194564 kb
Host smart-0b59c6ac-1871-4be9-9d2a-df3a03c5abbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230562287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3230562287
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1168078179
Short name T339
Test name
Test status
Simulation time 36818706 ps
CPU time 0.83 seconds
Started Jul 13 04:49:53 PM PDT 24
Finished Jul 13 04:49:55 PM PDT 24
Peak memory 195936 kb
Host smart-ed699ea1-eb69-4c7d-9e99-0620572925f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168078179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1168078179
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.857510126
Short name T245
Test name
Test status
Simulation time 305924156 ps
CPU time 8.37 seconds
Started Jul 13 04:49:38 PM PDT 24
Finished Jul 13 04:49:48 PM PDT 24
Peak memory 197228 kb
Host smart-841390ca-33eb-4e66-aad9-5ce84c8c70e4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857510126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stres
s.857510126
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.843305344
Short name T575
Test name
Test status
Simulation time 93282518 ps
CPU time 1.09 seconds
Started Jul 13 04:49:42 PM PDT 24
Finished Jul 13 04:49:45 PM PDT 24
Peak memory 197184 kb
Host smart-294475bd-928c-491c-9b69-4f1db621d49b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843305344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.843305344
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2024760530
Short name T626
Test name
Test status
Simulation time 38156475 ps
CPU time 0.88 seconds
Started Jul 13 04:49:45 PM PDT 24
Finished Jul 13 04:49:48 PM PDT 24
Peak memory 196000 kb
Host smart-7a8e2c63-1297-4729-b97c-0a30ed404b5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024760530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2024760530
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3299203116
Short name T272
Test name
Test status
Simulation time 92908578 ps
CPU time 4 seconds
Started Jul 13 04:49:37 PM PDT 24
Finished Jul 13 04:49:42 PM PDT 24
Peak memory 198668 kb
Host smart-b9a64309-eb78-4465-bda9-47222fcc8741
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299203116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3299203116
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.524442707
Short name T520
Test name
Test status
Simulation time 567882642 ps
CPU time 2.73 seconds
Started Jul 13 04:49:43 PM PDT 24
Finished Jul 13 04:49:47 PM PDT 24
Peak memory 197940 kb
Host smart-fd05d037-dda6-4b48-accc-b7879f6dc45e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524442707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
524442707
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.4252004306
Short name T498
Test name
Test status
Simulation time 23812410 ps
CPU time 0.76 seconds
Started Jul 13 04:49:40 PM PDT 24
Finished Jul 13 04:49:42 PM PDT 24
Peak memory 196744 kb
Host smart-a450726c-3217-48d4-b2f0-2d5ac13f16a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252004306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.4252004306
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.660129425
Short name T703
Test name
Test status
Simulation time 192213998 ps
CPU time 1.32 seconds
Started Jul 13 04:49:43 PM PDT 24
Finished Jul 13 04:49:46 PM PDT 24
Peak memory 198692 kb
Host smart-0d7c2199-b892-491d-bbc7-8c53ac5ed9c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660129425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.660129425
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1079903369
Short name T687
Test name
Test status
Simulation time 164252697 ps
CPU time 1.97 seconds
Started Jul 13 04:49:41 PM PDT 24
Finished Jul 13 04:49:45 PM PDT 24
Peak memory 198524 kb
Host smart-4bd9a165-9cbf-4927-a9ab-ce9e1425b67c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079903369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1079903369
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.4283482999
Short name T607
Test name
Test status
Simulation time 227730779 ps
CPU time 1.11 seconds
Started Jul 13 04:49:43 PM PDT 24
Finished Jul 13 04:49:46 PM PDT 24
Peak memory 195336 kb
Host smart-29de1128-682b-479f-a5c6-e64398f2e177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283482999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.4283482999
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.916843794
Short name T577
Test name
Test status
Simulation time 33937387 ps
CPU time 0.91 seconds
Started Jul 13 04:49:45 PM PDT 24
Finished Jul 13 04:49:47 PM PDT 24
Peak memory 196716 kb
Host smart-f2b725d8-7c04-416f-b25d-aab7e4457a04
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916843794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.916843794
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.2967719094
Short name T15
Test name
Test status
Simulation time 77998452528 ps
CPU time 839.1 seconds
Started Jul 13 04:49:40 PM PDT 24
Finished Jul 13 05:03:40 PM PDT 24
Peak memory 198800 kb
Host smart-acb2900c-d863-4b93-8289-eae28dc8f847
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2967719094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.2967719094
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.28775439
Short name T589
Test name
Test status
Simulation time 44633014 ps
CPU time 0.59 seconds
Started Jul 13 04:49:45 PM PDT 24
Finished Jul 13 04:49:47 PM PDT 24
Peak memory 194796 kb
Host smart-ef4b5ee1-fc63-486d-a578-cc98ede1767b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28775439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.28775439
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3216622872
Short name T171
Test name
Test status
Simulation time 73095721 ps
CPU time 0.75 seconds
Started Jul 13 04:49:39 PM PDT 24
Finished Jul 13 04:49:41 PM PDT 24
Peak memory 196532 kb
Host smart-3e856963-2b2e-447f-9d31-b67a0d38eba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216622872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3216622872
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1286862790
Short name T469
Test name
Test status
Simulation time 3061177525 ps
CPU time 27.46 seconds
Started Jul 13 04:49:38 PM PDT 24
Finished Jul 13 04:50:06 PM PDT 24
Peak memory 198708 kb
Host smart-42bb6ffd-5609-44a8-9405-902e85cd6cab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286862790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1286862790
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.230234478
Short name T169
Test name
Test status
Simulation time 151474422 ps
CPU time 0.99 seconds
Started Jul 13 04:49:41 PM PDT 24
Finished Jul 13 04:49:45 PM PDT 24
Peak memory 198308 kb
Host smart-70111e6b-088c-4b1c-880e-9834a878233d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230234478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.230234478
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.3099423977
Short name T514
Test name
Test status
Simulation time 140048466 ps
CPU time 1.2 seconds
Started Jul 13 04:49:44 PM PDT 24
Finished Jul 13 04:49:47 PM PDT 24
Peak memory 196680 kb
Host smart-cc59a304-da60-45b1-b4fb-b4d498927610
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099423977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.3099423977
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3484641132
Short name T167
Test name
Test status
Simulation time 280154395 ps
CPU time 2.78 seconds
Started Jul 13 04:49:44 PM PDT 24
Finished Jul 13 04:49:49 PM PDT 24
Peak memory 197128 kb
Host smart-1b5460e4-294a-46a7-8487-9e117ce58a69
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484641132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3484641132
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3866666284
Short name T621
Test name
Test status
Simulation time 97532850 ps
CPU time 1.98 seconds
Started Jul 13 04:49:37 PM PDT 24
Finished Jul 13 04:49:39 PM PDT 24
Peak memory 196568 kb
Host smart-011ec69d-7de0-44a3-b0d4-ef239a550798
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866666284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3866666284
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.3643230083
Short name T617
Test name
Test status
Simulation time 59399149 ps
CPU time 0.81 seconds
Started Jul 13 04:49:40 PM PDT 24
Finished Jul 13 04:49:42 PM PDT 24
Peak memory 197860 kb
Host smart-3f6199a2-d0ec-48f3-833b-7d8f36ecd15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643230083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.3643230083
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.751666918
Short name T547
Test name
Test status
Simulation time 255833873 ps
CPU time 1.29 seconds
Started Jul 13 04:49:39 PM PDT 24
Finished Jul 13 04:49:41 PM PDT 24
Peak memory 197544 kb
Host smart-6016e22f-ca1e-4409-a741-37b75ff6e366
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751666918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup
_pulldown.751666918
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2327987492
Short name T58
Test name
Test status
Simulation time 745399652 ps
CPU time 6.27 seconds
Started Jul 13 04:49:38 PM PDT 24
Finished Jul 13 04:49:46 PM PDT 24
Peak memory 198632 kb
Host smart-176eb695-2566-4c10-b240-00a13ca1fe38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327987492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2327987492
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.1176787728
Short name T557
Test name
Test status
Simulation time 112405081 ps
CPU time 1.48 seconds
Started Jul 13 04:49:45 PM PDT 24
Finished Jul 13 04:49:48 PM PDT 24
Peak memory 197368 kb
Host smart-27de2217-255f-4b03-98ed-216bbcd4c9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176787728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.1176787728
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.855219564
Short name T677
Test name
Test status
Simulation time 177093829 ps
CPU time 0.89 seconds
Started Jul 13 04:49:42 PM PDT 24
Finished Jul 13 04:49:45 PM PDT 24
Peak memory 196888 kb
Host smart-baa9ff02-ef27-47fc-85fb-00bb2e1d7b83
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855219564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.855219564
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.443931216
Short name T413
Test name
Test status
Simulation time 4422800265 ps
CPU time 57.56 seconds
Started Jul 13 04:49:38 PM PDT 24
Finished Jul 13 04:50:37 PM PDT 24
Peak memory 198732 kb
Host smart-8d0c2a3e-9870-4154-a3a1-b0f0348afb7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443931216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.g
pio_stress_all.443931216
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.3918298532
Short name T65
Test name
Test status
Simulation time 62710579597 ps
CPU time 1018.22 seconds
Started Jul 13 04:49:40 PM PDT 24
Finished Jul 13 05:06:40 PM PDT 24
Peak memory 198772 kb
Host smart-ac78f69a-1a13-4394-ad3c-39aba221d7a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3918298532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.3918298532
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.1191820380
Short name T724
Test name
Test status
Simulation time 32270013 ps
CPU time 0.58 seconds
Started Jul 13 04:49:41 PM PDT 24
Finished Jul 13 04:49:44 PM PDT 24
Peak memory 194676 kb
Host smart-f8bf1898-aa2d-4655-a351-9a0625854810
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191820380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.1191820380
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.1774442861
Short name T149
Test name
Test status
Simulation time 187551201 ps
CPU time 0.82 seconds
Started Jul 13 04:49:38 PM PDT 24
Finished Jul 13 04:49:40 PM PDT 24
Peak memory 196148 kb
Host smart-78b505f0-3004-4244-b59a-d28303c3cb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774442861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.1774442861
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1080374458
Short name T391
Test name
Test status
Simulation time 1601208103 ps
CPU time 27.61 seconds
Started Jul 13 04:49:41 PM PDT 24
Finished Jul 13 04:50:11 PM PDT 24
Peak memory 198532 kb
Host smart-ea297615-f59c-40ae-a33a-ea46a862b07d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080374458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1080374458
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3072282447
Short name T259
Test name
Test status
Simulation time 75948091 ps
CPU time 0.96 seconds
Started Jul 13 04:49:42 PM PDT 24
Finished Jul 13 04:49:45 PM PDT 24
Peak memory 197824 kb
Host smart-fe8f8ec3-94d8-439b-8c1e-74ba7cb6c481
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072282447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3072282447
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.2147426463
Short name T248
Test name
Test status
Simulation time 96088050 ps
CPU time 0.72 seconds
Started Jul 13 04:49:44 PM PDT 24
Finished Jul 13 04:49:46 PM PDT 24
Peak memory 194928 kb
Host smart-ad7f1472-6119-475b-8515-09c2586b5eb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147426463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.2147426463
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3898198941
Short name T142
Test name
Test status
Simulation time 56388578 ps
CPU time 2.29 seconds
Started Jul 13 04:49:40 PM PDT 24
Finished Jul 13 04:49:45 PM PDT 24
Peak memory 198916 kb
Host smart-a9e1c889-599f-4bf5-84e0-e2b72393640e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898198941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3898198941
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1848059343
Short name T239
Test name
Test status
Simulation time 53734873 ps
CPU time 0.95 seconds
Started Jul 13 04:49:42 PM PDT 24
Finished Jul 13 04:49:45 PM PDT 24
Peak memory 196772 kb
Host smart-2d6b77cb-a6a1-4930-8b16-30b689ef63eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848059343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1848059343
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2493793074
Short name T408
Test name
Test status
Simulation time 25466372 ps
CPU time 0.98 seconds
Started Jul 13 04:49:40 PM PDT 24
Finished Jul 13 04:49:43 PM PDT 24
Peak memory 197180 kb
Host smart-d2c08c26-716b-4826-b99a-2e25e5e55134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493793074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2493793074
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1087531420
Short name T318
Test name
Test status
Simulation time 151022304 ps
CPU time 1.13 seconds
Started Jul 13 04:49:41 PM PDT 24
Finished Jul 13 04:49:45 PM PDT 24
Peak memory 197704 kb
Host smart-f2e036a8-45e4-420a-8454-07de755575b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087531420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1087531420
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2520108029
Short name T393
Test name
Test status
Simulation time 1036502699 ps
CPU time 4.4 seconds
Started Jul 13 04:49:42 PM PDT 24
Finished Jul 13 04:49:48 PM PDT 24
Peak memory 198644 kb
Host smart-50a9bb2a-16c3-4d37-824b-bdc6bd6735dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520108029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2520108029
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.37633039
Short name T379
Test name
Test status
Simulation time 38108515 ps
CPU time 1.1 seconds
Started Jul 13 04:49:43 PM PDT 24
Finished Jul 13 04:49:46 PM PDT 24
Peak memory 196152 kb
Host smart-201c6ef5-607b-4f88-9bea-a25c3f5db9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37633039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.37633039
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.844146914
Short name T573
Test name
Test status
Simulation time 36994010 ps
CPU time 1.13 seconds
Started Jul 13 04:49:40 PM PDT 24
Finished Jul 13 04:49:42 PM PDT 24
Peak memory 196808 kb
Host smart-98e43955-e589-4a4e-b078-730b48240017
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844146914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.844146914
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.1212214013
Short name T666
Test name
Test status
Simulation time 12844293899 ps
CPU time 106.56 seconds
Started Jul 13 04:49:41 PM PDT 24
Finished Jul 13 04:51:30 PM PDT 24
Peak memory 198776 kb
Host smart-f85034b4-3c66-4844-9ad0-193ed3120bb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212214013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.1212214013
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.751428285
Short name T410
Test name
Test status
Simulation time 12786983 ps
CPU time 0.59 seconds
Started Jul 13 04:49:45 PM PDT 24
Finished Jul 13 04:49:47 PM PDT 24
Peak memory 194656 kb
Host smart-5d2e51ca-5e4f-416f-a4ff-5a3d8e5c0e21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751428285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.751428285
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2700787352
Short name T367
Test name
Test status
Simulation time 21343419 ps
CPU time 0.61 seconds
Started Jul 13 04:49:40 PM PDT 24
Finished Jul 13 04:49:42 PM PDT 24
Peak memory 194552 kb
Host smart-07f9679c-b490-4c36-907f-63c520639e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700787352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2700787352
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.84920057
Short name T233
Test name
Test status
Simulation time 424439539 ps
CPU time 21.53 seconds
Started Jul 13 04:49:43 PM PDT 24
Finished Jul 13 04:50:07 PM PDT 24
Peak memory 197316 kb
Host smart-4167e14f-a6aa-4cef-913b-89d90a58a046
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84920057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stress
.84920057
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.318540508
Short name T632
Test name
Test status
Simulation time 58484215 ps
CPU time 0.95 seconds
Started Jul 13 04:49:44 PM PDT 24
Finished Jul 13 04:49:47 PM PDT 24
Peak memory 197056 kb
Host smart-fe2437a0-504d-4b82-9c25-cee8825fec67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318540508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.318540508
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3036400456
Short name T642
Test name
Test status
Simulation time 91431664 ps
CPU time 1.15 seconds
Started Jul 13 04:49:38 PM PDT 24
Finished Jul 13 04:49:41 PM PDT 24
Peak memory 197308 kb
Host smart-fc72d06b-dc54-4ee2-aceb-74b0f458a824
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036400456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3036400456
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2067697548
Short name T437
Test name
Test status
Simulation time 29402368 ps
CPU time 1.22 seconds
Started Jul 13 04:49:40 PM PDT 24
Finished Jul 13 04:49:43 PM PDT 24
Peak memory 197088 kb
Host smart-650a4932-543c-404b-a066-e67b585f4d18
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067697548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2067697548
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.3940177468
Short name T507
Test name
Test status
Simulation time 142741252 ps
CPU time 2.84 seconds
Started Jul 13 04:49:42 PM PDT 24
Finished Jul 13 04:49:47 PM PDT 24
Peak memory 197236 kb
Host smart-7e7a646a-2261-4c32-a8e1-983239390fe8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940177468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.3940177468
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.1636699369
Short name T716
Test name
Test status
Simulation time 44211327 ps
CPU time 0.97 seconds
Started Jul 13 04:49:41 PM PDT 24
Finished Jul 13 04:49:44 PM PDT 24
Peak memory 196428 kb
Host smart-1b45fe19-7622-4045-b7d5-d299521e6564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636699369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.1636699369
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3197671354
Short name T707
Test name
Test status
Simulation time 43621034 ps
CPU time 0.95 seconds
Started Jul 13 04:49:37 PM PDT 24
Finished Jul 13 04:49:39 PM PDT 24
Peak memory 197176 kb
Host smart-279041c5-ea0e-437b-9179-ddbf826d7504
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197671354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3197671354
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.1890052399
Short name T14
Test name
Test status
Simulation time 553686309 ps
CPU time 3.04 seconds
Started Jul 13 04:49:43 PM PDT 24
Finished Jul 13 04:49:48 PM PDT 24
Peak memory 198656 kb
Host smart-2a56f02b-0c34-463d-8e08-d70b116c26a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890052399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.1890052399
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3322047135
Short name T125
Test name
Test status
Simulation time 59823693 ps
CPU time 1.21 seconds
Started Jul 13 04:49:40 PM PDT 24
Finished Jul 13 04:49:42 PM PDT 24
Peak memory 196312 kb
Host smart-d7049c1e-89b7-4549-903f-9f5bcf4cb339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322047135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3322047135
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.766893797
Short name T591
Test name
Test status
Simulation time 269058796 ps
CPU time 1.26 seconds
Started Jul 13 04:49:46 PM PDT 24
Finished Jul 13 04:49:48 PM PDT 24
Peak memory 198588 kb
Host smart-5abf0ff5-ef91-4e3f-893a-4ed81302607d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766893797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.766893797
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3046648950
Short name T317
Test name
Test status
Simulation time 14654961761 ps
CPU time 157.57 seconds
Started Jul 13 04:49:50 PM PDT 24
Finished Jul 13 04:52:29 PM PDT 24
Peak memory 198840 kb
Host smart-72607bdc-d30f-4af4-8a1f-3f96da0d1e6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046648950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3046648950
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.4130758074
Short name T281
Test name
Test status
Simulation time 37930827 ps
CPU time 0.58 seconds
Started Jul 13 04:49:47 PM PDT 24
Finished Jul 13 04:49:49 PM PDT 24
Peak memory 195348 kb
Host smart-e4ed44ac-f318-4d78-b868-0090e9146280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130758074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.4130758074
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2572020934
Short name T321
Test name
Test status
Simulation time 25226479 ps
CPU time 0.7 seconds
Started Jul 13 04:49:47 PM PDT 24
Finished Jul 13 04:49:50 PM PDT 24
Peak memory 194676 kb
Host smart-b38ac24d-fb47-4756-b0a0-942cc55e9c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572020934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2572020934
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.4070469985
Short name T280
Test name
Test status
Simulation time 368244068 ps
CPU time 18.72 seconds
Started Jul 13 04:49:48 PM PDT 24
Finished Jul 13 04:50:08 PM PDT 24
Peak memory 196876 kb
Host smart-906b9097-b7c5-4663-8b7f-dcd1f707b6c9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070469985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.4070469985
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.284827608
Short name T348
Test name
Test status
Simulation time 109522467 ps
CPU time 0.94 seconds
Started Jul 13 04:49:47 PM PDT 24
Finished Jul 13 04:49:50 PM PDT 24
Peak memory 197712 kb
Host smart-5c92bac8-6595-4358-ab51-ef33d9186117
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284827608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.284827608
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.2706934802
Short name T175
Test name
Test status
Simulation time 456347534 ps
CPU time 1.13 seconds
Started Jul 13 04:49:46 PM PDT 24
Finished Jul 13 04:49:49 PM PDT 24
Peak memory 196524 kb
Host smart-5bfcae8f-8a8f-45af-8aa6-1dc6a7bbe964
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706934802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.2706934802
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2277898057
Short name T385
Test name
Test status
Simulation time 234588896 ps
CPU time 2.65 seconds
Started Jul 13 04:49:47 PM PDT 24
Finished Jul 13 04:49:52 PM PDT 24
Peak memory 198792 kb
Host smart-acda8b73-e625-4bf3-862f-e3a947e317df
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277898057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2277898057
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1216775918
Short name T637
Test name
Test status
Simulation time 143645917 ps
CPU time 2.87 seconds
Started Jul 13 04:49:46 PM PDT 24
Finished Jul 13 04:49:50 PM PDT 24
Peak memory 198720 kb
Host smart-a6ec68f0-f1ed-4df8-ae3d-2d63b8861de4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216775918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1216775918
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.3183287128
Short name T390
Test name
Test status
Simulation time 99802582 ps
CPU time 0.85 seconds
Started Jul 13 04:49:47 PM PDT 24
Finished Jul 13 04:49:50 PM PDT 24
Peak memory 197708 kb
Host smart-b3571fe0-8555-4b7d-861e-a12d2fdb6219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183287128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3183287128
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.3432555195
Short name T694
Test name
Test status
Simulation time 161995856 ps
CPU time 0.83 seconds
Started Jul 13 04:49:46 PM PDT 24
Finished Jul 13 04:49:49 PM PDT 24
Peak memory 196804 kb
Host smart-792319f0-eb4b-4bcd-9f31-a91d3946b278
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432555195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.3432555195
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1977685192
Short name T537
Test name
Test status
Simulation time 645835062 ps
CPU time 2.8 seconds
Started Jul 13 04:49:53 PM PDT 24
Finished Jul 13 04:49:57 PM PDT 24
Peak memory 198572 kb
Host smart-ef868cb0-ffbe-4a3a-a864-cada9e34deb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977685192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1977685192
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3100778203
Short name T296
Test name
Test status
Simulation time 148219497 ps
CPU time 1.21 seconds
Started Jul 13 04:49:49 PM PDT 24
Finished Jul 13 04:49:52 PM PDT 24
Peak memory 196480 kb
Host smart-3a5bccf5-7f8f-49c1-a201-b7ca56f5b9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100778203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3100778203
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.814110498
Short name T186
Test name
Test status
Simulation time 1065971937 ps
CPU time 1.29 seconds
Started Jul 13 04:49:46 PM PDT 24
Finished Jul 13 04:49:49 PM PDT 24
Peak memory 196516 kb
Host smart-8f6bec53-bc91-402a-aa7f-152703f74be5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814110498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.814110498
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1338003883
Short name T517
Test name
Test status
Simulation time 2882707835 ps
CPU time 66 seconds
Started Jul 13 04:49:49 PM PDT 24
Finished Jul 13 04:50:56 PM PDT 24
Peak memory 198728 kb
Host smart-8e197c64-744d-4e6b-a0ac-d868bcaecbd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338003883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1338003883
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3758627717
Short name T442
Test name
Test status
Simulation time 27233374 ps
CPU time 0.6 seconds
Started Jul 13 04:49:48 PM PDT 24
Finished Jul 13 04:49:50 PM PDT 24
Peak memory 195876 kb
Host smart-7e64e0ab-7a03-4cbf-86f3-5ce6aaee8aae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758627717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3758627717
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.266269477
Short name T342
Test name
Test status
Simulation time 40879413 ps
CPU time 0.87 seconds
Started Jul 13 04:49:48 PM PDT 24
Finished Jul 13 04:49:51 PM PDT 24
Peak memory 196768 kb
Host smart-de86d8b3-5b12-4089-8a22-eee38d5294f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266269477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.266269477
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.3174914797
Short name T438
Test name
Test status
Simulation time 2532777960 ps
CPU time 19.86 seconds
Started Jul 13 04:49:53 PM PDT 24
Finished Jul 13 04:50:13 PM PDT 24
Peak memory 198656 kb
Host smart-835c8b8f-b1be-4bc3-985b-4065930f7171
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174914797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.3174914797
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.4187973472
Short name T397
Test name
Test status
Simulation time 201733588 ps
CPU time 0.86 seconds
Started Jul 13 04:49:50 PM PDT 24
Finished Jul 13 04:49:52 PM PDT 24
Peak memory 196496 kb
Host smart-f4d61fc2-fcb1-4cbe-a56e-a9f52b9c477d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187973472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.4187973472
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2529762281
Short name T578
Test name
Test status
Simulation time 124030488 ps
CPU time 0.8 seconds
Started Jul 13 04:49:45 PM PDT 24
Finished Jul 13 04:49:47 PM PDT 24
Peak memory 196288 kb
Host smart-c0b8bf68-ff56-442f-93a4-3b95a4208b1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529762281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2529762281
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.823181701
Short name T350
Test name
Test status
Simulation time 175067393 ps
CPU time 3.67 seconds
Started Jul 13 04:49:47 PM PDT 24
Finished Jul 13 04:49:52 PM PDT 24
Peak memory 198684 kb
Host smart-3edfa254-0e4f-420c-8420-acda0f8e353a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823181701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.gpio_intr_with_filter_rand_intr_event.823181701
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.2818038438
Short name T470
Test name
Test status
Simulation time 415022835 ps
CPU time 2.52 seconds
Started Jul 13 04:49:48 PM PDT 24
Finished Jul 13 04:49:52 PM PDT 24
Peak memory 197552 kb
Host smart-8a211a04-4b77-4907-80af-dbe5a5579fef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818038438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.2818038438
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3443680960
Short name T168
Test name
Test status
Simulation time 18782629 ps
CPU time 0.7 seconds
Started Jul 13 04:49:52 PM PDT 24
Finished Jul 13 04:49:53 PM PDT 24
Peak memory 194844 kb
Host smart-129d7bb0-09f9-44b8-9103-a40aa2988dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443680960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3443680960
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.271993332
Short name T210
Test name
Test status
Simulation time 57682146 ps
CPU time 1.22 seconds
Started Jul 13 04:49:53 PM PDT 24
Finished Jul 13 04:49:54 PM PDT 24
Peak memory 197508 kb
Host smart-29732bcf-7825-4af6-8e03-d20183fec7e9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271993332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup
_pulldown.271993332
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.762888686
Short name T563
Test name
Test status
Simulation time 846430640 ps
CPU time 2.64 seconds
Started Jul 13 04:49:47 PM PDT 24
Finished Jul 13 04:49:51 PM PDT 24
Peak memory 198664 kb
Host smart-1a4d4fac-be79-4a11-9005-e20f06779233
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762888686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ran
dom_long_reg_writes_reg_reads.762888686
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1156697177
Short name T618
Test name
Test status
Simulation time 53034640 ps
CPU time 1.1 seconds
Started Jul 13 04:49:53 PM PDT 24
Finished Jul 13 04:49:55 PM PDT 24
Peak memory 196948 kb
Host smart-b6f7c636-6070-4ca7-9ad3-1f9ce9d24126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156697177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1156697177
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.4267046472
Short name T276
Test name
Test status
Simulation time 34039117 ps
CPU time 0.89 seconds
Started Jul 13 04:49:53 PM PDT 24
Finished Jul 13 04:49:55 PM PDT 24
Peak memory 196676 kb
Host smart-f6fc428f-6979-4ca2-8588-5ca8a01e9b50
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267046472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.4267046472
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.2488532555
Short name T464
Test name
Test status
Simulation time 35252029598 ps
CPU time 143.74 seconds
Started Jul 13 04:49:47 PM PDT 24
Finished Jul 13 04:52:13 PM PDT 24
Peak memory 198760 kb
Host smart-68668550-6e65-4b43-97f9-6662bfc62536
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488532555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.2488532555
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.1003586177
Short name T340
Test name
Test status
Simulation time 74979185680 ps
CPU time 458.46 seconds
Started Jul 13 04:49:47 PM PDT 24
Finished Jul 13 04:57:27 PM PDT 24
Peak memory 198900 kb
Host smart-29171841-39a6-45e0-bae6-fd453ebbacb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1003586177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.1003586177
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.261275304
Short name T682
Test name
Test status
Simulation time 24526899 ps
CPU time 0.6 seconds
Started Jul 13 04:49:50 PM PDT 24
Finished Jul 13 04:49:52 PM PDT 24
Peak memory 194808 kb
Host smart-5ef7c4b5-6332-4e8e-b0b4-1dfef980b05c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261275304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.261275304
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.12774345
Short name T543
Test name
Test status
Simulation time 24860671 ps
CPU time 0.65 seconds
Started Jul 13 04:49:46 PM PDT 24
Finished Jul 13 04:49:48 PM PDT 24
Peak memory 194768 kb
Host smart-b40a7ea9-3d4e-42de-af48-184577623978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12774345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.12774345
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1222025114
Short name T545
Test name
Test status
Simulation time 1037539527 ps
CPU time 6.93 seconds
Started Jul 13 04:49:50 PM PDT 24
Finished Jul 13 04:49:58 PM PDT 24
Peak memory 196708 kb
Host smart-9f7828d2-310c-40e8-ab95-c91c8261e749
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222025114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1222025114
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.112902186
Short name T484
Test name
Test status
Simulation time 88498317 ps
CPU time 0.73 seconds
Started Jul 13 04:49:53 PM PDT 24
Finished Jul 13 04:49:54 PM PDT 24
Peak memory 195148 kb
Host smart-21b5e01d-4399-427c-bea3-8b79cc8e8b5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112902186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.112902186
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.459208414
Short name T616
Test name
Test status
Simulation time 68725551 ps
CPU time 0.91 seconds
Started Jul 13 04:49:46 PM PDT 24
Finished Jul 13 04:49:48 PM PDT 24
Peak memory 196340 kb
Host smart-cc9efb11-3092-4f1f-a8f7-e780aeca4ec1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459208414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.459208414
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.2368529612
Short name T500
Test name
Test status
Simulation time 108186948 ps
CPU time 2.44 seconds
Started Jul 13 04:49:53 PM PDT 24
Finished Jul 13 04:49:56 PM PDT 24
Peak memory 198612 kb
Host smart-0f39e7a9-b673-4b5e-9306-d380155a26e8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368529612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.2368529612
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.1897566065
Short name T601
Test name
Test status
Simulation time 208178192 ps
CPU time 3.18 seconds
Started Jul 13 04:49:47 PM PDT 24
Finished Jul 13 04:49:52 PM PDT 24
Peak memory 197748 kb
Host smart-02d2ab8b-e1ed-42c8-b75b-85f72fbb808b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897566065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.1897566065
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2311710375
Short name T506
Test name
Test status
Simulation time 98522632 ps
CPU time 1.11 seconds
Started Jul 13 04:49:50 PM PDT 24
Finished Jul 13 04:49:52 PM PDT 24
Peak memory 197820 kb
Host smart-d1bf8413-baa9-4e38-a80e-4ff673556eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311710375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2311710375
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1158628535
Short name T197
Test name
Test status
Simulation time 22413275 ps
CPU time 0.73 seconds
Started Jul 13 04:49:48 PM PDT 24
Finished Jul 13 04:49:50 PM PDT 24
Peak memory 196064 kb
Host smart-9c284f3e-6ea8-419a-9317-d2b3cb87b320
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158628535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1158628535
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.1469035906
Short name T139
Test name
Test status
Simulation time 100707271 ps
CPU time 4.49 seconds
Started Jul 13 04:49:48 PM PDT 24
Finished Jul 13 04:49:54 PM PDT 24
Peak memory 198648 kb
Host smart-ad2f3abc-ccff-4e5b-be32-4b7b2b535d51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469035906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.1469035906
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.195808652
Short name T613
Test name
Test status
Simulation time 89191106 ps
CPU time 1.38 seconds
Started Jul 13 04:49:47 PM PDT 24
Finished Jul 13 04:49:50 PM PDT 24
Peak memory 197544 kb
Host smart-28e6d25a-96e2-4bbd-9a7d-7725e96c8dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195808652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.195808652
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3122258484
Short name T440
Test name
Test status
Simulation time 276714503 ps
CPU time 1.45 seconds
Started Jul 13 04:49:53 PM PDT 24
Finished Jul 13 04:49:56 PM PDT 24
Peak memory 197400 kb
Host smart-ce842cc6-90c4-45f7-a5b7-448d833ca718
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122258484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3122258484
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.232006703
Short name T447
Test name
Test status
Simulation time 30313912347 ps
CPU time 196.86 seconds
Started Jul 13 04:49:47 PM PDT 24
Finished Jul 13 04:53:06 PM PDT 24
Peak memory 198716 kb
Host smart-af3c5fd3-b168-44b7-837d-1cb84985f036
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232006703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.232006703
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.3793016090
Short name T63
Test name
Test status
Simulation time 108142977016 ps
CPU time 1457.06 seconds
Started Jul 13 04:49:53 PM PDT 24
Finished Jul 13 05:14:10 PM PDT 24
Peak memory 198792 kb
Host smart-a5a20eab-60d2-470c-a150-d8d363bbf045
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3793016090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.3793016090
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.3357970237
Short name T450
Test name
Test status
Simulation time 15459525 ps
CPU time 0.59 seconds
Started Jul 13 04:49:54 PM PDT 24
Finished Jul 13 04:49:55 PM PDT 24
Peak memory 195472 kb
Host smart-5978c2aa-d77c-4fc2-9831-2e7965c64637
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357970237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.3357970237
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.3542766782
Short name T242
Test name
Test status
Simulation time 98771826 ps
CPU time 0.95 seconds
Started Jul 13 04:49:48 PM PDT 24
Finished Jul 13 04:49:50 PM PDT 24
Peak memory 196688 kb
Host smart-4e5af786-cb24-46e2-9389-07c41482c412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542766782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.3542766782
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.379474660
Short name T570
Test name
Test status
Simulation time 1193129988 ps
CPU time 8.7 seconds
Started Jul 13 04:49:55 PM PDT 24
Finished Jul 13 04:50:05 PM PDT 24
Peak memory 198620 kb
Host smart-71685de0-91bc-4a3c-9f07-84122cc2c47e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379474660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stres
s.379474660
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.492153976
Short name T232
Test name
Test status
Simulation time 67840153 ps
CPU time 0.86 seconds
Started Jul 13 04:49:59 PM PDT 24
Finished Jul 13 04:50:01 PM PDT 24
Peak memory 196624 kb
Host smart-8afe52a4-235a-4a7b-bb45-19a1bdd1cc34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492153976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.492153976
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.4240002657
Short name T165
Test name
Test status
Simulation time 190677878 ps
CPU time 0.85 seconds
Started Jul 13 04:49:53 PM PDT 24
Finished Jul 13 04:49:55 PM PDT 24
Peak memory 198056 kb
Host smart-1aa6669d-93ee-4828-991a-c33850c058f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240002657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.4240002657
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1295321700
Short name T203
Test name
Test status
Simulation time 46185324 ps
CPU time 1.83 seconds
Started Jul 13 04:49:50 PM PDT 24
Finished Jul 13 04:49:53 PM PDT 24
Peak memory 196984 kb
Host smart-1cc90cd8-5d03-4a7b-a6ef-d7392a986a13
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295321700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1295321700
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.2797717202
Short name T532
Test name
Test status
Simulation time 103353126 ps
CPU time 3.21 seconds
Started Jul 13 04:49:47 PM PDT 24
Finished Jul 13 04:49:52 PM PDT 24
Peak memory 198692 kb
Host smart-059151f1-d5e4-466e-abd3-e707dd87b32b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797717202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.2797717202
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.322411901
Short name T592
Test name
Test status
Simulation time 58571884 ps
CPU time 1.22 seconds
Started Jul 13 04:49:52 PM PDT 24
Finished Jul 13 04:49:54 PM PDT 24
Peak memory 196696 kb
Host smart-3d95f84a-4770-4b6e-86c7-1d787c627333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322411901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.322411901
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.4285317484
Short name T131
Test name
Test status
Simulation time 246259154 ps
CPU time 1.07 seconds
Started Jul 13 04:49:53 PM PDT 24
Finished Jul 13 04:49:55 PM PDT 24
Peak memory 196632 kb
Host smart-a0c2a1f8-907a-49ec-bbfa-9df033d721ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285317484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.4285317484
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1708003421
Short name T455
Test name
Test status
Simulation time 2820861718 ps
CPU time 3.69 seconds
Started Jul 13 04:49:56 PM PDT 24
Finished Jul 13 04:50:02 PM PDT 24
Peak memory 198692 kb
Host smart-7376736d-9790-42f1-b20d-a49ee8d488fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708003421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1708003421
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.2396645429
Short name T663
Test name
Test status
Simulation time 118887744 ps
CPU time 0.85 seconds
Started Jul 13 04:49:54 PM PDT 24
Finished Jul 13 04:49:56 PM PDT 24
Peak memory 195848 kb
Host smart-39f2226e-51b8-4663-93a8-1bc284de4116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396645429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.2396645429
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.3989865193
Short name T555
Test name
Test status
Simulation time 305798652 ps
CPU time 0.91 seconds
Started Jul 13 04:49:54 PM PDT 24
Finished Jul 13 04:49:56 PM PDT 24
Peak memory 196860 kb
Host smart-b1a51a92-c96e-43ee-a3ed-a85152db3d6d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989865193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.3989865193
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.2202522135
Short name T25
Test name
Test status
Simulation time 7189212588 ps
CPU time 111.96 seconds
Started Jul 13 04:49:56 PM PDT 24
Finished Jul 13 04:51:49 PM PDT 24
Peak memory 198684 kb
Host smart-456bad98-8bba-4af7-829c-34534e48ce68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202522135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2202522135
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.455625895
Short name T483
Test name
Test status
Simulation time 55835844153 ps
CPU time 928.48 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 05:05:34 PM PDT 24
Peak memory 198904 kb
Host smart-b108bb38-0132-41c2-a056-7a0b3b80f4a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=455625895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.455625895
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.662874261
Short name T683
Test name
Test status
Simulation time 11136311 ps
CPU time 0.58 seconds
Started Jul 13 04:48:42 PM PDT 24
Finished Jul 13 04:48:45 PM PDT 24
Peak memory 195248 kb
Host smart-32a19387-c99f-4035-b7c4-d5347dd165cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662874261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.662874261
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.2274963527
Short name T231
Test name
Test status
Simulation time 38183354 ps
CPU time 0.86 seconds
Started Jul 13 04:48:42 PM PDT 24
Finished Jul 13 04:48:45 PM PDT 24
Peak memory 197120 kb
Host smart-bbac7e09-940c-48e1-b5ac-c58c0bd856d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274963527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.2274963527
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1062030773
Short name T376
Test name
Test status
Simulation time 441328166 ps
CPU time 14.55 seconds
Started Jul 13 04:48:29 PM PDT 24
Finished Jul 13 04:48:45 PM PDT 24
Peak memory 198668 kb
Host smart-525e6d26-8785-4675-9cdc-7bd6d7f40c87
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062030773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1062030773
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2608396856
Short name T417
Test name
Test status
Simulation time 54131944 ps
CPU time 0.95 seconds
Started Jul 13 04:48:31 PM PDT 24
Finished Jul 13 04:48:35 PM PDT 24
Peak memory 197672 kb
Host smart-1ecfea41-93b4-4d23-a4d7-9ac77307f4d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608396856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2608396856
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3125966595
Short name T214
Test name
Test status
Simulation time 54513291 ps
CPU time 0.97 seconds
Started Jul 13 04:48:29 PM PDT 24
Finished Jul 13 04:48:32 PM PDT 24
Peak memory 197380 kb
Host smart-cc960725-c2c8-487a-8d27-926b90979c79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125966595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3125966595
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.646054003
Short name T150
Test name
Test status
Simulation time 94340666 ps
CPU time 1.07 seconds
Started Jul 13 04:48:33 PM PDT 24
Finished Jul 13 04:48:36 PM PDT 24
Peak memory 197024 kb
Host smart-67621328-7b43-4379-846e-11338ec932a7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646054003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.646054003
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3049058418
Short name T400
Test name
Test status
Simulation time 229318833 ps
CPU time 0.96 seconds
Started Jul 13 04:48:31 PM PDT 24
Finished Jul 13 04:48:34 PM PDT 24
Peak memory 196932 kb
Host smart-c1b58b86-6dea-4ed2-92a6-f768eaeb6829
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049058418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3049058418
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.241153793
Short name T182
Test name
Test status
Simulation time 212325177 ps
CPU time 1.21 seconds
Started Jul 13 04:48:30 PM PDT 24
Finished Jul 13 04:48:34 PM PDT 24
Peak memory 197432 kb
Host smart-f9a41119-f3a0-47de-99d0-d2c9e0747f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241153793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.241153793
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.652092678
Short name T357
Test name
Test status
Simulation time 83176010 ps
CPU time 0.95 seconds
Started Jul 13 04:48:30 PM PDT 24
Finished Jul 13 04:48:34 PM PDT 24
Peak memory 196664 kb
Host smart-996ef0c6-90ee-425c-ba7a-54925130bfbd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652092678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.652092678
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1736360051
Short name T662
Test name
Test status
Simulation time 526177379 ps
CPU time 3.82 seconds
Started Jul 13 04:48:30 PM PDT 24
Finished Jul 13 04:48:35 PM PDT 24
Peak memory 198604 kb
Host smart-f22ccf63-a1ce-4b12-a834-004081f800f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736360051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1736360051
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2704314134
Short name T49
Test name
Test status
Simulation time 64535957 ps
CPU time 0.86 seconds
Started Jul 13 04:48:31 PM PDT 24
Finished Jul 13 04:48:34 PM PDT 24
Peak memory 214252 kb
Host smart-24651ca5-845a-419f-b362-0228f36bb516
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704314134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2704314134
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.803907638
Short name T57
Test name
Test status
Simulation time 58444150 ps
CPU time 1.02 seconds
Started Jul 13 04:48:30 PM PDT 24
Finished Jul 13 04:48:34 PM PDT 24
Peak memory 196132 kb
Host smart-d3ad5414-9f12-4e40-a0d4-b38087285f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803907638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.803907638
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1099427371
Short name T216
Test name
Test status
Simulation time 418317170 ps
CPU time 1.28 seconds
Started Jul 13 04:48:33 PM PDT 24
Finished Jul 13 04:48:37 PM PDT 24
Peak memory 196360 kb
Host smart-38fca089-96bd-48bd-bcfd-224ff12e7974
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099427371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1099427371
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3756893938
Short name T7
Test name
Test status
Simulation time 51119325027 ps
CPU time 168.69 seconds
Started Jul 13 04:48:29 PM PDT 24
Finished Jul 13 04:51:20 PM PDT 24
Peak memory 198776 kb
Host smart-80a34579-a01e-4ae9-802a-3100ad8a8f95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756893938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3756893938
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.3332562351
Short name T62
Test name
Test status
Simulation time 70773316474 ps
CPU time 1609.31 seconds
Started Jul 13 04:48:31 PM PDT 24
Finished Jul 13 05:15:23 PM PDT 24
Peak memory 198924 kb
Host smart-23176cff-caf2-413e-b68f-0accdf1d1efb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3332562351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.3332562351
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.243389752
Short name T472
Test name
Test status
Simulation time 20685343 ps
CPU time 0.54 seconds
Started Jul 13 04:49:55 PM PDT 24
Finished Jul 13 04:49:58 PM PDT 24
Peak memory 194568 kb
Host smart-9784ba85-7576-4a71-813f-007d7ac6cb39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243389752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.243389752
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3501302225
Short name T608
Test name
Test status
Simulation time 26600621 ps
CPU time 0.78 seconds
Started Jul 13 04:50:00 PM PDT 24
Finished Jul 13 04:50:01 PM PDT 24
Peak memory 195804 kb
Host smart-b8b27c2f-0313-406f-aeba-a3c7469ebaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501302225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3501302225
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.186282918
Short name T103
Test name
Test status
Simulation time 711170431 ps
CPU time 18.05 seconds
Started Jul 13 04:49:55 PM PDT 24
Finished Jul 13 04:50:15 PM PDT 24
Peak memory 197460 kb
Host smart-865ec409-70a6-4534-b812-f22f103a7aa8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186282918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.186282918
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.85820870
Short name T337
Test name
Test status
Simulation time 128013692 ps
CPU time 0.81 seconds
Started Jul 13 04:49:56 PM PDT 24
Finished Jul 13 04:49:59 PM PDT 24
Peak memory 197120 kb
Host smart-e235eb4c-5adc-4aca-af0d-2eef693e3648
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85820870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.85820870
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1981160441
Short name T261
Test name
Test status
Simulation time 92659784 ps
CPU time 1.5 seconds
Started Jul 13 04:49:54 PM PDT 24
Finished Jul 13 04:49:56 PM PDT 24
Peak memory 197268 kb
Host smart-8cf0dbad-30ee-40fc-986a-1bc3c4c621c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981160441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1981160441
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.2315246922
Short name T428
Test name
Test status
Simulation time 406412557 ps
CPU time 3.72 seconds
Started Jul 13 04:49:56 PM PDT 24
Finished Jul 13 04:50:02 PM PDT 24
Peak memory 198744 kb
Host smart-3cc38356-3da8-4658-b2dc-882e10e5ce01
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315246922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.2315246922
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2839843106
Short name T482
Test name
Test status
Simulation time 159167070 ps
CPU time 3.49 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:09 PM PDT 24
Peak memory 197368 kb
Host smart-3382b823-7d14-4b6d-b060-b91958b33dad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839843106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2839843106
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.2944192273
Short name T70
Test name
Test status
Simulation time 62243228 ps
CPU time 0.81 seconds
Started Jul 13 04:49:55 PM PDT 24
Finished Jul 13 04:49:58 PM PDT 24
Peak memory 196148 kb
Host smart-bc8f0e96-4185-4293-947b-42e777d98d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944192273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2944192273
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.154304188
Short name T368
Test name
Test status
Simulation time 120986927 ps
CPU time 1.25 seconds
Started Jul 13 04:49:55 PM PDT 24
Finished Jul 13 04:49:58 PM PDT 24
Peak memory 197556 kb
Host smart-cda84040-6b95-4c33-8cc4-7eaac867c333
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154304188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup
_pulldown.154304188
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.1853207331
Short name T433
Test name
Test status
Simulation time 2147507783 ps
CPU time 6.48 seconds
Started Jul 13 04:50:00 PM PDT 24
Finished Jul 13 04:50:07 PM PDT 24
Peak memory 198520 kb
Host smart-9cc02b89-a52b-4cab-bcaa-fe66c63b8439
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853207331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.1853207331
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.1600714579
Short name T462
Test name
Test status
Simulation time 55630628 ps
CPU time 0.97 seconds
Started Jul 13 04:49:59 PM PDT 24
Finished Jul 13 04:50:01 PM PDT 24
Peak memory 196852 kb
Host smart-8be35f68-1e28-4832-9b0e-f65acf55bed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600714579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.1600714579
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.485118530
Short name T615
Test name
Test status
Simulation time 191819726 ps
CPU time 1.06 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:07 PM PDT 24
Peak memory 196412 kb
Host smart-d533942b-953e-47a4-a269-21307f3eb039
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485118530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.485118530
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.717570349
Short name T21
Test name
Test status
Simulation time 39392385708 ps
CPU time 121.28 seconds
Started Jul 13 04:49:55 PM PDT 24
Finished Jul 13 04:51:58 PM PDT 24
Peak memory 198804 kb
Host smart-f88e86b9-51e1-41c4-bbb5-a35402b49cc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717570349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.717570349
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.875128541
Short name T102
Test name
Test status
Simulation time 874451164160 ps
CPU time 1700.73 seconds
Started Jul 13 04:49:54 PM PDT 24
Finished Jul 13 05:18:16 PM PDT 24
Peak memory 207048 kb
Host smart-9099816d-2be1-4627-bfe5-792a23abf936
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=875128541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.875128541
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3051435444
Short name T297
Test name
Test status
Simulation time 44250129 ps
CPU time 0.57 seconds
Started Jul 13 04:49:59 PM PDT 24
Finished Jul 13 04:50:00 PM PDT 24
Peak memory 194648 kb
Host smart-b3dc70ee-57bb-4005-843f-4b0bfe0b7d4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051435444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3051435444
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3994313449
Short name T107
Test name
Test status
Simulation time 107200525 ps
CPU time 0.88 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:07 PM PDT 24
Peak memory 197732 kb
Host smart-731c2998-37da-444c-a518-500aac8da34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994313449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3994313449
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2731701743
Short name T396
Test name
Test status
Simulation time 5811932258 ps
CPU time 20.74 seconds
Started Jul 13 04:49:55 PM PDT 24
Finished Jul 13 04:50:17 PM PDT 24
Peak memory 197144 kb
Host smart-5128ed3d-a207-477c-91c8-1c0c0e4925db
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731701743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2731701743
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1978983816
Short name T559
Test name
Test status
Simulation time 62555105 ps
CPU time 0.71 seconds
Started Jul 13 04:49:55 PM PDT 24
Finished Jul 13 04:49:58 PM PDT 24
Peak memory 195196 kb
Host smart-1c3c8d15-d807-49d9-98c4-bed933a735c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978983816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1978983816
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.438440493
Short name T402
Test name
Test status
Simulation time 301829575 ps
CPU time 0.85 seconds
Started Jul 13 04:49:55 PM PDT 24
Finished Jul 13 04:49:58 PM PDT 24
Peak memory 196004 kb
Host smart-3b9cbf78-3b4e-4e9f-9fbf-ff6ae66bac99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438440493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.438440493
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3112627240
Short name T369
Test name
Test status
Simulation time 189558139 ps
CPU time 1.38 seconds
Started Jul 13 04:49:56 PM PDT 24
Finished Jul 13 04:49:59 PM PDT 24
Peak memory 197136 kb
Host smart-ef2b1d7f-b0ff-486b-8747-985f30e9698b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112627240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3112627240
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3513803702
Short name T715
Test name
Test status
Simulation time 75467960 ps
CPU time 1.08 seconds
Started Jul 13 04:49:55 PM PDT 24
Finished Jul 13 04:49:58 PM PDT 24
Peak memory 196224 kb
Host smart-faecc028-2608-4a5c-bff1-c3f54f4396be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513803702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3513803702
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.667603807
Short name T360
Test name
Test status
Simulation time 171052059 ps
CPU time 0.79 seconds
Started Jul 13 04:49:54 PM PDT 24
Finished Jul 13 04:49:55 PM PDT 24
Peak memory 196524 kb
Host smart-2a3d0c7d-f1a2-453f-8a2a-b89d2ef4c097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667603807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.667603807
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2194626891
Short name T364
Test name
Test status
Simulation time 25115752 ps
CPU time 0.71 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:06 PM PDT 24
Peak memory 196028 kb
Host smart-ea92ce0b-5da5-40d0-bd81-00e263472b27
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194626891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2194626891
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1143100443
Short name T671
Test name
Test status
Simulation time 325289096 ps
CPU time 3.41 seconds
Started Jul 13 04:49:55 PM PDT 24
Finished Jul 13 04:50:00 PM PDT 24
Peak memory 198616 kb
Host smart-78541c4a-c6f7-4b0a-a731-c4bdb30b3d48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143100443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1143100443
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1045918299
Short name T53
Test name
Test status
Simulation time 217596710 ps
CPU time 1.19 seconds
Started Jul 13 04:49:59 PM PDT 24
Finished Jul 13 04:50:01 PM PDT 24
Peak memory 197396 kb
Host smart-ed363d09-1008-4dc1-9a26-0e8b4e1057c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045918299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1045918299
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.4015000312
Short name T148
Test name
Test status
Simulation time 349955393 ps
CPU time 1.36 seconds
Started Jul 13 04:50:00 PM PDT 24
Finished Jul 13 04:50:02 PM PDT 24
Peak memory 197400 kb
Host smart-e426ac89-94ca-43a1-bdc8-3b449df719bc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015000312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.4015000312
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2350559393
Short name T383
Test name
Test status
Simulation time 45794201684 ps
CPU time 154.34 seconds
Started Jul 13 04:49:57 PM PDT 24
Finished Jul 13 04:52:33 PM PDT 24
Peak memory 198784 kb
Host smart-c251a1fe-702f-4192-b67d-e226fea75e94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350559393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2350559393
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3435481028
Short name T322
Test name
Test status
Simulation time 30268655 ps
CPU time 0.57 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:06 PM PDT 24
Peak memory 194468 kb
Host smart-eefa0fd6-4aee-4dfb-ac64-5b4407700b7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435481028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3435481028
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2781505816
Short name T208
Test name
Test status
Simulation time 18569555 ps
CPU time 0.65 seconds
Started Jul 13 04:49:56 PM PDT 24
Finished Jul 13 04:49:59 PM PDT 24
Peak memory 194640 kb
Host smart-7c4ef551-0e6f-4ca7-942e-a16526efd165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781505816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2781505816
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2747680751
Short name T355
Test name
Test status
Simulation time 390353263 ps
CPU time 19.42 seconds
Started Jul 13 04:50:00 PM PDT 24
Finished Jul 13 04:50:20 PM PDT 24
Peak memory 197384 kb
Host smart-4d69ba90-65d0-4ca8-adf2-cbe5008f4029
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747680751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2747680751
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3394602694
Short name T535
Test name
Test status
Simulation time 74248450 ps
CPU time 0.93 seconds
Started Jul 13 04:49:59 PM PDT 24
Finished Jul 13 04:50:01 PM PDT 24
Peak memory 197740 kb
Host smart-589360d8-a1cc-461d-9280-064636507e49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394602694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3394602694
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.3225947053
Short name T163
Test name
Test status
Simulation time 66145146 ps
CPU time 1.17 seconds
Started Jul 13 04:49:57 PM PDT 24
Finished Jul 13 04:49:59 PM PDT 24
Peak memory 196640 kb
Host smart-8cbd4f06-f97c-4030-a1d8-2164b2616fbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225947053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.3225947053
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3410623882
Short name T166
Test name
Test status
Simulation time 67620356 ps
CPU time 2.51 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:07 PM PDT 24
Peak memory 198692 kb
Host smart-726b6a09-8728-4602-810d-a2a25e9d335a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410623882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3410623882
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.1094969982
Short name T251
Test name
Test status
Simulation time 23502242 ps
CPU time 0.95 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:07 PM PDT 24
Peak memory 196368 kb
Host smart-e3109f9b-5cfa-4be8-b3d0-2d7a57bed46f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094969982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.1094969982
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.1856588860
Short name T22
Test name
Test status
Simulation time 19852627 ps
CPU time 0.82 seconds
Started Jul 13 04:49:55 PM PDT 24
Finished Jul 13 04:49:58 PM PDT 24
Peak memory 196104 kb
Host smart-25345c0a-a1e1-4766-b352-2729bd8add41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856588860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1856588860
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3102374911
Short name T196
Test name
Test status
Simulation time 27417580 ps
CPU time 1.02 seconds
Started Jul 13 04:49:55 PM PDT 24
Finished Jul 13 04:49:57 PM PDT 24
Peak memory 196384 kb
Host smart-e498414c-896f-4229-903f-445a0a071628
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102374911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3102374911
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2173277182
Short name T249
Test name
Test status
Simulation time 113146334 ps
CPU time 2.62 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:08 PM PDT 24
Peak memory 198552 kb
Host smart-d20e8ed1-9e27-49b8-81f7-9d33b027074c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173277182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2173277182
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.1922367460
Short name T425
Test name
Test status
Simulation time 592371906 ps
CPU time 1.12 seconds
Started Jul 13 04:49:56 PM PDT 24
Finished Jul 13 04:49:59 PM PDT 24
Peak memory 196224 kb
Host smart-45a0fc8d-d9dd-4263-9769-9f8d838ebf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922367460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.1922367460
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.7016324
Short name T176
Test name
Test status
Simulation time 144160279 ps
CPU time 1.21 seconds
Started Jul 13 04:49:55 PM PDT 24
Finished Jul 13 04:49:58 PM PDT 24
Peak memory 198552 kb
Host smart-35b4805c-47f7-41ab-b433-001ff6e9af6e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7016324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.7016324
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.678891881
Short name T534
Test name
Test status
Simulation time 11012552241 ps
CPU time 132.18 seconds
Started Jul 13 04:49:56 PM PDT 24
Finished Jul 13 04:52:10 PM PDT 24
Peak memory 198788 kb
Host smart-09bf6227-3ef1-40f3-995d-32d134012408
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678891881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.g
pio_stress_all.678891881
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1240661978
Short name T530
Test name
Test status
Simulation time 17811649 ps
CPU time 0.57 seconds
Started Jul 13 04:50:04 PM PDT 24
Finished Jul 13 04:50:07 PM PDT 24
Peak memory 194652 kb
Host smart-efce1b06-76e0-4714-bdea-62e8c272a209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240661978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1240661978
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1707578151
Short name T711
Test name
Test status
Simulation time 25266213 ps
CPU time 0.7 seconds
Started Jul 13 04:49:55 PM PDT 24
Finished Jul 13 04:49:58 PM PDT 24
Peak memory 194784 kb
Host smart-716157f0-5eab-4bc1-856d-a618931e7ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707578151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1707578151
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2755188211
Short name T313
Test name
Test status
Simulation time 322279324 ps
CPU time 9.32 seconds
Started Jul 13 04:50:02 PM PDT 24
Finished Jul 13 04:50:13 PM PDT 24
Peak memory 197500 kb
Host smart-04a36de3-5f6f-4b8a-97e1-ec3dd1677729
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755188211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2755188211
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3881506003
Short name T504
Test name
Test status
Simulation time 28546192 ps
CPU time 0.69 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:06 PM PDT 24
Peak memory 195136 kb
Host smart-7c3ff160-d194-4630-bdb3-06cb7e4eeb41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881506003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3881506003
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.4147813146
Short name T213
Test name
Test status
Simulation time 102937330 ps
CPU time 0.74 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:06 PM PDT 24
Peak memory 196204 kb
Host smart-41b25bf2-7ffb-4d81-b69a-28841b942815
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147813146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.4147813146
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3532962145
Short name T619
Test name
Test status
Simulation time 54633072 ps
CPU time 2.34 seconds
Started Jul 13 04:50:01 PM PDT 24
Finished Jul 13 04:50:04 PM PDT 24
Peak memory 198720 kb
Host smart-ad1e7060-bf39-47cb-8a20-6e6710ec5f9d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532962145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3532962145
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.1967314892
Short name T629
Test name
Test status
Simulation time 527380300 ps
CPU time 1.57 seconds
Started Jul 13 04:50:02 PM PDT 24
Finished Jul 13 04:50:04 PM PDT 24
Peak memory 196740 kb
Host smart-0c21032e-8095-436d-900b-5e4446b1a7a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967314892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.1967314892
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1757381576
Short name T639
Test name
Test status
Simulation time 119992314 ps
CPU time 1.23 seconds
Started Jul 13 04:49:57 PM PDT 24
Finished Jul 13 04:50:00 PM PDT 24
Peak memory 196416 kb
Host smart-c1568b39-80e1-4e7c-a1ef-9ac27529b2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757381576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1757381576
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3283388660
Short name T382
Test name
Test status
Simulation time 290233625 ps
CPU time 1.17 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:06 PM PDT 24
Peak memory 196756 kb
Host smart-af93b8ee-6d48-4a1d-92cf-bbba9747157b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283388660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3283388660
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2934086324
Short name T633
Test name
Test status
Simulation time 1417048496 ps
CPU time 4.08 seconds
Started Jul 13 04:50:04 PM PDT 24
Finished Jul 13 04:50:11 PM PDT 24
Peak memory 198420 kb
Host smart-bac66dc5-f4d6-481a-bd51-741538725680
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934086324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2934086324
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2286580781
Short name T541
Test name
Test status
Simulation time 105406868 ps
CPU time 0.78 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:06 PM PDT 24
Peak memory 195824 kb
Host smart-b7f79ba3-f76c-42f0-97b1-03b49fd55dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286580781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2286580781
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.2720303014
Short name T515
Test name
Test status
Simulation time 362530308 ps
CPU time 1.38 seconds
Started Jul 13 04:49:59 PM PDT 24
Finished Jul 13 04:50:01 PM PDT 24
Peak memory 196268 kb
Host smart-8b7b5359-4355-413b-96d6-ab55921d342c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720303014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.2720303014
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.965871149
Short name T566
Test name
Test status
Simulation time 55285874874 ps
CPU time 163.73 seconds
Started Jul 13 04:50:04 PM PDT 24
Finished Jul 13 04:52:51 PM PDT 24
Peak memory 192548 kb
Host smart-a1407424-2584-4b1b-ad92-918574f8c224
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965871149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g
pio_stress_all.965871149
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.1722963515
Short name T71
Test name
Test status
Simulation time 34498203518 ps
CPU time 759.98 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 05:02:45 PM PDT 24
Peak memory 198892 kb
Host smart-e15eeaa7-0bb9-44a5-9ee9-20f849cbfdf6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1722963515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.1722963515
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1286105806
Short name T723
Test name
Test status
Simulation time 33106941 ps
CPU time 0.58 seconds
Started Jul 13 04:50:05 PM PDT 24
Finished Jul 13 04:50:09 PM PDT 24
Peak memory 194540 kb
Host smart-23959c60-259b-479d-adfe-63049c87309c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286105806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1286105806
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1933682280
Short name T463
Test name
Test status
Simulation time 63572209 ps
CPU time 0.66 seconds
Started Jul 13 04:50:02 PM PDT 24
Finished Jul 13 04:50:03 PM PDT 24
Peak memory 195176 kb
Host smart-5b93bd1a-686e-43be-a088-9dd9239db9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933682280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1933682280
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.350588800
Short name T104
Test name
Test status
Simulation time 1338992909 ps
CPU time 4.29 seconds
Started Jul 13 04:50:02 PM PDT 24
Finished Jul 13 04:50:06 PM PDT 24
Peak memory 197384 kb
Host smart-0f70c501-5610-43a8-8eba-282fb2ef55b0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350588800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stres
s.350588800
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.606881825
Short name T19
Test name
Test status
Simulation time 22301398 ps
CPU time 0.64 seconds
Started Jul 13 04:50:04 PM PDT 24
Finished Jul 13 04:50:08 PM PDT 24
Peak memory 195764 kb
Host smart-978c391e-9693-4d43-802d-62f8c7b3fb42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606881825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.606881825
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.488273513
Short name T467
Test name
Test status
Simulation time 95483875 ps
CPU time 1.4 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:07 PM PDT 24
Peak memory 196428 kb
Host smart-8eccff80-e184-450d-9bd4-4af75194c6dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488273513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.488273513
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2931882298
Short name T133
Test name
Test status
Simulation time 170517216 ps
CPU time 3.09 seconds
Started Jul 13 04:49:59 PM PDT 24
Finished Jul 13 04:50:03 PM PDT 24
Peak memory 198548 kb
Host smart-78cda2d4-bb2e-4cb3-a04d-76669766fb9c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931882298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2931882298
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.3404423982
Short name T588
Test name
Test status
Simulation time 317407763 ps
CPU time 3.54 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:08 PM PDT 24
Peak memory 197232 kb
Host smart-7f59edf5-2b92-4788-805d-6f68148634f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404423982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.3404423982
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.171595512
Short name T540
Test name
Test status
Simulation time 114776545 ps
CPU time 1.2 seconds
Started Jul 13 04:50:04 PM PDT 24
Finished Jul 13 04:50:08 PM PDT 24
Peak memory 197512 kb
Host smart-32650639-0f41-4125-830d-ecc19a7a5abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171595512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.171595512
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1215502769
Short name T111
Test name
Test status
Simulation time 29181333 ps
CPU time 0.67 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:05 PM PDT 24
Peak memory 195604 kb
Host smart-ca359b76-8861-45d9-881c-d5023af7eabf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215502769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1215502769
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1932402791
Short name T250
Test name
Test status
Simulation time 670593615 ps
CPU time 2.12 seconds
Started Jul 13 04:50:01 PM PDT 24
Finished Jul 13 04:50:04 PM PDT 24
Peak memory 198624 kb
Host smart-f1939b63-c04c-46f5-a7a1-ccb21ce46db2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932402791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1932402791
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.3739045523
Short name T665
Test name
Test status
Simulation time 188169809 ps
CPU time 1.47 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:07 PM PDT 24
Peak memory 197484 kb
Host smart-fe5db444-f3c1-4d7a-84ed-b9b677ad034d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739045523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3739045523
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3329448614
Short name T335
Test name
Test status
Simulation time 143780272 ps
CPU time 1.33 seconds
Started Jul 13 04:50:05 PM PDT 24
Finished Jul 13 04:50:10 PM PDT 24
Peak memory 197192 kb
Host smart-d4e87c0a-a321-4875-a626-4c47bec93690
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329448614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3329448614
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2270165077
Short name T600
Test name
Test status
Simulation time 14718851808 ps
CPU time 50.89 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:56 PM PDT 24
Peak memory 198784 kb
Host smart-ac011d54-32d7-4e4f-ad3c-d6431fbf6cb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270165077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2270165077
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.3062307651
Short name T471
Test name
Test status
Simulation time 108595830908 ps
CPU time 1365.67 seconds
Started Jul 13 04:50:07 PM PDT 24
Finished Jul 13 05:12:55 PM PDT 24
Peak memory 199176 kb
Host smart-767a9435-af87-447b-9564-b072c3a90359
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3062307651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.3062307651
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3304912451
Short name T244
Test name
Test status
Simulation time 13557250 ps
CPU time 0.57 seconds
Started Jul 13 04:50:05 PM PDT 24
Finished Jul 13 04:50:09 PM PDT 24
Peak memory 194676 kb
Host smart-232b67da-e5c6-452f-8de0-fdbc5c9b1cf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304912451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3304912451
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.432829142
Short name T623
Test name
Test status
Simulation time 19988771 ps
CPU time 0.68 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:06 PM PDT 24
Peak memory 194668 kb
Host smart-799b800b-000d-48fc-948f-44fd75aaf4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432829142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.432829142
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.975668424
Short name T721
Test name
Test status
Simulation time 2515084841 ps
CPU time 21.77 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:28 PM PDT 24
Peak memory 197576 kb
Host smart-e04936f4-d70b-4007-ba7a-30c943e738a0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975668424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.975668424
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.4187715053
Short name T550
Test name
Test status
Simulation time 67095918 ps
CPU time 0.74 seconds
Started Jul 13 04:50:09 PM PDT 24
Finished Jul 13 04:50:11 PM PDT 24
Peak memory 197000 kb
Host smart-2c5c0e39-67cc-4d7f-be9b-3a2dd6716c49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187715053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.4187715053
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.3261158783
Short name T122
Test name
Test status
Simulation time 87876914 ps
CPU time 1.35 seconds
Started Jul 13 04:50:01 PM PDT 24
Finished Jul 13 04:50:03 PM PDT 24
Peak memory 196476 kb
Host smart-fd3c536e-8672-4759-b46f-2a773c0cf992
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261158783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.3261158783
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.3157892278
Short name T409
Test name
Test status
Simulation time 154347716 ps
CPU time 1.31 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:07 PM PDT 24
Peak memory 198532 kb
Host smart-29d04f85-95cb-42e5-909e-59fe5322bf7b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157892278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.3157892278
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2990819860
Short name T130
Test name
Test status
Simulation time 592145531 ps
CPU time 1.44 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:06 PM PDT 24
Peak memory 197132 kb
Host smart-e7d5576f-6009-4013-90f0-4e6dea362d47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990819860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2990819860
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.2739305078
Short name T255
Test name
Test status
Simulation time 113787849 ps
CPU time 1.32 seconds
Started Jul 13 04:50:07 PM PDT 24
Finished Jul 13 04:50:10 PM PDT 24
Peak memory 196444 kb
Host smart-e706bbfd-bbe0-4396-9ae1-88c6bb8d3dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739305078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2739305078
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2612174789
Short name T288
Test name
Test status
Simulation time 20866157 ps
CPU time 0.84 seconds
Started Jul 13 04:50:02 PM PDT 24
Finished Jul 13 04:50:05 PM PDT 24
Peak memory 197252 kb
Host smart-be507269-a888-45dc-a33c-04a5311b5ec7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612174789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2612174789
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1472218844
Short name T3
Test name
Test status
Simulation time 510017154 ps
CPU time 5.93 seconds
Started Jul 13 04:50:04 PM PDT 24
Finished Jul 13 04:50:13 PM PDT 24
Peak memory 198608 kb
Host smart-3f92b1b9-1cd1-4780-a61f-985c8076f82b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472218844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.1472218844
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.3225621241
Short name T667
Test name
Test status
Simulation time 38155906 ps
CPU time 1.12 seconds
Started Jul 13 04:50:04 PM PDT 24
Finished Jul 13 04:50:08 PM PDT 24
Peak memory 196260 kb
Host smart-a384f311-638f-4d40-9c9a-e14412101380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225621241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.3225621241
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.259087238
Short name T489
Test name
Test status
Simulation time 26405217 ps
CPU time 0.89 seconds
Started Jul 13 04:50:05 PM PDT 24
Finished Jul 13 04:50:09 PM PDT 24
Peak memory 196996 kb
Host smart-6eb2468a-52fc-44a2-a90b-e160d115f5ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259087238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.259087238
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2508175108
Short name T518
Test name
Test status
Simulation time 1390916636 ps
CPU time 43.65 seconds
Started Jul 13 04:50:07 PM PDT 24
Finished Jul 13 04:50:53 PM PDT 24
Peak memory 198632 kb
Host smart-060771e2-5819-4884-8982-28232f123de8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508175108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2508175108
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.276659996
Short name T585
Test name
Test status
Simulation time 21814598 ps
CPU time 0.63 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:07 PM PDT 24
Peak memory 194704 kb
Host smart-cf7c8573-5f66-46c6-8a8e-648686c86c02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276659996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.276659996
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.4193053545
Short name T392
Test name
Test status
Simulation time 24548959 ps
CPU time 0.87 seconds
Started Jul 13 04:50:05 PM PDT 24
Finished Jul 13 04:50:09 PM PDT 24
Peak memory 195916 kb
Host smart-fc36a635-a3ad-4c83-9b43-5269e16b7fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193053545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.4193053545
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.504614477
Short name T435
Test name
Test status
Simulation time 1045138821 ps
CPU time 15.18 seconds
Started Jul 13 04:50:04 PM PDT 24
Finished Jul 13 04:50:22 PM PDT 24
Peak memory 198640 kb
Host smart-84670a6d-f11c-400f-8c98-d4f75f747b99
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504614477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stres
s.504614477
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.28363754
Short name T509
Test name
Test status
Simulation time 46271273 ps
CPU time 0.89 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:07 PM PDT 24
Peak memory 197324 kb
Host smart-68ff6e20-0ec9-411e-9881-23d882beb15d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28363754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.28363754
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.350592557
Short name T668
Test name
Test status
Simulation time 292190449 ps
CPU time 1 seconds
Started Jul 13 04:50:06 PM PDT 24
Finished Jul 13 04:50:10 PM PDT 24
Peak memory 196688 kb
Host smart-f2576f8b-5772-4ed9-9f47-f250bac6572c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350592557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.350592557
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1996457630
Short name T191
Test name
Test status
Simulation time 76442877 ps
CPU time 2.88 seconds
Started Jul 13 04:50:09 PM PDT 24
Finished Jul 13 04:50:13 PM PDT 24
Peak memory 198632 kb
Host smart-92dd9e53-1152-4124-8bc1-95db882446c7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996457630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1996457630
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3501640563
Short name T359
Test name
Test status
Simulation time 298108617 ps
CPU time 1.73 seconds
Started Jul 13 04:50:05 PM PDT 24
Finished Jul 13 04:50:10 PM PDT 24
Peak memory 196528 kb
Host smart-3e90aa17-bf1f-4d95-a793-0c97250d6d7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501640563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3501640563
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.2655208005
Short name T187
Test name
Test status
Simulation time 149070472 ps
CPU time 1.11 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:06 PM PDT 24
Peak memory 196660 kb
Host smart-8d623112-73f9-4c98-95d3-1a4abe3145aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655208005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.2655208005
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3524665415
Short name T243
Test name
Test status
Simulation time 25293258 ps
CPU time 1.02 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:06 PM PDT 24
Peak memory 196572 kb
Host smart-290ce1eb-a2a9-42b3-a5ec-11f29cead19b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524665415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3524665415
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2443374588
Short name T670
Test name
Test status
Simulation time 22300955 ps
CPU time 1.12 seconds
Started Jul 13 04:50:05 PM PDT 24
Finished Jul 13 04:50:09 PM PDT 24
Peak memory 196952 kb
Host smart-a7ee9b63-0bc2-4679-bacc-1c76f4f3cb25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443374588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.2443374588
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.2552973922
Short name T190
Test name
Test status
Simulation time 351057948 ps
CPU time 1.27 seconds
Started Jul 13 04:50:05 PM PDT 24
Finished Jul 13 04:50:09 PM PDT 24
Peak memory 196504 kb
Host smart-235dea52-bdab-45da-a90b-c55bf3085fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552973922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2552973922
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2840539353
Short name T291
Test name
Test status
Simulation time 98204913 ps
CPU time 1.38 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:07 PM PDT 24
Peak memory 196312 kb
Host smart-19daad18-9412-447a-a517-7c5baa682108
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840539353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2840539353
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1820750554
Short name T173
Test name
Test status
Simulation time 34291083699 ps
CPU time 91.44 seconds
Started Jul 13 04:50:05 PM PDT 24
Finished Jul 13 04:51:39 PM PDT 24
Peak memory 198776 kb
Host smart-344595c8-acd7-45f3-a482-a9c174a96b60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820750554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1820750554
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.2822063508
Short name T690
Test name
Test status
Simulation time 79689842016 ps
CPU time 1019.75 seconds
Started Jul 13 04:50:07 PM PDT 24
Finished Jul 13 05:07:09 PM PDT 24
Peak memory 198848 kb
Host smart-5b638835-c65c-42fd-a34c-411ba482c9e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2822063508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.2822063508
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1948179202
Short name T234
Test name
Test status
Simulation time 13676361 ps
CPU time 0.6 seconds
Started Jul 13 04:50:11 PM PDT 24
Finished Jul 13 04:50:13 PM PDT 24
Peak memory 194620 kb
Host smart-9dca2956-4a82-4adb-bdf9-7c9e9844bf00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948179202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1948179202
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1816636897
Short name T502
Test name
Test status
Simulation time 33235784 ps
CPU time 0.72 seconds
Started Jul 13 04:50:08 PM PDT 24
Finished Jul 13 04:50:10 PM PDT 24
Peak memory 194644 kb
Host smart-886b58e6-33a3-493b-bbeb-1e38432a8930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816636897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1816636897
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2227076294
Short name T411
Test name
Test status
Simulation time 1106701901 ps
CPU time 12.49 seconds
Started Jul 13 04:50:10 PM PDT 24
Finished Jul 13 04:50:24 PM PDT 24
Peak memory 198568 kb
Host smart-ba009a39-a28d-46ed-9dcc-00da72196eac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227076294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2227076294
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.1628856178
Short name T315
Test name
Test status
Simulation time 115412413 ps
CPU time 0.65 seconds
Started Jul 13 04:50:07 PM PDT 24
Finished Jul 13 04:50:10 PM PDT 24
Peak memory 194268 kb
Host smart-abdb725a-b7ef-4e05-8b95-7b0a6b7ce26c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628856178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1628856178
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1344216652
Short name T693
Test name
Test status
Simulation time 54616681 ps
CPU time 1.03 seconds
Started Jul 13 04:50:08 PM PDT 24
Finished Jul 13 04:50:11 PM PDT 24
Peak memory 196552 kb
Host smart-f7061801-8438-40f8-b110-b041c3532f7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344216652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1344216652
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3263326349
Short name T115
Test name
Test status
Simulation time 97173582 ps
CPU time 1.7 seconds
Started Jul 13 04:50:10 PM PDT 24
Finished Jul 13 04:50:13 PM PDT 24
Peak memory 197352 kb
Host smart-d57cba1d-5221-4d0b-9096-4381d61dac4f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263326349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.3263326349
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.732302199
Short name T333
Test name
Test status
Simulation time 213141794 ps
CPU time 1.03 seconds
Started Jul 13 04:50:06 PM PDT 24
Finished Jul 13 04:50:10 PM PDT 24
Peak memory 196360 kb
Host smart-21a8a80e-067c-4d1d-a338-818f35f630ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732302199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger.
732302199
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2254788110
Short name T681
Test name
Test status
Simulation time 20796489 ps
CPU time 0.93 seconds
Started Jul 13 04:50:08 PM PDT 24
Finished Jul 13 04:50:11 PM PDT 24
Peak memory 196068 kb
Host smart-170f79b9-a31f-4975-814b-4ad13194d090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254788110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2254788110
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.815024819
Short name T561
Test name
Test status
Simulation time 36266178 ps
CPU time 1.01 seconds
Started Jul 13 04:50:02 PM PDT 24
Finished Jul 13 04:50:05 PM PDT 24
Peak memory 196708 kb
Host smart-4a798fe3-1c63-4505-a531-106dc30999bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815024819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.815024819
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.4016401779
Short name T363
Test name
Test status
Simulation time 227139851 ps
CPU time 5.04 seconds
Started Jul 13 04:50:17 PM PDT 24
Finished Jul 13 04:50:22 PM PDT 24
Peak memory 198612 kb
Host smart-4ae36e8f-f2cf-495f-bd69-3bc04df64a57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016401779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.4016401779
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1853833
Short name T352
Test name
Test status
Simulation time 77637391 ps
CPU time 1.28 seconds
Started Jul 13 04:50:03 PM PDT 24
Finished Jul 13 04:50:08 PM PDT 24
Peak memory 197340 kb
Host smart-befb5763-0efb-4247-a863-e3d24b1b34ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1853833
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.60293285
Short name T269
Test name
Test status
Simulation time 73019772 ps
CPU time 1.08 seconds
Started Jul 13 04:50:06 PM PDT 24
Finished Jul 13 04:50:10 PM PDT 24
Peak memory 197328 kb
Host smart-9d430c49-0037-4856-b4dd-f734a76a6c67
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60293285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.60293285
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.611981159
Short name T497
Test name
Test status
Simulation time 21863269436 ps
CPU time 141.76 seconds
Started Jul 13 04:50:12 PM PDT 24
Finished Jul 13 04:52:34 PM PDT 24
Peak memory 198708 kb
Host smart-70aa1ab5-1197-48bf-9438-5b092e6105a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611981159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.g
pio_stress_all.611981159
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.2889505933
Short name T59
Test name
Test status
Simulation time 96305441608 ps
CPU time 1428.23 seconds
Started Jul 13 04:50:09 PM PDT 24
Finished Jul 13 05:13:59 PM PDT 24
Peak memory 198940 kb
Host smart-ba15f639-0b5b-4be2-acc2-e9fba6ff6691
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2889505933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.2889505933
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.1066261785
Short name T478
Test name
Test status
Simulation time 13353965 ps
CPU time 0.57 seconds
Started Jul 13 04:50:12 PM PDT 24
Finished Jul 13 04:50:13 PM PDT 24
Peak memory 194652 kb
Host smart-a4ee8d9f-5b90-4e30-ae60-7c8ef280f413
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066261785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.1066261785
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.2864046229
Short name T604
Test name
Test status
Simulation time 44321381 ps
CPU time 0.82 seconds
Started Jul 13 04:50:14 PM PDT 24
Finished Jul 13 04:50:15 PM PDT 24
Peak memory 196408 kb
Host smart-beacbd2b-26fc-4dfb-91f4-cb11bd7ac6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864046229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.2864046229
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.4077623824
Short name T546
Test name
Test status
Simulation time 706874473 ps
CPU time 24.38 seconds
Started Jul 13 04:50:10 PM PDT 24
Finished Jul 13 04:50:36 PM PDT 24
Peak memory 198564 kb
Host smart-9c08a298-49d0-463c-b320-63df19aa81d7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077623824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.4077623824
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.4210131370
Short name T658
Test name
Test status
Simulation time 65880627 ps
CPU time 1.08 seconds
Started Jul 13 04:50:10 PM PDT 24
Finished Jul 13 04:50:13 PM PDT 24
Peak memory 198748 kb
Host smart-751aefd6-3957-4890-a2ee-de79f9777773
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210131370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.4210131370
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.1168092149
Short name T224
Test name
Test status
Simulation time 573212639 ps
CPU time 1.26 seconds
Started Jul 13 04:50:09 PM PDT 24
Finished Jul 13 04:50:12 PM PDT 24
Peak memory 198736 kb
Host smart-d5111598-d192-4080-817f-8e0215384c83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168092149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1168092149
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.265141851
Short name T480
Test name
Test status
Simulation time 90386256 ps
CPU time 1.16 seconds
Started Jul 13 04:50:11 PM PDT 24
Finished Jul 13 04:50:13 PM PDT 24
Peak memory 197952 kb
Host smart-ac86193e-1b59-49a7-b3ae-6beff85c5e68
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265141851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.265141851
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2171203713
Short name T676
Test name
Test status
Simulation time 641873771 ps
CPU time 1.97 seconds
Started Jul 13 04:50:10 PM PDT 24
Finished Jul 13 04:50:13 PM PDT 24
Peak memory 197772 kb
Host smart-8d165352-5025-42df-bf48-3c9abbd153af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171203713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2171203713
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.4084004283
Short name T172
Test name
Test status
Simulation time 112376356 ps
CPU time 1.24 seconds
Started Jul 13 04:50:11 PM PDT 24
Finished Jul 13 04:50:13 PM PDT 24
Peak memory 197580 kb
Host smart-b7908d7a-7f0e-4a67-bfdb-2e35116d4a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084004283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.4084004283
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3205254108
Short name T128
Test name
Test status
Simulation time 55967395 ps
CPU time 1.01 seconds
Started Jul 13 04:50:16 PM PDT 24
Finished Jul 13 04:50:18 PM PDT 24
Peak memory 196600 kb
Host smart-6e25182a-8342-4f97-aa50-73b952bfe290
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205254108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3205254108
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3091566180
Short name T192
Test name
Test status
Simulation time 3285381879 ps
CPU time 6.15 seconds
Started Jul 13 04:50:08 PM PDT 24
Finished Jul 13 04:50:16 PM PDT 24
Peak memory 198740 kb
Host smart-7c4a3483-54ac-4423-868c-ed63439d8662
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091566180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3091566180
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.3045305467
Short name T366
Test name
Test status
Simulation time 32786836 ps
CPU time 1.02 seconds
Started Jul 13 04:50:07 PM PDT 24
Finished Jul 13 04:50:10 PM PDT 24
Peak memory 196204 kb
Host smart-a30f06fd-569c-4f14-9b8b-79991833863b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045305467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.3045305467
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.200678734
Short name T571
Test name
Test status
Simulation time 345307492 ps
CPU time 0.93 seconds
Started Jul 13 04:50:17 PM PDT 24
Finished Jul 13 04:50:18 PM PDT 24
Peak memory 195888 kb
Host smart-b30c7aaf-328c-483b-a561-9803e1677b5e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200678734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.200678734
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.921610502
Short name T416
Test name
Test status
Simulation time 16961728590 ps
CPU time 26.17 seconds
Started Jul 13 04:50:08 PM PDT 24
Finished Jul 13 04:50:36 PM PDT 24
Peak memory 198676 kb
Host smart-6fcdfab3-b913-4a09-a17c-04def5232e55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921610502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.g
pio_stress_all.921610502
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1018351922
Short name T198
Test name
Test status
Simulation time 29219598 ps
CPU time 0.55 seconds
Started Jul 13 04:50:20 PM PDT 24
Finished Jul 13 04:50:21 PM PDT 24
Peak memory 194632 kb
Host smart-2ca2f5fd-5942-4147-94fa-5c80fda348f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018351922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1018351922
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2660940628
Short name T294
Test name
Test status
Simulation time 18026857 ps
CPU time 0.61 seconds
Started Jul 13 04:50:11 PM PDT 24
Finished Jul 13 04:50:12 PM PDT 24
Peak memory 195052 kb
Host smart-98c6a1ca-c6c0-488c-adef-a1b4eda173ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660940628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2660940628
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2200904443
Short name T188
Test name
Test status
Simulation time 437509394 ps
CPU time 24.38 seconds
Started Jul 13 04:50:18 PM PDT 24
Finished Jul 13 04:50:43 PM PDT 24
Peak memory 197604 kb
Host smart-e5669e02-d37c-4874-826e-c34fcb5765e9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200904443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2200904443
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2335421137
Short name T511
Test name
Test status
Simulation time 578344008 ps
CPU time 0.88 seconds
Started Jul 13 04:50:21 PM PDT 24
Finished Jul 13 04:50:22 PM PDT 24
Peak memory 197680 kb
Host smart-6d0293c9-3675-4290-a0f3-74589e2b156c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335421137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2335421137
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3059133799
Short name T155
Test name
Test status
Simulation time 120530103 ps
CPU time 1.21 seconds
Started Jul 13 04:50:12 PM PDT 24
Finished Jul 13 04:50:14 PM PDT 24
Peak memory 196676 kb
Host smart-2d4ef1dd-a062-4942-980b-0aa0cadf65bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059133799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3059133799
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1555821884
Short name T579
Test name
Test status
Simulation time 355472533 ps
CPU time 3.28 seconds
Started Jul 13 04:50:09 PM PDT 24
Finished Jul 13 04:50:14 PM PDT 24
Peak memory 198940 kb
Host smart-e7db9980-e358-470b-a231-2d09922bf5ae
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555821884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1555821884
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.717010273
Short name T362
Test name
Test status
Simulation time 91001771 ps
CPU time 2.69 seconds
Started Jul 13 04:50:12 PM PDT 24
Finished Jul 13 04:50:15 PM PDT 24
Peak memory 197896 kb
Host smart-088966e4-f920-43c4-ac99-3ec101959c98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717010273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.
717010273
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.216208477
Short name T653
Test name
Test status
Simulation time 41551724 ps
CPU time 0.65 seconds
Started Jul 13 04:50:10 PM PDT 24
Finished Jul 13 04:50:12 PM PDT 24
Peak memory 194832 kb
Host smart-8900d247-bc48-4e2f-9b78-1a3d67320c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216208477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.216208477
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1071593119
Short name T701
Test name
Test status
Simulation time 107583782 ps
CPU time 0.96 seconds
Started Jul 13 04:50:11 PM PDT 24
Finished Jul 13 04:50:13 PM PDT 24
Peak memory 197320 kb
Host smart-cc7b4226-5b9f-4546-91d7-6ff0bf5eafc0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071593119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1071593119
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.425915521
Short name T565
Test name
Test status
Simulation time 2403486447 ps
CPU time 3 seconds
Started Jul 13 04:50:18 PM PDT 24
Finished Jul 13 04:50:21 PM PDT 24
Peak memory 198596 kb
Host smart-f414aca0-8bed-4a7b-b6bd-36d45daf55b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425915521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ran
dom_long_reg_writes_reg_reads.425915521
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.2775196847
Short name T194
Test name
Test status
Simulation time 88095835 ps
CPU time 0.98 seconds
Started Jul 13 04:50:09 PM PDT 24
Finished Jul 13 04:50:12 PM PDT 24
Peak memory 196988 kb
Host smart-8042eae2-8772-46d3-b2c5-8543b75fe057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775196847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.2775196847
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2466257954
Short name T593
Test name
Test status
Simulation time 111947367 ps
CPU time 1.12 seconds
Started Jul 13 04:50:17 PM PDT 24
Finished Jul 13 04:50:19 PM PDT 24
Peak memory 196356 kb
Host smart-bc375333-9dcf-49d1-83b8-1353cf1bee54
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466257954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2466257954
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.311656818
Short name T656
Test name
Test status
Simulation time 10062544233 ps
CPU time 39.64 seconds
Started Jul 13 04:50:19 PM PDT 24
Finished Jul 13 04:50:59 PM PDT 24
Peak memory 198756 kb
Host smart-314c7461-e941-4c94-ad3f-4b245ca7b209
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311656818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.g
pio_stress_all.311656818
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.1930433976
Short name T692
Test name
Test status
Simulation time 108377910404 ps
CPU time 1381.44 seconds
Started Jul 13 04:50:22 PM PDT 24
Finished Jul 13 05:13:24 PM PDT 24
Peak memory 198832 kb
Host smart-586534e6-c5ae-4730-bfb9-361af4b7ff23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1930433976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.1930433976
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1922172413
Short name T336
Test name
Test status
Simulation time 19602678 ps
CPU time 0.59 seconds
Started Jul 13 04:48:38 PM PDT 24
Finished Jul 13 04:48:40 PM PDT 24
Peak memory 195312 kb
Host smart-77729f2c-cfe3-4734-9e92-0c84654e2069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922172413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1922172413
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1651061065
Short name T267
Test name
Test status
Simulation time 181420594 ps
CPU time 0.79 seconds
Started Jul 13 04:48:31 PM PDT 24
Finished Jul 13 04:48:34 PM PDT 24
Peak memory 195884 kb
Host smart-45f6b19b-c199-4f7a-bb12-09c825f63320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651061065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.1651061065
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.1703221097
Short name T444
Test name
Test status
Simulation time 1216583653 ps
CPU time 23.1 seconds
Started Jul 13 04:48:30 PM PDT 24
Finished Jul 13 04:48:56 PM PDT 24
Peak memory 197540 kb
Host smart-bb8f095c-41b8-4ffa-aa53-b432fe2379af
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703221097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.1703221097
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3553725145
Short name T9
Test name
Test status
Simulation time 192688164 ps
CPU time 0.69 seconds
Started Jul 13 04:48:30 PM PDT 24
Finished Jul 13 04:48:33 PM PDT 24
Peak memory 195176 kb
Host smart-7fbe690d-30e4-4d20-adc7-f84b8383b068
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553725145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3553725145
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3916409121
Short name T338
Test name
Test status
Simulation time 99077724 ps
CPU time 0.74 seconds
Started Jul 13 04:48:29 PM PDT 24
Finished Jul 13 04:48:32 PM PDT 24
Peak memory 195644 kb
Host smart-8ed802b8-cb1c-48e0-9e98-e995a981a8e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916409121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3916409121
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.1668480498
Short name T206
Test name
Test status
Simulation time 59764987 ps
CPU time 2.19 seconds
Started Jul 13 04:48:30 PM PDT 24
Finished Jul 13 04:48:34 PM PDT 24
Peak memory 198752 kb
Host smart-88f837ac-063a-431e-bcf5-ebb57d48c906
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668480498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.1668480498
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.3501325093
Short name T625
Test name
Test status
Simulation time 32450568 ps
CPU time 1.1 seconds
Started Jul 13 04:48:42 PM PDT 24
Finished Jul 13 04:48:45 PM PDT 24
Peak memory 196328 kb
Host smart-a140da1b-cf9c-4b01-a43b-9d3e4f0884b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501325093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
3501325093
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.762618088
Short name T310
Test name
Test status
Simulation time 59303593 ps
CPU time 1.16 seconds
Started Jul 13 04:48:30 PM PDT 24
Finished Jul 13 04:48:32 PM PDT 24
Peak memory 196596 kb
Host smart-e9f17472-eaa3-4e7e-8e28-b4a09568df90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762618088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.762618088
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3611333180
Short name T712
Test name
Test status
Simulation time 34831342 ps
CPU time 0.86 seconds
Started Jul 13 04:48:42 PM PDT 24
Finished Jul 13 04:48:45 PM PDT 24
Peak memory 195964 kb
Host smart-6422185c-adcd-4a28-8475-032102c884b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611333180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3611333180
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3890300166
Short name T6
Test name
Test status
Simulation time 352497432 ps
CPU time 4.15 seconds
Started Jul 13 04:48:30 PM PDT 24
Finished Jul 13 04:48:36 PM PDT 24
Peak memory 198584 kb
Host smart-b25a3230-7d14-4d90-8855-392d749e5e2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890300166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3890300166
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.996673413
Short name T174
Test name
Test status
Simulation time 257743607 ps
CPU time 1.18 seconds
Started Jul 13 04:48:31 PM PDT 24
Finished Jul 13 04:48:35 PM PDT 24
Peak memory 196212 kb
Host smart-348f9a64-c608-499f-82b8-b8e4548e29ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996673413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.996673413
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2724196879
Short name T459
Test name
Test status
Simulation time 62623953 ps
CPU time 1.2 seconds
Started Jul 13 04:48:31 PM PDT 24
Finished Jul 13 04:48:35 PM PDT 24
Peak memory 196396 kb
Host smart-d8442572-0caa-4c31-804b-bd22ee1b070c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724196879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2724196879
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1447406930
Short name T56
Test name
Test status
Simulation time 13592796474 ps
CPU time 104.33 seconds
Started Jul 13 04:48:30 PM PDT 24
Finished Jul 13 04:50:17 PM PDT 24
Peak memory 198788 kb
Host smart-ac00c952-2500-485e-8287-52ec8d9248a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447406930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1447406930
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3433625166
Short name T722
Test name
Test status
Simulation time 11847810 ps
CPU time 0.58 seconds
Started Jul 13 04:48:38 PM PDT 24
Finished Jul 13 04:48:40 PM PDT 24
Peak memory 194540 kb
Host smart-cb300b13-26df-42f1-94be-3315f030212c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433625166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3433625166
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1854091671
Short name T264
Test name
Test status
Simulation time 20750261 ps
CPU time 0.69 seconds
Started Jul 13 04:48:38 PM PDT 24
Finished Jul 13 04:48:39 PM PDT 24
Peak memory 195408 kb
Host smart-e9e35c0f-0e73-44d4-a4ca-cd7dda848a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854091671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1854091671
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.2684582962
Short name T108
Test name
Test status
Simulation time 402616111 ps
CPU time 10.59 seconds
Started Jul 13 04:48:38 PM PDT 24
Finished Jul 13 04:48:50 PM PDT 24
Peak memory 198652 kb
Host smart-459a2b1b-34e7-4c5c-aa9c-5727a704e464
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684582962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.2684582962
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3643963923
Short name T669
Test name
Test status
Simulation time 74111545 ps
CPU time 0.77 seconds
Started Jul 13 04:48:39 PM PDT 24
Finished Jul 13 04:48:42 PM PDT 24
Peak memory 197144 kb
Host smart-dd39d08c-8e9e-431d-8fb7-ee941723c577
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643963923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3643963923
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3990661583
Short name T674
Test name
Test status
Simulation time 198168318 ps
CPU time 1.55 seconds
Started Jul 13 04:48:39 PM PDT 24
Finished Jul 13 04:48:43 PM PDT 24
Peak memory 198652 kb
Host smart-a8d845cb-ab77-4cef-a563-b93305b7539a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990661583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3990661583
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3082797364
Short name T199
Test name
Test status
Simulation time 204978714 ps
CPU time 2.14 seconds
Started Jul 13 04:48:41 PM PDT 24
Finished Jul 13 04:48:45 PM PDT 24
Peak memory 198616 kb
Host smart-5572fdec-89db-48e9-a4aa-3d46491621a5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082797364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3082797364
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.2750931808
Short name T247
Test name
Test status
Simulation time 150192178 ps
CPU time 2.57 seconds
Started Jul 13 04:48:40 PM PDT 24
Finished Jul 13 04:48:46 PM PDT 24
Peak memory 197724 kb
Host smart-c0db75cc-00b3-4feb-9f90-5ca9f2ddc31c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750931808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
2750931808
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.1615149518
Short name T386
Test name
Test status
Simulation time 51692120 ps
CPU time 1.12 seconds
Started Jul 13 04:48:40 PM PDT 24
Finished Jul 13 04:48:44 PM PDT 24
Peak memory 196752 kb
Host smart-936742c9-3fa4-4e46-8f50-8bd495e37c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615149518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1615149518
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.2251540067
Short name T602
Test name
Test status
Simulation time 82348013 ps
CPU time 0.84 seconds
Started Jul 13 04:48:38 PM PDT 24
Finished Jul 13 04:48:40 PM PDT 24
Peak memory 196116 kb
Host smart-26a2ccea-450a-4b17-950f-a68ec56a5384
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251540067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.2251540067
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.641167252
Short name T551
Test name
Test status
Simulation time 539459032 ps
CPU time 2.74 seconds
Started Jul 13 04:48:42 PM PDT 24
Finished Jul 13 04:48:47 PM PDT 24
Peak memory 198604 kb
Host smart-56b0f056-1e0b-4afb-97f9-174e5a7c10c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641167252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.641167252
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3535389999
Short name T644
Test name
Test status
Simulation time 33308387 ps
CPU time 0.96 seconds
Started Jul 13 04:48:38 PM PDT 24
Finished Jul 13 04:48:40 PM PDT 24
Peak memory 197220 kb
Host smart-da316c29-d9f4-4e06-b836-004b61eff735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535389999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3535389999
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3690079502
Short name T487
Test name
Test status
Simulation time 59538685 ps
CPU time 1.01 seconds
Started Jul 13 04:48:41 PM PDT 24
Finished Jul 13 04:48:44 PM PDT 24
Peak memory 196084 kb
Host smart-319b1ca6-f932-4f42-8028-ab03f70a5564
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690079502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3690079502
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.487127310
Short name T422
Test name
Test status
Simulation time 15156984947 ps
CPU time 214.08 seconds
Started Jul 13 04:48:39 PM PDT 24
Finished Jul 13 04:52:14 PM PDT 24
Peak memory 198840 kb
Host smart-c0295fc8-a6e7-49f7-b464-c74bf11626be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487127310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp
io_stress_all.487127310
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2869413769
Short name T334
Test name
Test status
Simulation time 52828511 ps
CPU time 0.62 seconds
Started Jul 13 04:48:39 PM PDT 24
Finished Jul 13 04:48:41 PM PDT 24
Peak memory 195252 kb
Host smart-407e11fe-e63b-49cd-aca0-a6c0a9ae6a30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869413769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2869413769
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3038937242
Short name T705
Test name
Test status
Simulation time 43170268 ps
CPU time 0.88 seconds
Started Jul 13 04:48:40 PM PDT 24
Finished Jul 13 04:48:43 PM PDT 24
Peak memory 197024 kb
Host smart-c2575169-caa6-4226-9cbd-93d980ceccf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038937242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3038937242
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.256673316
Short name T568
Test name
Test status
Simulation time 415218423 ps
CPU time 21.75 seconds
Started Jul 13 04:48:40 PM PDT 24
Finished Jul 13 04:49:04 PM PDT 24
Peak memory 197724 kb
Host smart-32b7c306-b3b3-473a-b642-326b0195dc45
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256673316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stress
.256673316
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.3809750089
Short name T643
Test name
Test status
Simulation time 61440848 ps
CPU time 0.93 seconds
Started Jul 13 04:48:38 PM PDT 24
Finished Jul 13 04:48:40 PM PDT 24
Peak memory 196616 kb
Host smart-22de1526-5b55-42b5-9a37-bb9bf8a90076
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809750089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.3809750089
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2847808316
Short name T536
Test name
Test status
Simulation time 422207489 ps
CPU time 1.54 seconds
Started Jul 13 04:48:43 PM PDT 24
Finished Jul 13 04:48:47 PM PDT 24
Peak memory 197624 kb
Host smart-4147280b-dfce-43b1-b75e-545dc23fd482
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847808316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2847808316
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.542514932
Short name T414
Test name
Test status
Simulation time 247337627 ps
CPU time 2.63 seconds
Started Jul 13 04:48:39 PM PDT 24
Finished Jul 13 04:48:44 PM PDT 24
Peak memory 198696 kb
Host smart-83c35a58-8abc-41fa-ad02-6e63f4288a84
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542514932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.gpio_intr_with_filter_rand_intr_event.542514932
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.753794087
Short name T631
Test name
Test status
Simulation time 748217177 ps
CPU time 2.09 seconds
Started Jul 13 04:48:38 PM PDT 24
Finished Jul 13 04:48:41 PM PDT 24
Peak memory 196436 kb
Host smart-bef3091f-4f60-455f-98e3-4186314645ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753794087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.753794087
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.4022510454
Short name T319
Test name
Test status
Simulation time 21190961 ps
CPU time 0.76 seconds
Started Jul 13 04:48:41 PM PDT 24
Finished Jul 13 04:48:44 PM PDT 24
Peak memory 195952 kb
Host smart-8d8d6232-8bee-4d6a-b25a-952bae334c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022510454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.4022510454
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3052469197
Short name T702
Test name
Test status
Simulation time 26128204 ps
CPU time 1.05 seconds
Started Jul 13 04:48:40 PM PDT 24
Finished Jul 13 04:48:43 PM PDT 24
Peak memory 196640 kb
Host smart-ffd663f5-c007-4131-bb83-530039b4645a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052469197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3052469197
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1994496700
Short name T344
Test name
Test status
Simulation time 246825964 ps
CPU time 6.06 seconds
Started Jul 13 04:48:40 PM PDT 24
Finished Jul 13 04:48:49 PM PDT 24
Peak memory 198348 kb
Host smart-16440474-1309-405c-9879-acea117333df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994496700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.1994496700
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.4186611536
Short name T524
Test name
Test status
Simulation time 74096199 ps
CPU time 0.67 seconds
Started Jul 13 04:48:39 PM PDT 24
Finished Jul 13 04:48:41 PM PDT 24
Peak memory 194624 kb
Host smart-02eb2225-d82c-4d7e-b6f4-913519f875cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186611536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.4186611536
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.1325307418
Short name T246
Test name
Test status
Simulation time 174841538 ps
CPU time 1.17 seconds
Started Jul 13 04:48:40 PM PDT 24
Finished Jul 13 04:48:43 PM PDT 24
Peak memory 197324 kb
Host smart-eb4ebae9-7f85-47ed-8069-866f99789f3c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325307418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1325307418
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.3723051049
Short name T491
Test name
Test status
Simulation time 70335677028 ps
CPU time 187.18 seconds
Started Jul 13 04:48:38 PM PDT 24
Finished Jul 13 04:51:45 PM PDT 24
Peak memory 198832 kb
Host smart-d6fa7009-7e79-426a-bf88-2993c2a6be6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723051049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.3723051049
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.2542971000
Short name T426
Test name
Test status
Simulation time 337263267035 ps
CPU time 1642.3 seconds
Started Jul 13 04:48:40 PM PDT 24
Finished Jul 13 05:16:05 PM PDT 24
Peak memory 198808 kb
Host smart-daaf745d-1f11-4066-ba02-96d27a1d12dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2542971000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.2542971000
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2540916101
Short name T38
Test name
Test status
Simulation time 78977121 ps
CPU time 0.58 seconds
Started Jul 13 04:48:45 PM PDT 24
Finished Jul 13 04:48:49 PM PDT 24
Peak memory 194560 kb
Host smart-bd44f712-dfcc-4627-a84c-e209951cf95d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540916101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2540916101
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.251812963
Short name T486
Test name
Test status
Simulation time 291336101 ps
CPU time 0.87 seconds
Started Jul 13 04:48:40 PM PDT 24
Finished Jul 13 04:48:44 PM PDT 24
Peak memory 197128 kb
Host smart-6ba46a2c-c4d5-4db6-b067-8d18f07c8790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251812963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.251812963
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1550652428
Short name T704
Test name
Test status
Simulation time 490954275 ps
CPU time 6.48 seconds
Started Jul 13 04:48:47 PM PDT 24
Finished Jul 13 04:48:57 PM PDT 24
Peak memory 198556 kb
Host smart-e4cb028d-9aec-4a80-a032-9ca51e539f15
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550652428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1550652428
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.2391916972
Short name T501
Test name
Test status
Simulation time 75054463 ps
CPU time 0.67 seconds
Started Jul 13 04:48:46 PM PDT 24
Finished Jul 13 04:48:50 PM PDT 24
Peak memory 195936 kb
Host smart-31265294-660d-4d8e-98b5-8e59f0f100d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391916972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2391916972
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2587005227
Short name T18
Test name
Test status
Simulation time 234703045 ps
CPU time 1.28 seconds
Started Jul 13 04:48:39 PM PDT 24
Finished Jul 13 04:48:43 PM PDT 24
Peak memory 197648 kb
Host smart-e4896813-2508-413b-94b0-1bde27a0dd96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587005227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2587005227
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.3770237188
Short name T240
Test name
Test status
Simulation time 58776606 ps
CPU time 2.28 seconds
Started Jul 13 04:48:45 PM PDT 24
Finished Jul 13 04:48:50 PM PDT 24
Peak memory 198664 kb
Host smart-9490ae94-6bbd-4a40-ba2d-b74866c7cd01
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770237188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.3770237188
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2008829694
Short name T252
Test name
Test status
Simulation time 870491812 ps
CPU time 3.15 seconds
Started Jul 13 04:48:48 PM PDT 24
Finished Jul 13 04:48:54 PM PDT 24
Peak memory 197328 kb
Host smart-34cc20d0-ef4f-42d1-9a9c-0a5dc0564f96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008829694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2008829694
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.4283671388
Short name T154
Test name
Test status
Simulation time 47857628 ps
CPU time 1.02 seconds
Started Jul 13 04:48:40 PM PDT 24
Finished Jul 13 04:48:44 PM PDT 24
Peak memory 196424 kb
Host smart-694a58f4-dc48-443e-81a8-62709304169e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283671388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.4283671388
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1409052551
Short name T325
Test name
Test status
Simulation time 274066821 ps
CPU time 1.26 seconds
Started Jul 13 04:48:41 PM PDT 24
Finished Jul 13 04:48:44 PM PDT 24
Peak memory 197668 kb
Host smart-de6498e8-a2a7-4e3e-85ab-b83e5cc35581
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409052551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1409052551
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3447233060
Short name T20
Test name
Test status
Simulation time 486387687 ps
CPU time 3.47 seconds
Started Jul 13 04:54:05 PM PDT 24
Finished Jul 13 04:54:09 PM PDT 24
Peak memory 198860 kb
Host smart-91fa7a84-6014-492a-9592-d43e4bf818f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447233060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3447233060
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3972911704
Short name T590
Test name
Test status
Simulation time 128933203 ps
CPU time 0.83 seconds
Started Jul 13 04:48:39 PM PDT 24
Finished Jul 13 04:48:40 PM PDT 24
Peak memory 195836 kb
Host smart-ff4cd1f4-6650-4dd5-a111-fb0a9deb0b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972911704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3972911704
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.443548517
Short name T527
Test name
Test status
Simulation time 32832034 ps
CPU time 1.17 seconds
Started Jul 13 04:48:41 PM PDT 24
Finished Jul 13 04:48:45 PM PDT 24
Peak memory 196328 kb
Host smart-8db5cf80-c8cc-4224-b0c9-0f0485c72416
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443548517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.443548517
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.3283279092
Short name T17
Test name
Test status
Simulation time 1260339785 ps
CPU time 27.14 seconds
Started Jul 13 04:48:44 PM PDT 24
Finished Jul 13 04:49:13 PM PDT 24
Peak memory 198744 kb
Host smart-b74538f1-94aa-4a12-b189-cd437b2bd2e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283279092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.3283279092
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2616354533
Short name T574
Test name
Test status
Simulation time 40168383 ps
CPU time 0.58 seconds
Started Jul 13 04:48:45 PM PDT 24
Finished Jul 13 04:48:48 PM PDT 24
Peak memory 194792 kb
Host smart-3bd43859-c91f-4e22-9965-cbe60fc96a50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616354533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2616354533
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2829680085
Short name T468
Test name
Test status
Simulation time 18717219 ps
CPU time 0.72 seconds
Started Jul 13 04:48:48 PM PDT 24
Finished Jul 13 04:48:51 PM PDT 24
Peak memory 194828 kb
Host smart-3e105de8-d96d-4b10-98b6-360a6590f507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829680085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2829680085
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2650227044
Short name T430
Test name
Test status
Simulation time 1376608742 ps
CPU time 18.75 seconds
Started Jul 13 04:48:44 PM PDT 24
Finished Jul 13 04:49:06 PM PDT 24
Peak memory 197576 kb
Host smart-ce16066e-6a8a-4d70-90f6-47a55209c83d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650227044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2650227044
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.988899926
Short name T230
Test name
Test status
Simulation time 98060301 ps
CPU time 0.69 seconds
Started Jul 13 04:48:48 PM PDT 24
Finished Jul 13 04:48:52 PM PDT 24
Peak memory 195316 kb
Host smart-b0a3d35f-4804-4484-a875-1086f24dc769
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988899926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.988899926
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.2216395177
Short name T399
Test name
Test status
Simulation time 341814865 ps
CPU time 1.24 seconds
Started Jul 13 04:48:44 PM PDT 24
Finished Jul 13 04:48:47 PM PDT 24
Peak memory 196484 kb
Host smart-b117a637-468c-43bf-b1ba-5a4ebbd83f07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216395177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.2216395177
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.3623444160
Short name T105
Test name
Test status
Simulation time 230145133 ps
CPU time 2.61 seconds
Started Jul 13 04:48:46 PM PDT 24
Finished Jul 13 04:48:52 PM PDT 24
Peak memory 198616 kb
Host smart-7771708b-1c8f-44ab-b868-0a58c947a39d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623444160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.3623444160
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.4228075080
Short name T341
Test name
Test status
Simulation time 730901315 ps
CPU time 3.11 seconds
Started Jul 13 04:48:46 PM PDT 24
Finished Jul 13 04:48:52 PM PDT 24
Peak memory 197360 kb
Host smart-a0ee186f-8032-4872-8196-a31c3e7cb501
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228075080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
4228075080
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.2596824865
Short name T361
Test name
Test status
Simulation time 366641948 ps
CPU time 1.31 seconds
Started Jul 13 04:48:44 PM PDT 24
Finished Jul 13 04:48:47 PM PDT 24
Peak memory 197548 kb
Host smart-3adbbcc7-0039-4fe5-8707-54b0a8f80c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596824865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.2596824865
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.523845940
Short name T554
Test name
Test status
Simulation time 110864975 ps
CPU time 0.72 seconds
Started Jul 13 04:48:46 PM PDT 24
Finished Jul 13 04:48:50 PM PDT 24
Peak memory 196740 kb
Host smart-3ea30649-7fde-407c-b6ab-5984db15b941
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523845940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.523845940
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.334177430
Short name T257
Test name
Test status
Simulation time 498502811 ps
CPU time 4.32 seconds
Started Jul 13 04:48:45 PM PDT 24
Finished Jul 13 04:48:52 PM PDT 24
Peak memory 198580 kb
Host smart-28144cb7-85c1-4483-be66-d192dae8ea7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334177430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.334177430
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.3996214642
Short name T508
Test name
Test status
Simulation time 300634431 ps
CPU time 1.34 seconds
Started Jul 13 04:48:44 PM PDT 24
Finished Jul 13 04:48:48 PM PDT 24
Peak memory 196192 kb
Host smart-a5ba27dd-8706-4fb9-864f-ff0a9b0abaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996214642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3996214642
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1751022190
Short name T675
Test name
Test status
Simulation time 30945838 ps
CPU time 0.93 seconds
Started Jul 13 04:48:47 PM PDT 24
Finished Jul 13 04:48:51 PM PDT 24
Peak memory 196364 kb
Host smart-fc940700-4bd2-48d7-b808-be99df877f87
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751022190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1751022190
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.114338023
Short name T717
Test name
Test status
Simulation time 11248499186 ps
CPU time 223.61 seconds
Started Jul 13 04:48:44 PM PDT 24
Finished Jul 13 04:52:31 PM PDT 24
Peak memory 198596 kb
Host smart-50e82c0b-117f-4a4e-a46e-ab61803e47ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114338023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.114338023
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.2993520980
Short name T29
Test name
Test status
Simulation time 530407511877 ps
CPU time 1689.06 seconds
Started Jul 13 04:48:45 PM PDT 24
Finished Jul 13 05:16:58 PM PDT 24
Peak memory 198920 kb
Host smart-e5871c09-d895-4346-93af-3d4c3a1fa30d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2993520980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.2993520980
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.976743429
Short name T911
Test name
Test status
Simulation time 31335846 ps
CPU time 1.05 seconds
Started Jul 13 05:52:09 PM PDT 24
Finished Jul 13 05:52:11 PM PDT 24
Peak memory 196860 kb
Host smart-9ffaf6e5-5fb3-4774-989b-97502f1f7565
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=976743429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.976743429
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3921079823
Short name T946
Test name
Test status
Simulation time 277318540 ps
CPU time 0.84 seconds
Started Jul 13 05:52:07 PM PDT 24
Finished Jul 13 05:52:09 PM PDT 24
Peak memory 196496 kb
Host smart-2d3ec6e5-25ff-4686-ad44-c9a4fd72b0c0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921079823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3921079823
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.856638496
Short name T926
Test name
Test status
Simulation time 202260725 ps
CPU time 1.16 seconds
Started Jul 13 05:52:12 PM PDT 24
Finished Jul 13 05:52:14 PM PDT 24
Peak memory 197052 kb
Host smart-2b26723f-c1b3-40b0-9139-3c3f895b1964
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=856638496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.856638496
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2172751177
Short name T933
Test name
Test status
Simulation time 106666415 ps
CPU time 1.14 seconds
Started Jul 13 05:52:11 PM PDT 24
Finished Jul 13 05:52:13 PM PDT 24
Peak memory 196960 kb
Host smart-eea33082-f4ff-4718-bf58-cfb5f59de6b8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172751177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2172751177
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.377726935
Short name T867
Test name
Test status
Simulation time 50929623 ps
CPU time 1.12 seconds
Started Jul 13 05:52:17 PM PDT 24
Finished Jul 13 05:52:21 PM PDT 24
Peak memory 198436 kb
Host smart-699193ae-8d85-4dba-a2cf-14b379615993
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=377726935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.377726935
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.700620714
Short name T898
Test name
Test status
Simulation time 86376153 ps
CPU time 1.37 seconds
Started Jul 13 05:52:20 PM PDT 24
Finished Jul 13 05:52:23 PM PDT 24
Peak memory 198504 kb
Host smart-8b637bf5-e5f5-41f7-8928-e07a5f2d6517
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700620714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.700620714
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1002572728
Short name T897
Test name
Test status
Simulation time 162729439 ps
CPU time 1.54 seconds
Started Jul 13 05:52:17 PM PDT 24
Finished Jul 13 05:52:21 PM PDT 24
Peak memory 198496 kb
Host smart-4f59405d-4f90-48ee-9c14-b2126eadbcad
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1002572728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1002572728
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2441620004
Short name T858
Test name
Test status
Simulation time 211455932 ps
CPU time 1.09 seconds
Started Jul 13 05:52:16 PM PDT 24
Finished Jul 13 05:52:18 PM PDT 24
Peak memory 196932 kb
Host smart-0fe1d1b3-0381-4624-b1fc-03f558a55a98
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441620004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2441620004
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2321162829
Short name T886
Test name
Test status
Simulation time 104326396 ps
CPU time 1.36 seconds
Started Jul 13 05:52:17 PM PDT 24
Finished Jul 13 05:52:21 PM PDT 24
Peak memory 197200 kb
Host smart-2732c92c-f1d9-4288-b70c-8c84c748fc42
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2321162829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2321162829
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3709435447
Short name T899
Test name
Test status
Simulation time 46669210 ps
CPU time 1.27 seconds
Started Jul 13 05:52:21 PM PDT 24
Finished Jul 13 05:52:24 PM PDT 24
Peak memory 197540 kb
Host smart-087a6f22-940c-47d1-9381-0d974b4645d4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709435447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3709435447
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.19295012
Short name T883
Test name
Test status
Simulation time 168062223 ps
CPU time 1.43 seconds
Started Jul 13 05:52:21 PM PDT 24
Finished Jul 13 05:52:23 PM PDT 24
Peak memory 197152 kb
Host smart-68adc27b-f104-47ac-aec0-765a00d56c27
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=19295012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.19295012
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1707186835
Short name T868
Test name
Test status
Simulation time 45176476 ps
CPU time 0.74 seconds
Started Jul 13 05:52:16 PM PDT 24
Finished Jul 13 05:52:17 PM PDT 24
Peak memory 195488 kb
Host smart-bdc6b8b9-d4cc-4d2e-83a4-ce7ee2a59be0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707186835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1707186835
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2656964345
Short name T855
Test name
Test status
Simulation time 47595341 ps
CPU time 0.87 seconds
Started Jul 13 05:52:16 PM PDT 24
Finished Jul 13 05:52:17 PM PDT 24
Peak memory 195796 kb
Host smart-0e5752e0-3b3a-42a8-9dcb-b4d86fe0a7bd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2656964345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2656964345
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.60732533
Short name T875
Test name
Test status
Simulation time 176244198 ps
CPU time 0.99 seconds
Started Jul 13 05:52:18 PM PDT 24
Finished Jul 13 05:52:21 PM PDT 24
Peak memory 196048 kb
Host smart-c87de8d8-fa5b-485c-bce1-1435a913be48
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60732533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.60732533
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.506090086
Short name T913
Test name
Test status
Simulation time 190060809 ps
CPU time 1.3 seconds
Started Jul 13 05:52:16 PM PDT 24
Finished Jul 13 05:52:18 PM PDT 24
Peak memory 197348 kb
Host smart-fcf7ca86-6dfa-44a3-9035-773ce7e3961d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=506090086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.506090086
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3650184316
Short name T888
Test name
Test status
Simulation time 172998495 ps
CPU time 0.93 seconds
Started Jul 13 05:52:21 PM PDT 24
Finished Jul 13 05:52:23 PM PDT 24
Peak memory 196132 kb
Host smart-742bcb01-73b6-4073-90ed-ee06b1c92882
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650184316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3650184316
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2476922565
Short name T916
Test name
Test status
Simulation time 197689077 ps
CPU time 1.08 seconds
Started Jul 13 05:52:22 PM PDT 24
Finished Jul 13 05:52:24 PM PDT 24
Peak memory 197236 kb
Host smart-efca5e67-563b-4590-824d-ef65dbd8f432
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2476922565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2476922565
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1961847006
Short name T887
Test name
Test status
Simulation time 156436524 ps
CPU time 1.08 seconds
Started Jul 13 05:52:17 PM PDT 24
Finished Jul 13 05:52:20 PM PDT 24
Peak memory 197012 kb
Host smart-dd8f2422-25de-4bba-a89b-f2acc5e6dd55
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961847006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1961847006
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2039140966
Short name T945
Test name
Test status
Simulation time 670375829 ps
CPU time 1.27 seconds
Started Jul 13 05:52:16 PM PDT 24
Finished Jul 13 05:52:19 PM PDT 24
Peak memory 196900 kb
Host smart-a4c14435-f8d0-4780-86ae-a0846b30c20c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2039140966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2039140966
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1142220241
Short name T893
Test name
Test status
Simulation time 58853037 ps
CPU time 1.25 seconds
Started Jul 13 05:52:18 PM PDT 24
Finished Jul 13 05:52:21 PM PDT 24
Peak memory 197344 kb
Host smart-bcc17168-1217-405b-9918-db41cec1b408
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142220241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1142220241
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.184418331
Short name T871
Test name
Test status
Simulation time 193255011 ps
CPU time 1.11 seconds
Started Jul 13 05:52:17 PM PDT 24
Finished Jul 13 05:52:21 PM PDT 24
Peak memory 196924 kb
Host smart-7417c642-1ea8-4791-81a1-58ea75f69ef6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=184418331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.184418331
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3784859077
Short name T884
Test name
Test status
Simulation time 517534943 ps
CPU time 1.08 seconds
Started Jul 13 05:52:18 PM PDT 24
Finished Jul 13 05:52:21 PM PDT 24
Peak memory 196200 kb
Host smart-2f23192a-bff8-4076-9a47-81c0e96a6eb4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784859077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3784859077
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1519535484
Short name T878
Test name
Test status
Simulation time 67550774 ps
CPU time 1.21 seconds
Started Jul 13 05:52:20 PM PDT 24
Finished Jul 13 05:52:23 PM PDT 24
Peak memory 196888 kb
Host smart-e05a1570-4b88-4dfc-9cf8-f2092092681b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1519535484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.1519535484
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3758899166
Short name T872
Test name
Test status
Simulation time 409027924 ps
CPU time 1.42 seconds
Started Jul 13 05:52:18 PM PDT 24
Finished Jul 13 05:52:21 PM PDT 24
Peak memory 197384 kb
Host smart-f9bdc53c-c97f-4178-93a3-dd93f6e71c38
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758899166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3758899166
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1548607471
Short name T936
Test name
Test status
Simulation time 53929570 ps
CPU time 1.01 seconds
Started Jul 13 05:52:18 PM PDT 24
Finished Jul 13 05:52:21 PM PDT 24
Peak memory 196952 kb
Host smart-febe315b-fab7-443d-a888-73b799b06da2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1548607471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1548607471
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1441766676
Short name T912
Test name
Test status
Simulation time 102784000 ps
CPU time 0.91 seconds
Started Jul 13 05:52:18 PM PDT 24
Finished Jul 13 05:52:21 PM PDT 24
Peak memory 197164 kb
Host smart-d3ddca0f-aa67-4a95-9161-34ed78c27647
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441766676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1441766676
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2561542558
Short name T924
Test name
Test status
Simulation time 123813889 ps
CPU time 0.82 seconds
Started Jul 13 05:52:20 PM PDT 24
Finished Jul 13 05:52:22 PM PDT 24
Peak memory 195928 kb
Host smart-98a14c3b-c8d8-4b8d-b26a-c219fbd14b2a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2561542558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2561542558
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2563281736
Short name T930
Test name
Test status
Simulation time 55221107 ps
CPU time 1.12 seconds
Started Jul 13 05:52:18 PM PDT 24
Finished Jul 13 05:52:21 PM PDT 24
Peak memory 197040 kb
Host smart-2afa8c5f-abba-427b-b428-0ef063f77cd4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563281736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2563281736
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1739553894
Short name T939
Test name
Test status
Simulation time 58854950 ps
CPU time 0.86 seconds
Started Jul 13 05:52:20 PM PDT 24
Finished Jul 13 05:52:22 PM PDT 24
Peak memory 195872 kb
Host smart-0fe0d8f0-6f06-4925-8081-94c73d5f0e41
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1739553894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1739553894
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.54490323
Short name T917
Test name
Test status
Simulation time 73620248 ps
CPU time 0.82 seconds
Started Jul 13 05:52:18 PM PDT 24
Finished Jul 13 05:52:21 PM PDT 24
Peak memory 196508 kb
Host smart-61d34050-7fd4-4307-96bc-1699a20e8336
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54490323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.54490323
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.31616732
Short name T915
Test name
Test status
Simulation time 44211403 ps
CPU time 1.3 seconds
Started Jul 13 05:52:19 PM PDT 24
Finished Jul 13 05:52:22 PM PDT 24
Peak memory 197240 kb
Host smart-ce19cf56-2155-46dd-8bb8-632bcdf813b8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=31616732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.31616732
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.249930331
Short name T869
Test name
Test status
Simulation time 367000110 ps
CPU time 1.45 seconds
Started Jul 13 05:52:17 PM PDT 24
Finished Jul 13 05:52:21 PM PDT 24
Peak memory 197160 kb
Host smart-966238a3-a668-4b09-acea-2ad92efbc5cd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249930331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.249930331
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3669615441
Short name T940
Test name
Test status
Simulation time 1084144524 ps
CPU time 1.45 seconds
Started Jul 13 05:52:17 PM PDT 24
Finished Jul 13 05:52:21 PM PDT 24
Peak memory 197200 kb
Host smart-decefdaf-e081-45c1-ba52-a471c32bcd2f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3669615441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3669615441
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4114891885
Short name T929
Test name
Test status
Simulation time 25559152 ps
CPU time 0.8 seconds
Started Jul 13 05:52:19 PM PDT 24
Finished Jul 13 05:52:22 PM PDT 24
Peak memory 195592 kb
Host smart-ae761862-75a1-49a5-b737-f36df43044f3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114891885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4114891885
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.468971038
Short name T853
Test name
Test status
Simulation time 440898490 ps
CPU time 0.83 seconds
Started Jul 13 05:52:22 PM PDT 24
Finished Jul 13 05:52:24 PM PDT 24
Peak memory 196656 kb
Host smart-9ecd6829-53fd-44b1-8241-04220e88079e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=468971038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.468971038
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2342583255
Short name T920
Test name
Test status
Simulation time 101579108 ps
CPU time 0.9 seconds
Started Jul 13 05:52:24 PM PDT 24
Finished Jul 13 05:52:25 PM PDT 24
Peak memory 196584 kb
Host smart-c4767a24-58f1-413a-8a63-b4df3b19e838
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342583255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2342583255
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1611344
Short name T873
Test name
Test status
Simulation time 116806167 ps
CPU time 0.92 seconds
Started Jul 13 05:52:31 PM PDT 24
Finished Jul 13 05:52:33 PM PDT 24
Peak memory 195640 kb
Host smart-a22b29f6-c060-490b-bfd7-649df4ecd643
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1611344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1611344
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.185324551
Short name T919
Test name
Test status
Simulation time 33745802 ps
CPU time 0.96 seconds
Started Jul 13 05:52:29 PM PDT 24
Finished Jul 13 05:52:31 PM PDT 24
Peak memory 195884 kb
Host smart-5b311423-5fbf-4877-b66e-485c81bbe1bc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185324551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.185324551
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1717059045
Short name T889
Test name
Test status
Simulation time 37830859 ps
CPU time 1.16 seconds
Started Jul 13 05:52:25 PM PDT 24
Finished Jul 13 05:52:27 PM PDT 24
Peak memory 196284 kb
Host smart-9e25b7c0-a3de-4fd8-bb7c-da02f1e6c1ec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1717059045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1717059045
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1224272072
Short name T941
Test name
Test status
Simulation time 221206276 ps
CPU time 1.01 seconds
Started Jul 13 05:52:28 PM PDT 24
Finished Jul 13 05:52:30 PM PDT 24
Peak memory 196952 kb
Host smart-110a40dd-a152-401c-8226-505a923872c4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224272072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1224272072
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1310887456
Short name T870
Test name
Test status
Simulation time 172041344 ps
CPU time 1.32 seconds
Started Jul 13 05:52:24 PM PDT 24
Finished Jul 13 05:52:27 PM PDT 24
Peak memory 197020 kb
Host smart-f5fea687-fca1-47f1-86f1-dccfb4575d5f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1310887456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1310887456
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3971999161
Short name T860
Test name
Test status
Simulation time 62827682 ps
CPU time 1.17 seconds
Started Jul 13 05:52:30 PM PDT 24
Finished Jul 13 05:52:33 PM PDT 24
Peak memory 196344 kb
Host smart-fbd3c189-b51a-4642-863d-723c919165dc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971999161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3971999161
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3194682452
Short name T859
Test name
Test status
Simulation time 38790298 ps
CPU time 1.11 seconds
Started Jul 13 05:52:23 PM PDT 24
Finished Jul 13 05:52:25 PM PDT 24
Peak memory 196328 kb
Host smart-88bbdb37-7328-42ba-b1ba-a8fc0e6427ad
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3194682452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3194682452
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1474253139
Short name T877
Test name
Test status
Simulation time 33173386 ps
CPU time 0.94 seconds
Started Jul 13 05:52:28 PM PDT 24
Finished Jul 13 05:52:30 PM PDT 24
Peak memory 196884 kb
Host smart-df291d78-bd49-4fba-8764-c24e81167ebb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474253139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1474253139
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3431031921
Short name T921
Test name
Test status
Simulation time 119734647 ps
CPU time 0.95 seconds
Started Jul 13 05:52:27 PM PDT 24
Finished Jul 13 05:52:29 PM PDT 24
Peak memory 196860 kb
Host smart-e0bbd0ec-c62b-463a-8f79-ee494535e740
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3431031921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3431031921
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2090014018
Short name T876
Test name
Test status
Simulation time 90954218 ps
CPU time 1.32 seconds
Started Jul 13 05:52:30 PM PDT 24
Finished Jul 13 05:52:33 PM PDT 24
Peak memory 196112 kb
Host smart-e77c2c3b-b86b-48c8-8068-9c957a47ebc5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090014018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2090014018
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1187872382
Short name T862
Test name
Test status
Simulation time 63703218 ps
CPU time 1.25 seconds
Started Jul 13 05:52:17 PM PDT 24
Finished Jul 13 05:52:20 PM PDT 24
Peak memory 197112 kb
Host smart-e6549ae9-9814-4b1c-b2af-6703099dbaeb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1187872382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1187872382
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4008687726
Short name T910
Test name
Test status
Simulation time 229945742 ps
CPU time 0.84 seconds
Started Jul 13 05:52:17 PM PDT 24
Finished Jul 13 05:52:19 PM PDT 24
Peak memory 195800 kb
Host smart-fe2041a4-ec80-4ff7-8ac6-3aa5ea70d7aa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008687726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4008687726
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2987959130
Short name T892
Test name
Test status
Simulation time 64269225 ps
CPU time 0.85 seconds
Started Jul 13 05:52:22 PM PDT 24
Finished Jul 13 05:52:24 PM PDT 24
Peak memory 195936 kb
Host smart-b918d8bb-5040-4363-a232-0456c7b42d2b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2987959130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2987959130
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1421486001
Short name T938
Test name
Test status
Simulation time 72602807 ps
CPU time 1.28 seconds
Started Jul 13 05:52:25 PM PDT 24
Finished Jul 13 05:52:27 PM PDT 24
Peak memory 197628 kb
Host smart-dd81bb45-6602-4d21-91f1-bbd12e1e1540
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421486001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1421486001
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1371716688
Short name T896
Test name
Test status
Simulation time 35090183 ps
CPU time 0.96 seconds
Started Jul 13 05:52:30 PM PDT 24
Finished Jul 13 05:52:33 PM PDT 24
Peak memory 197132 kb
Host smart-e74e23f2-cb08-4eef-966c-5ca3586c9a6f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1371716688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1371716688
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2465510690
Short name T900
Test name
Test status
Simulation time 28482907 ps
CPU time 0.95 seconds
Started Jul 13 05:52:27 PM PDT 24
Finished Jul 13 05:52:30 PM PDT 24
Peak memory 196680 kb
Host smart-75fc86d0-1e26-4722-a585-e809f3cb552b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465510690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2465510690
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1210394909
Short name T905
Test name
Test status
Simulation time 62369944 ps
CPU time 1.18 seconds
Started Jul 13 05:52:24 PM PDT 24
Finished Jul 13 05:52:25 PM PDT 24
Peak memory 198464 kb
Host smart-9a0d9891-b253-460b-9207-fa6ad571e6db
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1210394909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.1210394909
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2381967735
Short name T906
Test name
Test status
Simulation time 85363571 ps
CPU time 1.4 seconds
Started Jul 13 05:52:39 PM PDT 24
Finished Jul 13 05:52:41 PM PDT 24
Peak memory 198424 kb
Host smart-e122dec2-6c4a-4067-ad72-866cff7b7c4f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381967735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2381967735
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2260721900
Short name T861
Test name
Test status
Simulation time 43986185 ps
CPU time 0.93 seconds
Started Jul 13 05:52:26 PM PDT 24
Finished Jul 13 05:52:28 PM PDT 24
Peak memory 195704 kb
Host smart-247e501b-cba3-4682-9725-63fce9be2bd0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2260721900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2260721900
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1595423090
Short name T866
Test name
Test status
Simulation time 79846067 ps
CPU time 1.33 seconds
Started Jul 13 05:52:25 PM PDT 24
Finished Jul 13 05:52:27 PM PDT 24
Peak memory 196888 kb
Host smart-1a960f1c-6405-4950-a1f2-921cccb52e33
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595423090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1595423090
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3358270591
Short name T863
Test name
Test status
Simulation time 216931607 ps
CPU time 1.13 seconds
Started Jul 13 05:52:25 PM PDT 24
Finished Jul 13 05:52:27 PM PDT 24
Peak memory 196856 kb
Host smart-ea143da0-f148-4b59-aa66-25f048f02df8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3358270591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3358270591
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4075062501
Short name T881
Test name
Test status
Simulation time 163224786 ps
CPU time 1.29 seconds
Started Jul 13 05:52:22 PM PDT 24
Finished Jul 13 05:52:24 PM PDT 24
Peak memory 198436 kb
Host smart-39e04ec3-fa3d-4d83-b068-6f10db2d0431
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075062501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4075062501
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3357369524
Short name T935
Test name
Test status
Simulation time 72671167 ps
CPU time 1.03 seconds
Started Jul 13 05:52:22 PM PDT 24
Finished Jul 13 05:52:24 PM PDT 24
Peak memory 196292 kb
Host smart-06fb9d99-3cb7-4d3d-815a-69f3b1ab3f7c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3357369524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3357369524
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.668943440
Short name T909
Test name
Test status
Simulation time 300833379 ps
CPU time 0.88 seconds
Started Jul 13 05:52:28 PM PDT 24
Finished Jul 13 05:52:30 PM PDT 24
Peak memory 195712 kb
Host smart-1f274e8a-180e-477f-b89a-f89d564df5b2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668943440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.668943440
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.529095061
Short name T934
Test name
Test status
Simulation time 168811850 ps
CPU time 1.28 seconds
Started Jul 13 05:52:29 PM PDT 24
Finished Jul 13 05:52:30 PM PDT 24
Peak memory 197068 kb
Host smart-a49c2b8e-68a1-406f-99c8-d9e0b205045f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=529095061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.529095061
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1026637529
Short name T942
Test name
Test status
Simulation time 80464437 ps
CPU time 1.07 seconds
Started Jul 13 05:52:32 PM PDT 24
Finished Jul 13 05:52:35 PM PDT 24
Peak memory 197500 kb
Host smart-b6aef85c-c8de-4aca-85d4-a45265b37784
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026637529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1026637529
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2175967245
Short name T849
Test name
Test status
Simulation time 135903292 ps
CPU time 1.1 seconds
Started Jul 13 05:52:31 PM PDT 24
Finished Jul 13 05:52:34 PM PDT 24
Peak memory 196252 kb
Host smart-93e7d8ce-6011-4a4f-95af-7a188c93f450
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2175967245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2175967245
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4165694342
Short name T852
Test name
Test status
Simulation time 59480132 ps
CPU time 1.18 seconds
Started Jul 13 05:52:31 PM PDT 24
Finished Jul 13 05:52:33 PM PDT 24
Peak memory 197060 kb
Host smart-e3ff1aba-64ec-4bb5-829f-62eb562be436
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165694342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4165694342
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3545773114
Short name T932
Test name
Test status
Simulation time 519610551 ps
CPU time 1.14 seconds
Started Jul 13 05:52:25 PM PDT 24
Finished Jul 13 05:52:27 PM PDT 24
Peak memory 196964 kb
Host smart-f7baf2eb-c523-4fe9-a294-5c49262ccd20
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3545773114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3545773114
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2236641983
Short name T882
Test name
Test status
Simulation time 48734364 ps
CPU time 1.35 seconds
Started Jul 13 05:52:41 PM PDT 24
Finished Jul 13 05:52:43 PM PDT 24
Peak memory 197208 kb
Host smart-63f63f2d-8ee0-4d02-b2b3-9e30ac84aa50
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236641983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2236641983
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1695785049
Short name T895
Test name
Test status
Simulation time 187731373 ps
CPU time 1.29 seconds
Started Jul 13 05:52:28 PM PDT 24
Finished Jul 13 05:52:30 PM PDT 24
Peak memory 197332 kb
Host smart-04e8bdf1-3841-4584-9a16-56f83c1b5f49
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1695785049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1695785049
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3381115659
Short name T864
Test name
Test status
Simulation time 660582249 ps
CPU time 1.28 seconds
Started Jul 13 05:52:30 PM PDT 24
Finished Jul 13 05:52:33 PM PDT 24
Peak memory 197096 kb
Host smart-9e718773-0418-402c-8b15-b11b3fed7f57
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381115659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3381115659
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.122760912
Short name T944
Test name
Test status
Simulation time 50539238 ps
CPU time 0.92 seconds
Started Jul 13 05:52:17 PM PDT 24
Finished Jul 13 05:52:21 PM PDT 24
Peak memory 195924 kb
Host smart-7cb73a17-5e75-475a-a381-c0467847f784
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=122760912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.122760912
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1364791002
Short name T918
Test name
Test status
Simulation time 61092092 ps
CPU time 1.29 seconds
Started Jul 13 05:52:16 PM PDT 24
Finished Jul 13 05:52:18 PM PDT 24
Peak memory 198504 kb
Host smart-6f0cca80-5f46-442c-9077-06b66a8a66c4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364791002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1364791002
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1223708931
Short name T885
Test name
Test status
Simulation time 280837397 ps
CPU time 1.27 seconds
Started Jul 13 05:52:39 PM PDT 24
Finished Jul 13 05:52:41 PM PDT 24
Peak memory 196112 kb
Host smart-86c20532-ea70-4c93-a543-f38db63409b6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1223708931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1223708931
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1920667293
Short name T931
Test name
Test status
Simulation time 284840258 ps
CPU time 1.21 seconds
Started Jul 13 05:52:30 PM PDT 24
Finished Jul 13 05:52:33 PM PDT 24
Peak memory 197144 kb
Host smart-50c2e807-f0b3-40f2-b883-7d3266346176
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920667293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1920667293
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3898324348
Short name T848
Test name
Test status
Simulation time 59300605 ps
CPU time 1.13 seconds
Started Jul 13 05:52:39 PM PDT 24
Finished Jul 13 05:52:41 PM PDT 24
Peak memory 197004 kb
Host smart-135f85f5-30d0-4313-9966-8bf8b579b283
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3898324348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3898324348
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4064817340
Short name T850
Test name
Test status
Simulation time 60710091 ps
CPU time 1.26 seconds
Started Jul 13 05:52:30 PM PDT 24
Finished Jul 13 05:52:33 PM PDT 24
Peak memory 197456 kb
Host smart-fc4b6885-cff5-42fd-a638-0812b06dd5fe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064817340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4064817340
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3500209033
Short name T927
Test name
Test status
Simulation time 48518336 ps
CPU time 1.09 seconds
Started Jul 13 05:52:30 PM PDT 24
Finished Jul 13 05:52:33 PM PDT 24
Peak memory 196964 kb
Host smart-fe56b99b-2939-482a-8705-e343702a384c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3500209033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3500209033
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3904917132
Short name T928
Test name
Test status
Simulation time 158234105 ps
CPU time 1.14 seconds
Started Jul 13 05:52:31 PM PDT 24
Finished Jul 13 05:52:34 PM PDT 24
Peak memory 197048 kb
Host smart-173dd07a-5ab3-454d-84d6-098f39e345b5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904917132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3904917132
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2953023519
Short name T856
Test name
Test status
Simulation time 63558447 ps
CPU time 1.08 seconds
Started Jul 13 05:52:30 PM PDT 24
Finished Jul 13 05:52:33 PM PDT 24
Peak memory 197984 kb
Host smart-edbd137f-754c-461f-9235-ed58d34dd730
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2953023519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2953023519
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1812106201
Short name T890
Test name
Test status
Simulation time 179358670 ps
CPU time 1.27 seconds
Started Jul 13 05:52:38 PM PDT 24
Finished Jul 13 05:52:39 PM PDT 24
Peak memory 196412 kb
Host smart-2fe4f0a9-3031-429b-9487-33ae467cd8e7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812106201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1812106201
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2549300710
Short name T854
Test name
Test status
Simulation time 57253076 ps
CPU time 1.15 seconds
Started Jul 13 05:52:30 PM PDT 24
Finished Jul 13 05:52:33 PM PDT 24
Peak memory 198464 kb
Host smart-6162da06-589d-4621-a468-c0ddf11f017a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2549300710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.2549300710
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4067460648
Short name T891
Test name
Test status
Simulation time 110827263 ps
CPU time 1.06 seconds
Started Jul 13 05:52:38 PM PDT 24
Finished Jul 13 05:52:40 PM PDT 24
Peak memory 198396 kb
Host smart-584d3dcb-cc1c-4fe6-9355-75a02b325475
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067460648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4067460648
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1941291746
Short name T857
Test name
Test status
Simulation time 31459995 ps
CPU time 0.82 seconds
Started Jul 13 05:52:37 PM PDT 24
Finished Jul 13 05:52:39 PM PDT 24
Peak memory 195764 kb
Host smart-6e9ece86-56c0-4e79-aa0d-09be804c485b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1941291746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1941291746
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.407756075
Short name T865
Test name
Test status
Simulation time 161871182 ps
CPU time 1.42 seconds
Started Jul 13 05:52:39 PM PDT 24
Finished Jul 13 05:52:41 PM PDT 24
Peak memory 197036 kb
Host smart-1ebafad6-0cec-44ac-84f9-c88cd68aea4e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407756075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.407756075
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.447896864
Short name T908
Test name
Test status
Simulation time 25643450 ps
CPU time 0.72 seconds
Started Jul 13 05:52:38 PM PDT 24
Finished Jul 13 05:52:39 PM PDT 24
Peak memory 193844 kb
Host smart-bcdf9a0b-7d0b-4051-97b7-f39804484df9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=447896864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.447896864
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2953765866
Short name T903
Test name
Test status
Simulation time 42282603 ps
CPU time 1.07 seconds
Started Jul 13 05:52:39 PM PDT 24
Finished Jul 13 05:52:41 PM PDT 24
Peak memory 196976 kb
Host smart-52a2888e-e128-47a9-b9d9-83f46b0bb188
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953765866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2953765866
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1239543144
Short name T894
Test name
Test status
Simulation time 87892118 ps
CPU time 1.37 seconds
Started Jul 13 05:52:31 PM PDT 24
Finished Jul 13 05:52:34 PM PDT 24
Peak memory 196912 kb
Host smart-01e147c2-576e-4a62-a06f-171090f5f56d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1239543144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1239543144
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4130943230
Short name T925
Test name
Test status
Simulation time 287745667 ps
CPU time 1.36 seconds
Started Jul 13 05:52:38 PM PDT 24
Finished Jul 13 05:52:40 PM PDT 24
Peak memory 196068 kb
Host smart-d1dcc4c8-bc52-4e09-96a6-ff40e80eba5b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130943230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4130943230
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.796840094
Short name T907
Test name
Test status
Simulation time 46521456 ps
CPU time 1.07 seconds
Started Jul 13 05:52:29 PM PDT 24
Finished Jul 13 05:52:31 PM PDT 24
Peak memory 197764 kb
Host smart-92d96b0f-e111-4598-bbd0-fd7099d7e7ad
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=796840094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.796840094
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3463187423
Short name T874
Test name
Test status
Simulation time 133980465 ps
CPU time 1.01 seconds
Started Jul 13 05:52:37 PM PDT 24
Finished Jul 13 05:52:39 PM PDT 24
Peak memory 196908 kb
Host smart-395bab50-7bdb-4e45-8d69-ac0727d76525
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463187423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3463187423
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1428424262
Short name T851
Test name
Test status
Simulation time 294423662 ps
CPU time 1.13 seconds
Started Jul 13 05:52:44 PM PDT 24
Finished Jul 13 05:52:45 PM PDT 24
Peak memory 197320 kb
Host smart-f75c1ad2-14ba-4453-8db4-597deae7462e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1428424262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1428424262
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2819342249
Short name T901
Test name
Test status
Simulation time 40532779 ps
CPU time 1.13 seconds
Started Jul 13 05:52:38 PM PDT 24
Finished Jul 13 05:52:40 PM PDT 24
Peak memory 197036 kb
Host smart-9d9b62fa-402b-42b7-b4e7-5370fd31846f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819342249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2819342249
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2296801502
Short name T943
Test name
Test status
Simulation time 588405389 ps
CPU time 1.26 seconds
Started Jul 13 05:52:20 PM PDT 24
Finished Jul 13 05:52:23 PM PDT 24
Peak memory 198432 kb
Host smart-96298833-7a98-4b0e-b6b2-06022df06ed5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2296801502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2296801502
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2698831526
Short name T904
Test name
Test status
Simulation time 355069365 ps
CPU time 1.11 seconds
Started Jul 13 05:52:17 PM PDT 24
Finished Jul 13 05:52:20 PM PDT 24
Peak memory 196920 kb
Host smart-00d99c85-3f7d-4566-b401-cecd5253ba69
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698831526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2698831526
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2444292108
Short name T923
Test name
Test status
Simulation time 124654048 ps
CPU time 1.1 seconds
Started Jul 13 05:52:16 PM PDT 24
Finished Jul 13 05:52:19 PM PDT 24
Peak memory 196092 kb
Host smart-cf907288-1292-4566-9a96-f191198634f5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2444292108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2444292108
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3962677788
Short name T947
Test name
Test status
Simulation time 143172786 ps
CPU time 0.94 seconds
Started Jul 13 05:52:18 PM PDT 24
Finished Jul 13 05:52:21 PM PDT 24
Peak memory 196828 kb
Host smart-2b973586-aa00-4987-9127-09f36550c517
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962677788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3962677788
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2515217849
Short name T937
Test name
Test status
Simulation time 46501412 ps
CPU time 1.12 seconds
Started Jul 13 05:52:16 PM PDT 24
Finished Jul 13 05:52:19 PM PDT 24
Peak memory 196924 kb
Host smart-7b362acf-236e-4b28-9839-00be4f9d470d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2515217849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2515217849
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3094349269
Short name T879
Test name
Test status
Simulation time 126072002 ps
CPU time 1.02 seconds
Started Jul 13 05:52:16 PM PDT 24
Finished Jul 13 05:52:17 PM PDT 24
Peak memory 197080 kb
Host smart-b168c768-15c5-4c3c-b7dc-e2f240552ed7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094349269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3094349269
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.535606442
Short name T902
Test name
Test status
Simulation time 394722346 ps
CPU time 1.1 seconds
Started Jul 13 05:52:16 PM PDT 24
Finished Jul 13 05:52:18 PM PDT 24
Peak memory 197096 kb
Host smart-3c1d6ac2-17f5-4a40-a498-6c68f127c8f8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=535606442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.535606442
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.344311587
Short name T922
Test name
Test status
Simulation time 74191053 ps
CPU time 1.35 seconds
Started Jul 13 05:52:17 PM PDT 24
Finished Jul 13 05:52:20 PM PDT 24
Peak memory 198484 kb
Host smart-e4faff9b-6b08-4ff4-afb9-7cc68d7f0edd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344311587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.344311587
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.4045974981
Short name T914
Test name
Test status
Simulation time 49839736 ps
CPU time 0.89 seconds
Started Jul 13 05:52:18 PM PDT 24
Finished Jul 13 05:52:21 PM PDT 24
Peak memory 197796 kb
Host smart-c3aafee3-7a4b-4332-bda1-a59d5b83ff8f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4045974981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.4045974981
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.581287564
Short name T880
Test name
Test status
Simulation time 70292089 ps
CPU time 1.13 seconds
Started Jul 13 05:52:19 PM PDT 24
Finished Jul 13 05:52:22 PM PDT 24
Peak memory 196884 kb
Host smart-ddf6ba59-5133-4a86-a59d-f359f354a3c3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581287564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.581287564
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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