Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3649320	1			T1	679		T11	1		T12	1
all_pins[1]	3649320	1			T1	679		T11	1		T12	1
all_pins[2]	3649320	1			T1	679		T11	1		T12	1
all_pins[3]	3649320	1			T1	679		T11	1		T12	1
all_pins[4]	3649320	1			T1	679		T11	1		T12	1
all_pins[5]	3649320	1			T1	679		T11	1		T12	1
all_pins[6]	3649320	1			T1	679		T11	1		T12	1
all_pins[7]	3649320	1			T1	679		T11	1		T12	1
all_pins[8]	3649320	1			T1	679		T11	1		T12	1
all_pins[9]	3649320	1			T1	679		T11	1		T12	1
all_pins[10]	3649320	1			T1	679		T11	1		T12	1
all_pins[11]	3649320	1			T1	679		T11	1		T12	1
all_pins[12]	3649320	1			T1	679		T11	1		T12	1
all_pins[13]	3649320	1			T1	679		T11	1		T12	1
all_pins[14]	3649320	1			T1	679		T11	1		T12	1
all_pins[15]	3649320	1			T1	679		T11	1		T12	1
all_pins[16]	3649320	1			T1	679		T11	1		T12	1
all_pins[17]	3649320	1			T1	679		T11	1		T12	1
all_pins[18]	3649320	1			T1	679		T11	1		T12	1
all_pins[19]	3649320	1			T1	679		T11	1		T12	1
all_pins[20]	3649320	1			T1	679		T11	1		T12	1
all_pins[21]	3649320	1			T1	679		T11	1		T12	1
all_pins[22]	3649320	1			T1	679		T11	1		T12	1
all_pins[23]	3649320	1			T1	679		T11	1		T12	1
all_pins[24]	3649320	1			T1	679		T11	1		T12	1
all_pins[25]	3649320	1			T1	679		T11	1		T12	1
all_pins[26]	3649320	1			T1	679		T11	1		T12	1
all_pins[27]	3649320	1			T1	679		T11	1		T12	1
all_pins[28]	3649320	1			T1	679		T11	1		T12	1
all_pins[29]	3649320	1			T1	679		T11	1		T12	1
all_pins[30]	3649320	1			T1	679		T11	1		T12	1
all_pins[31]	3649320	1			T1	679		T11	1		T12	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	72582895	1			T1	13199		T11	32		T12	32
values[0x1]	44195345	1			T1	8529		T13	903		T15	9
transitions[0x0=>0x1]	26495820	1			T1	4986		T13	576		T15	7
transitions[0x1=>0x0]	26495656	1			T1	4986		T13	575		T15	7

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2271429	1			T1	400		T11	1		T12	1
all_pins[0]	values[0x1]	1377891	1			T1	279		T13	33		T16	12
all_pins[0]	transitions[0x0=>0x1]	854545	1			T1	188		T13	17		T16	5
all_pins[0]	transitions[0x1=>0x0]	858670	1			T1	177		T13	15		T15	1
all_pins[1]	values[0x0]	2268308	1			T1	435		T11	1		T12	1
all_pins[1]	values[0x1]	1381012	1			T1	244		T13	18		T16	23
all_pins[1]	transitions[0x0=>0x1]	825315	1			T1	147		T13	15		T16	17
all_pins[1]	transitions[0x1=>0x0]	822194	1			T1	182		T13	30		T16	6
all_pins[2]	values[0x0]	2270493	1			T1	388		T11	1		T12	1
all_pins[2]	values[0x1]	1378827	1			T1	291		T13	30		T16	27
all_pins[2]	transitions[0x0=>0x1]	827358	1			T1	153		T13	23		T16	12
all_pins[2]	transitions[0x1=>0x0]	829543	1			T1	106		T13	11		T16	8
all_pins[3]	values[0x0]	2265528	1			T1	456		T11	1		T12	1
all_pins[3]	values[0x1]	1383792	1			T1	223		T13	53		T15	1
all_pins[3]	transitions[0x0=>0x1]	829702	1			T1	113		T13	32		T15	1
all_pins[3]	transitions[0x1=>0x0]	824737	1			T1	181		T13	9		T16	20
all_pins[4]	values[0x0]	2271591	1			T1	405		T11	1		T12	1
all_pins[4]	values[0x1]	1377729	1			T1	274		T13	29		T16	22
all_pins[4]	transitions[0x0=>0x1]	826177	1			T1	174		T13	11		T16	11
all_pins[4]	transitions[0x1=>0x0]	832240	1			T1	123		T13	35		T15	1
all_pins[5]	values[0x0]	2265545	1			T1	395		T11	1		T12	1
all_pins[5]	values[0x1]	1383775	1			T1	284		T13	30		T16	20
all_pins[5]	transitions[0x0=>0x1]	827939	1			T1	152		T13	11		T16	10
all_pins[5]	transitions[0x1=>0x0]	821893	1			T1	142		T13	10		T16	12
all_pins[6]	values[0x0]	2268113	1			T1	441		T11	1		T12	1
all_pins[6]	values[0x1]	1381207	1			T1	238		T13	16		T16	12
all_pins[6]	transitions[0x0=>0x1]	826165	1			T1	131		T13	15		T16	6
all_pins[6]	transitions[0x1=>0x0]	828733	1			T1	177		T13	29		T16	14
all_pins[7]	values[0x0]	2263259	1			T1	374		T11	1		T12	1
all_pins[7]	values[0x1]	1386061	1			T1	305		T13	26		T15	1
all_pins[7]	transitions[0x0=>0x1]	829233	1			T1	198		T13	20		T15	1
all_pins[7]	transitions[0x1=>0x0]	824379	1			T1	131		T13	10		T16	6
all_pins[8]	values[0x0]	2267073	1			T1	400		T11	1		T12	1
all_pins[8]	values[0x1]	1382247	1			T1	279		T13	13		T16	22
all_pins[8]	transitions[0x0=>0x1]	827079	1			T1	153		T13	11		T16	9
all_pins[8]	transitions[0x1=>0x0]	830893	1			T1	179		T13	24		T15	1
all_pins[9]	values[0x0]	2263784	1			T1	349		T11	1		T12	1
all_pins[9]	values[0x1]	1385536	1			T1	330		T13	34		T16	20
all_pins[9]	transitions[0x0=>0x1]	831481	1			T1	181		T13	30		T16	16
all_pins[9]	transitions[0x1=>0x0]	828192	1			T1	130		T13	9		T16	18
all_pins[10]	values[0x0]	2269768	1			T1	419		T11	1		T12	1
all_pins[10]	values[0x1]	1379552	1			T1	260		T13	26		T16	26
all_pins[10]	transitions[0x0=>0x1]	823628	1			T1	151		T13	15		T16	19
all_pins[10]	transitions[0x1=>0x0]	829612	1			T1	221		T13	23		T16	13
all_pins[11]	values[0x0]	2270000	1			T1	418		T11	1		T12	1
all_pins[11]	values[0x1]	1379320	1			T1	261		T13	14		T16	27
all_pins[11]	transitions[0x0=>0x1]	826847	1			T1	160		T13	4		T16	11
all_pins[11]	transitions[0x1=>0x0]	827079	1			T1	159		T13	16		T16	10
all_pins[12]	values[0x0]	2264848	1			T1	397		T11	1		T12	1
all_pins[12]	values[0x1]	1384472	1			T1	282		T13	25		T16	23
all_pins[12]	transitions[0x0=>0x1]	829379	1			T1	157		T13	18		T16	11
all_pins[12]	transitions[0x1=>0x0]	824227	1			T1	136		T13	7		T16	15
all_pins[13]	values[0x0]	2272573	1			T1	353		T11	1		T12	1
all_pins[13]	values[0x1]	1376747	1			T1	326		T13	46		T15	1
all_pins[13]	transitions[0x0=>0x1]	824296	1			T1	161		T13	27		T15	1
all_pins[13]	transitions[0x1=>0x0]	832021	1			T1	117		T13	6		T16	10
all_pins[14]	values[0x0]	2270175	1			T1	469		T11	1		T12	1
all_pins[14]	values[0x1]	1379145	1			T1	210		T13	9		T15	1
all_pins[14]	transitions[0x0=>0x1]	827307	1			T1	96		T13	5		T16	13
all_pins[14]	transitions[0x1=>0x0]	824909	1			T1	212		T13	42		T16	10
all_pins[15]	values[0x0]	2266849	1			T1	393		T11	1		T12	1
all_pins[15]	values[0x1]	1382471	1			T1	286		T13	33		T16	21
all_pins[15]	transitions[0x0=>0x1]	828576	1			T1	207		T13	29		T16	11
all_pins[15]	transitions[0x1=>0x0]	825250	1			T1	131		T13	5		T15	1
all_pins[16]	values[0x0]	2264414	1			T1	371		T11	1		T12	1
all_pins[16]	values[0x1]	1384906	1			T1	308		T13	35		T16	21
all_pins[16]	transitions[0x0=>0x1]	829103	1			T1	157		T13	18		T16	10
all_pins[16]	transitions[0x1=>0x0]	826668	1			T1	135		T13	16		T16	10
all_pins[17]	values[0x0]	2272372	1			T1	386		T11	1		T12	1
all_pins[17]	values[0x1]	1376948	1			T1	293		T13	31		T16	26
all_pins[17]	transitions[0x0=>0x1]	824447	1			T1	155		T13	12		T16	15
all_pins[17]	transitions[0x1=>0x0]	832405	1			T1	170		T13	16		T16	10
all_pins[18]	values[0x0]	2265799	1			T1	400		T11	1		T12	1
all_pins[18]	values[0x1]	1383521	1			T1	279		T13	29		T15	1
all_pins[18]	transitions[0x0=>0x1]	830488	1			T1	156		T13	13		T15	1
all_pins[18]	transitions[0x1=>0x0]	823915	1			T1	170		T13	15		T16	13
all_pins[19]	values[0x0]	2271678	1			T1	407		T11	1		T12	1
all_pins[19]	values[0x1]	1377642	1			T1	272		T13	26		T16	20
all_pins[19]	transitions[0x0=>0x1]	822602	1			T1	163		T13	24		T16	16
all_pins[19]	transitions[0x1=>0x0]	828481	1			T1	170		T13	27		T15	1
all_pins[20]	values[0x0]	2260924	1			T1	421		T11	1		T12	1
all_pins[20]	values[0x1]	1388396	1			T1	258		T13	53		T16	15
all_pins[20]	transitions[0x0=>0x1]	833866	1			T1	154		T13	37		T16	5
all_pins[20]	transitions[0x1=>0x0]	823112	1			T1	168		T13	10		T16	10
all_pins[21]	values[0x0]	2265786	1			T1	433		T11	1		T12	1
all_pins[21]	values[0x1]	1383534	1			T1	246		T13	35		T16	18
all_pins[21]	transitions[0x0=>0x1]	826647	1			T1	146		T13	11		T16	9
all_pins[21]	transitions[0x1=>0x0]	831509	1			T1	158		T13	29		T16	6
all_pins[22]	values[0x0]	2266819	1			T1	426		T11	1		T12	1
all_pins[22]	values[0x1]	1382501	1			T1	253		T13	12		T16	21
all_pins[22]	transitions[0x0=>0x1]	828601	1			T1	134		T13	10		T16	12
all_pins[22]	transitions[0x1=>0x0]	829634	1			T1	127		T13	33		T16	9
all_pins[23]	values[0x0]	2269607	1			T1	438		T11	1		T12	1
all_pins[23]	values[0x1]	1379713	1			T1	241		T13	32		T15	1
all_pins[23]	transitions[0x0=>0x1]	825271	1			T1	141		T13	30		T15	1
all_pins[23]	transitions[0x1=>0x0]	828059	1			T1	153		T13	10		T16	14
all_pins[24]	values[0x0]	2268660	1			T1	436		T11	1		T12	1
all_pins[24]	values[0x1]	1380660	1			T1	243		T13	4		T16	14
all_pins[24]	transitions[0x0=>0x1]	826716	1			T1	150		T13	3		T16	8
all_pins[24]	transitions[0x1=>0x0]	825769	1			T1	148		T13	31		T15	1
all_pins[25]	values[0x0]	2270415	1			T1	468		T11	1		T12	1
all_pins[25]	values[0x1]	1378905	1			T1	211		T13	27		T16	23
all_pins[25]	transitions[0x0=>0x1]	826408	1			T1	110		T13	25		T16	12
all_pins[25]	transitions[0x1=>0x0]	828163	1			T1	142		T13	2		T16	3
all_pins[26]	values[0x0]	2269774	1			T1	430		T11	1		T12	1
all_pins[26]	values[0x1]	1379546	1			T1	249		T13	24		T16	13
all_pins[26]	transitions[0x0=>0x1]	826075	1			T1	176		T13	6		T16	3
all_pins[26]	transitions[0x1=>0x0]	825434	1			T1	138		T13	9		T16	13
all_pins[27]	values[0x0]	2270160	1			T1	398		T11	1		T12	1
all_pins[27]	values[0x1]	1379160	1			T1	281		T13	53		T15	1
all_pins[27]	transitions[0x0=>0x1]	825914	1			T1	173		T13	40		T15	1
all_pins[27]	transitions[0x1=>0x0]	826300	1			T1	141		T13	11		T16	8
all_pins[28]	values[0x0]	2265760	1			T1	432		T11	1		T12	1
all_pins[28]	values[0x1]	1383560	1			T1	247		T13	25		T16	25
all_pins[28]	transitions[0x0=>0x1]	828145	1			T1	146		T13	4		T16	14
all_pins[28]	transitions[0x1=>0x0]	823745	1			T1	180		T13	32		T15	1
all_pins[29]	values[0x0]	2273363	1			T1	402		T11	1		T12	1
all_pins[29]	values[0x1]	1375957	1			T1	277		T13	24		T16	17
all_pins[29]	transitions[0x0=>0x1]	822370	1			T1	185		T13	24		T16	3
all_pins[29]	transitions[0x1=>0x0]	829973	1			T1	155		T13	25		T16	11
all_pins[30]	values[0x0]	2270888	1			T1	448		T11	1		T12	1
all_pins[30]	values[0x1]	1378432	1			T1	231		T13	26		T15	1
all_pins[30]	transitions[0x0=>0x1]	825079	1			T1	143		T13	15		T15	1
all_pins[30]	transitions[0x1=>0x0]	822604	1			T1	189		T13	13		T16	11
all_pins[31]	values[0x0]	2267140	1			T1	411		T11	1		T12	1
all_pins[31]	values[0x1]	1382180	1			T1	268		T13	32		T15	1
all_pins[31]	transitions[0x0=>0x1]	829061	1			T1	175		T13	21		T16	9
all_pins[31]	transitions[0x1=>0x0]	825313	1			T1	138		T13	15		T16	10