Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	12522203	1			T1	1935		T11	44		T12	31
all_values[1]	12522203	1			T1	1935		T11	44		T12	31
all_values[2]	12522203	1			T1	1935		T11	44		T12	31
all_values[3]	12522203	1			T1	1935		T11	44		T12	31
all_values[4]	12522203	1			T1	1935		T11	44		T12	31
all_values[5]	12522203	1			T1	1935		T11	44		T12	31
all_values[6]	12522203	1			T1	1935		T11	44		T12	31
all_values[7]	12522203	1			T1	1935		T11	44		T12	31
all_values[8]	12522203	1			T1	1935		T11	44		T12	31
all_values[9]	12522203	1			T1	1935		T11	44		T12	31
all_values[10]	12522203	1			T1	1935		T11	44		T12	31
all_values[11]	12522203	1			T1	1935		T11	44		T12	31
all_values[12]	12522203	1			T1	1935		T11	44		T12	31
all_values[13]	12522203	1			T1	1935		T11	44		T12	31
all_values[14]	12522203	1			T1	1935		T11	44		T12	31
all_values[15]	12522203	1			T1	1935		T11	44		T12	31
all_values[16]	12522203	1			T1	1935		T11	44		T12	31
all_values[17]	12522203	1			T1	1935		T11	44		T12	31
all_values[18]	12522203	1			T1	1935		T11	44		T12	31
all_values[19]	12522203	1			T1	1935		T11	44		T12	31
all_values[20]	12522203	1			T1	1935		T11	44		T12	31
all_values[21]	12522203	1			T1	1935		T11	44		T12	31
all_values[22]	12522203	1			T1	1935		T11	44		T12	31
all_values[23]	12522203	1			T1	1935		T11	44		T12	31
all_values[24]	12522203	1			T1	1935		T11	44		T12	31
all_values[25]	12522203	1			T1	1935		T11	44		T12	31
all_values[26]	12522203	1			T1	1935		T11	44		T12	31
all_values[27]	12522203	1			T1	1935		T11	44		T12	31
all_values[28]	12522203	1			T1	1935		T11	44		T12	31
all_values[29]	12522203	1			T1	1935		T11	44		T12	31
all_values[30]	12522203	1			T1	1935		T11	44		T12	31
all_values[31]	12522203	1			T1	1935		T11	44		T12	31

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

236209980

1

T1

30605

T11

1408

T12

992

auto[1]

164500516

1

T1

31315

T13

3012

T15

51

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102925714

1

T1

6944

T11

1408

T12

992

auto[1]

297784782

1

T1

54976

T13

5476

T15

30

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

396415623

1

T1

59410

T11

1408

T12

992

auto[1]

4294873

1

T1

2510

T13

204

T15

12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2714929	1			T1	70		T11	44		T12	31
all_values[0]	auto[0]	auto[0]	auto[1]	4638833	1			T1	835		T13	86		T19	10378
all_values[0]	auto[0]	auto[1]	auto[0]	491415	1			T1	138		T13	11		T15	3
all_values[0]	auto[0]	auto[1]	auto[1]	4542703	1			T1	812		T13	90		T19	12047
all_values[0]	auto[1]	auto[0]	auto[1]	67822	1			T1	33		T13	3		T19	148
all_values[0]	auto[1]	auto[1]	auto[1]	66501	1			T1	47		T13	2		T19	139
all_values[1]	auto[0]	auto[0]	auto[0]	2716011	1			T1	124		T11	44		T12	31
all_values[1]	auto[0]	auto[0]	auto[1]	4561818	1			T1	919		T13	110		T15	2
all_values[1]	auto[0]	auto[1]	auto[0]	499561	1			T1	101		T13	10		T19	1360
all_values[1]	auto[0]	auto[1]	auto[1]	4610148	1			T1	725		T13	46		T19	11287
all_values[1]	auto[1]	auto[0]	auto[1]	67263	1			T1	30		T13	3		T19	141
all_values[1]	auto[1]	auto[1]	auto[1]	67402	1			T1	36		T13	1		T19	125
all_values[2]	auto[0]	auto[0]	auto[0]	2723606	1			T1	74		T11	44		T12	31
all_values[2]	auto[0]	auto[0]	auto[1]	4586539	1			T1	705		T13	68		T19	11269
all_values[2]	auto[0]	auto[1]	auto[0]	505058	1			T1	133		T13	24		T15	3
all_values[2]	auto[0]	auto[1]	auto[1]	4572485	1			T1	943		T13	97		T19	11173
all_values[2]	auto[1]	auto[0]	auto[1]	67384	1			T1	38		T13	3		T19	143
all_values[2]	auto[1]	auto[1]	auto[1]	67131	1			T1	42		T13	3		T19	129
all_values[3]	auto[0]	auto[0]	auto[0]	2722268	1			T1	139		T11	44		T12	31
all_values[3]	auto[0]	auto[0]	auto[1]	4588150	1			T1	846		T13	44		T19	10629
all_values[3]	auto[0]	auto[1]	auto[0]	504007	1			T1	139		T13	10		T15	2
all_values[3]	auto[0]	auto[1]	auto[1]	4573604	1			T1	737		T13	136		T19	11790
all_values[3]	auto[1]	auto[0]	auto[1]	67308	1			T1	40		T19	149		T106	27
all_values[3]	auto[1]	auto[1]	auto[1]	66866	1			T1	34		T13	4		T15	1
all_values[4]	auto[0]	auto[0]	auto[0]	2720943	1			T1	113		T11	44		T12	31
all_values[4]	auto[0]	auto[0]	auto[1]	4596459	1			T1	715		T13	44		T19	11259
all_values[4]	auto[0]	auto[1]	auto[0]	505715	1			T1	111		T13	40		T19	907
all_values[4]	auto[0]	auto[1]	auto[1]	4564917	1			T1	918		T13	92		T19	11378
all_values[4]	auto[1]	auto[0]	auto[1]	67646	1			T1	37		T13	3		T19	127
all_values[4]	auto[1]	auto[1]	auto[1]	66523	1			T1	41		T13	5		T19	156
all_values[5]	auto[0]	auto[0]	auto[0]	2718595	1			T1	131		T11	44		T12	31
all_values[5]	auto[0]	auto[0]	auto[1]	4595359	1			T1	728		T13	86		T15	1
all_values[5]	auto[0]	auto[1]	auto[0]	499534	1			T1	97		T13	17		T15	3
all_values[5]	auto[0]	auto[1]	auto[1]	4574199	1			T1	897		T13	68		T19	11195
all_values[5]	auto[1]	auto[0]	auto[1]	67748	1			T1	40		T13	6		T19	134
all_values[5]	auto[1]	auto[1]	auto[1]	66768	1			T1	42		T13	1		T19	140
all_values[6]	auto[0]	auto[0]	auto[0]	2715243	1			T1	70		T11	44		T12	31
all_values[6]	auto[0]	auto[0]	auto[1]	4579512	1			T1	864		T13	116		T19	12563
all_values[6]	auto[0]	auto[1]	auto[0]	504437	1			T1	162		T13	1		T19	1030
all_values[6]	auto[0]	auto[1]	auto[1]	4588790	1			T1	758		T13	72		T19	9986
all_values[6]	auto[1]	auto[0]	auto[1]	67622	1			T1	37		T13	3		T19	155
all_values[6]	auto[1]	auto[1]	auto[1]	66599	1			T1	44		T13	3		T19	129
all_values[7]	auto[0]	auto[0]	auto[0]	2713229	1			T1	78		T11	44		T12	31
all_values[7]	auto[0]	auto[0]	auto[1]	4589138	1			T1	734		T13	107		T19	10491
all_values[7]	auto[0]	auto[1]	auto[0]	503808	1			T1	92		T13	8		T15	2
all_values[7]	auto[0]	auto[1]	auto[1]	4582539	1			T1	953		T13	64		T19	11645
all_values[7]	auto[1]	auto[0]	auto[1]	67186	1			T1	30		T13	4		T19	145
all_values[7]	auto[1]	auto[1]	auto[1]	66303	1			T1	48		T13	2		T15	1
all_values[8]	auto[0]	auto[0]	auto[0]	2718748	1			T1	114		T11	44		T12	31
all_values[8]	auto[0]	auto[0]	auto[1]	4619591	1			T1	746		T13	95		T19	10973
all_values[8]	auto[0]	auto[1]	auto[0]	500163	1			T1	83		T13	9		T19	1399
all_values[8]	auto[0]	auto[1]	auto[1]	4549390	1			T1	912		T13	58		T19	11214
all_values[8]	auto[1]	auto[0]	auto[1]	67204	1			T1	37		T13	6		T19	148
all_values[8]	auto[1]	auto[1]	auto[1]	67107	1			T1	43		T13	3		T19	140
all_values[9]	auto[0]	auto[0]	auto[0]	2716601	1			T1	59		T11	44		T12	31
all_values[9]	auto[0]	auto[0]	auto[1]	4595253	1			T1	715		T13	92		T15	1
all_values[9]	auto[0]	auto[1]	auto[0]	502183	1			T1	84		T19	1401		T105	78
all_values[9]	auto[0]	auto[1]	auto[1]	4574247	1			T1	1005		T13	98		T19	11020
all_values[9]	auto[1]	auto[0]	auto[1]	67131	1			T1	37		T13	1		T19	142
all_values[9]	auto[1]	auto[1]	auto[1]	66788	1			T1	35		T13	4		T19	132
all_values[10]	auto[0]	auto[0]	auto[0]	2718306	1			T1	120		T11	44		T12	31
all_values[10]	auto[0]	auto[0]	auto[1]	4615765	1			T1	840		T13	101		T15	2
all_values[10]	auto[0]	auto[1]	auto[0]	502453	1			T1	53		T13	8		T19	1078
all_values[10]	auto[0]	auto[1]	auto[1]	4551070	1			T1	839		T13	75		T19	11374
all_values[10]	auto[1]	auto[0]	auto[1]	67475	1			T1	43		T13	4		T19	137
all_values[10]	auto[1]	auto[1]	auto[1]	67134	1			T1	40		T13	1		T19	140
all_values[11]	auto[0]	auto[0]	auto[0]	2716061	1			T1	138		T11	44		T12	31
all_values[11]	auto[0]	auto[0]	auto[1]	4634653	1			T1	832		T13	140		T15	1
all_values[11]	auto[0]	auto[1]	auto[0]	498968	1			T1	78		T13	3		T19	1151
all_values[11]	auto[0]	auto[1]	auto[1]	4538128	1			T1	812		T13	34		T19	10959
all_values[11]	auto[1]	auto[0]	auto[1]	67552	1			T1	46		T13	7		T19	143
all_values[11]	auto[1]	auto[1]	auto[1]	66841	1			T1	29		T13	1		T19	136
all_values[12]	auto[0]	auto[0]	auto[0]	2712149	1			T1	92		T11	44		T12	31
all_values[12]	auto[0]	auto[0]	auto[1]	4565737	1			T1	756		T13	83		T19	10699
all_values[12]	auto[0]	auto[1]	auto[0]	505354	1			T1	159		T13	14		T15	3
all_values[12]	auto[0]	auto[1]	auto[1]	4604838	1			T1	849		T13	75		T19	11846
all_values[12]	auto[1]	auto[0]	auto[1]	66852	1			T1	34		T13	5		T19	111
all_values[12]	auto[1]	auto[1]	auto[1]	67273	1			T1	45		T13	3		T19	143
all_values[13]	auto[0]	auto[0]	auto[0]	2729368	1			T1	72		T11	44		T12	31
all_values[13]	auto[0]	auto[0]	auto[1]	4629202	1			T1	775		T13	34		T19	10294
all_values[13]	auto[0]	auto[1]	auto[0]	496965	1			T1	80		T13	6		T15	2
all_values[13]	auto[0]	auto[1]	auto[1]	4532307	1			T1	924		T13	124		T19	12266
all_values[13]	auto[1]	auto[0]	auto[1]	67407	1			T1	48		T13	3		T19	140
all_values[13]	auto[1]	auto[1]	auto[1]	66954	1			T1	36		T13	5		T15	1
all_values[14]	auto[0]	auto[0]	auto[0]	2717512	1			T1	64		T11	44		T12	31
all_values[14]	auto[0]	auto[0]	auto[1]	4609311	1			T1	1046		T13	125		T15	1
all_values[14]	auto[0]	auto[1]	auto[0]	501775	1			T1	120		T13	12		T15	2
all_values[14]	auto[0]	auto[1]	auto[1]	4559915	1			T1	626		T13	24		T19	11748
all_values[14]	auto[1]	auto[0]	auto[1]	67298	1			T1	49		T13	6		T19	108
all_values[14]	auto[1]	auto[1]	auto[1]	66392	1			T1	30		T13	1		T15	1
all_values[15]	auto[0]	auto[0]	auto[0]	2714805	1			T1	76		T11	44		T12	31
all_values[15]	auto[0]	auto[0]	auto[1]	4564213	1			T1	779		T13	62		T19	10978
all_values[15]	auto[0]	auto[1]	auto[0]	496234	1			T1	90		T13	3		T19	1073
all_values[15]	auto[0]	auto[1]	auto[1]	4612733	1			T1	901		T13	115		T19	11706
all_values[15]	auto[1]	auto[0]	auto[1]	67469	1			T1	38		T13	3		T15	1
all_values[15]	auto[1]	auto[1]	auto[1]	66749	1			T1	51		T13	7		T19	135
all_values[16]	auto[0]	auto[0]	auto[0]	2718767	1			T1	85		T11	44		T12	31
all_values[16]	auto[0]	auto[0]	auto[1]	4597784	1			T1	771		T13	95		T19	12285
all_values[16]	auto[0]	auto[1]	auto[0]	495333	1			T1	70		T13	2		T15	3
all_values[16]	auto[0]	auto[1]	auto[1]	4576474	1			T1	932		T13	76		T19	10026
all_values[16]	auto[1]	auto[0]	auto[1]	67050	1			T1	32		T13	6		T19	137
all_values[16]	auto[1]	auto[1]	auto[1]	66795	1			T1	45		T19	126		T106	35
all_values[17]	auto[0]	auto[0]	auto[0]	2708231	1			T1	112		T11	44		T12	31
all_values[17]	auto[0]	auto[0]	auto[1]	4618286	1			T1	781		T13	99		T15	2
all_values[17]	auto[0]	auto[1]	auto[0]	501500	1			T1	91		T13	5		T19	1176
all_values[17]	auto[0]	auto[1]	auto[1]	4559726	1			T1	864		T13	82		T19	11578
all_values[17]	auto[1]	auto[0]	auto[1]	67650	1			T1	41		T13	1		T15	1
all_values[17]	auto[1]	auto[1]	auto[1]	66810	1			T1	46		T13	2		T19	118
all_values[18]	auto[0]	auto[0]	auto[0]	2712829	1			T1	159		T11	44		T12	31
all_values[18]	auto[0]	auto[0]	auto[1]	4561705	1			T1	742		T13	110		T19	10679
all_values[18]	auto[0]	auto[1]	auto[0]	502233	1			T1	82		T13	11		T15	2
all_values[18]	auto[0]	auto[1]	auto[1]	4610838	1			T1	876		T13	58		T19	11703
all_values[18]	auto[1]	auto[0]	auto[1]	67259	1			T1	39		T13	7		T19	142
all_values[18]	auto[1]	auto[1]	auto[1]	67339	1			T1	37		T13	1		T15	1
all_values[19]	auto[0]	auto[0]	auto[0]	2716004	1			T1	110		T11	44		T12	31
all_values[19]	auto[0]	auto[0]	auto[1]	4612752	1			T1	929		T13	69		T19	11069
all_values[19]	auto[0]	auto[1]	auto[0]	504148	1			T1	59		T13	29		T19	1310
all_values[19]	auto[0]	auto[1]	auto[1]	4555378	1			T1	746		T13	71		T19	11176
all_values[19]	auto[1]	auto[0]	auto[1]	67381	1			T1	43		T13	5		T19	123
all_values[19]	auto[1]	auto[1]	auto[1]	66540	1			T1	48		T13	2		T19	146
all_values[20]	auto[0]	auto[0]	auto[0]	2707940	1			T1	97		T11	44		T12	31
all_values[20]	auto[0]	auto[0]	auto[1]	4574970	1			T1	797		T13	81		T19	10959
all_values[20]	auto[0]	auto[1]	auto[0]	499122	1			T1	107		T15	3		T19	1154
all_values[20]	auto[0]	auto[1]	auto[1]	4606181	1			T1	862		T13	108		T19	11523
all_values[20]	auto[1]	auto[0]	auto[1]	66693	1			T1	34		T13	4		T19	168
all_values[20]	auto[1]	auto[1]	auto[1]	67297	1			T1	38		T13	5		T19	126
all_values[21]	auto[0]	auto[0]	auto[0]	2712812	1			T1	112		T11	44		T12	31
all_values[21]	auto[0]	auto[0]	auto[1]	4590894	1			T1	811		T13	78		T15	2
all_values[21]	auto[0]	auto[1]	auto[0]	496850	1			T1	142		T13	31		T15	3
all_values[21]	auto[0]	auto[1]	auto[1]	4587615	1			T1	781		T13	81		T19	10911
all_values[21]	auto[1]	auto[0]	auto[1]	66948	1			T1	41		T13	3		T19	118
all_values[21]	auto[1]	auto[1]	auto[1]	67084	1			T1	48		T13	5		T19	155
all_values[22]	auto[0]	auto[0]	auto[0]	2716750	1			T1	135		T11	44		T12	31
all_values[22]	auto[0]	auto[0]	auto[1]	4594957	1			T1	716		T13	135		T15	2
all_values[22]	auto[0]	auto[1]	auto[0]	489539	1			T1	185		T13	7		T19	963
all_values[22]	auto[0]	auto[1]	auto[1]	4586444	1			T1	826		T13	39		T19	10530
all_values[22]	auto[1]	auto[0]	auto[1]	67730	1			T1	31		T13	6		T19	140
all_values[22]	auto[1]	auto[1]	auto[1]	66783	1			T1	42		T13	1		T19	139
all_values[23]	auto[0]	auto[0]	auto[0]	2719357	1			T1	141		T11	44		T12	31
all_values[23]	auto[0]	auto[0]	auto[1]	4594785	1			T1	833		T13	65		T19	10798
all_values[23]	auto[0]	auto[1]	auto[0]	498776	1			T1	82		T13	29		T15	2
all_values[23]	auto[0]	auto[1]	auto[1]	4574797	1			T1	796		T13	86		T19	11580
all_values[23]	auto[1]	auto[0]	auto[1]	67971	1			T1	51		T13	3		T19	159
all_values[23]	auto[1]	auto[1]	auto[1]	66517	1			T1	32		T13	3		T15	1
all_values[24]	auto[0]	auto[0]	auto[0]	2713543	1			T1	139		T11	44		T12	31
all_values[24]	auto[0]	auto[0]	auto[1]	4576857	1			T1	806		T13	118		T19	10785
all_values[24]	auto[0]	auto[1]	auto[0]	500152	1			T1	91		T13	17		T15	3
all_values[24]	auto[0]	auto[1]	auto[1]	4597587	1			T1	820		T13	22		T19	11703
all_values[24]	auto[1]	auto[0]	auto[1]	67604	1			T1	33		T13	3		T19	130
all_values[24]	auto[1]	auto[1]	auto[1]	66460	1			T1	46		T19	144		T106	37
all_values[25]	auto[0]	auto[0]	auto[0]	2711909	1			T1	176		T11	44		T12	31
all_values[25]	auto[0]	auto[0]	auto[1]	4609030	1			T1	893		T13	65		T15	1
all_values[25]	auto[0]	auto[1]	auto[0]	501903	1			T1	91		T13	30		T19	1106
all_values[25]	auto[0]	auto[1]	auto[1]	4565408	1			T1	698		T13	98		T19	11577
all_values[25]	auto[1]	auto[0]	auto[1]	67218	1			T1	47		T13	2		T15	1
all_values[25]	auto[1]	auto[1]	auto[1]	66735	1			T1	30		T13	3		T19	125
all_values[26]	auto[0]	auto[0]	auto[0]	2717424	1			T1	81		T11	44		T12	31
all_values[26]	auto[0]	auto[0]	auto[1]	4593651	1			T1	916		T13	61		T15	1
all_values[26]	auto[0]	auto[1]	auto[0]	492273	1			T1	94		T13	34		T19	1422
all_values[26]	auto[0]	auto[1]	auto[1]	4584710	1			T1	766		T13	93		T19	11777
all_values[26]	auto[1]	auto[0]	auto[1]	67531	1			T1	42		T13	2		T19	158
all_values[26]	auto[1]	auto[1]	auto[1]	66614	1			T1	36		T13	2		T19	118
all_values[27]	auto[0]	auto[0]	auto[0]	2712671	1			T1	118		T11	44		T12	31
all_values[27]	auto[0]	auto[0]	auto[1]	4616746	1			T1	723		T13	54		T19	10939
all_values[27]	auto[0]	auto[1]	auto[0]	501370	1			T1	132		T13	9		T15	2
all_values[27]	auto[0]	auto[1]	auto[1]	4556911	1			T1	887		T13	121		T19	11564
all_values[27]	auto[1]	auto[0]	auto[1]	67684	1			T1	36		T13	3		T19	130
all_values[27]	auto[1]	auto[1]	auto[1]	66821	1			T1	39		T13	6		T15	1
all_values[28]	auto[0]	auto[0]	auto[0]	2716639	1			T1	124		T11	44		T12	31
all_values[28]	auto[0]	auto[0]	auto[1]	4604920	1			T1	791		T13	123		T19	11351
all_values[28]	auto[0]	auto[1]	auto[0]	504320	1			T1	116		T13	4		T19	1091
all_values[28]	auto[0]	auto[1]	auto[1]	4561841	1			T1	832		T13	37		T19	10982
all_values[28]	auto[1]	auto[0]	auto[1]	67488	1			T1	41		T13	3		T19	153
all_values[28]	auto[1]	auto[1]	auto[1]	66995	1			T1	31		T13	2		T19	114
all_values[29]	auto[0]	auto[0]	auto[0]	2726867	1			T1	115		T11	44		T12	31
all_values[29]	auto[0]	auto[0]	auto[1]	4595678	1			T1	844		T13	103		T19	11689
all_values[29]	auto[0]	auto[1]	auto[0]	502390	1			T1	76		T13	16		T19	1098
all_values[29]	auto[0]	auto[1]	auto[1]	4563214	1			T1	822		T13	70		T19	10733
all_values[29]	auto[1]	auto[0]	auto[1]	67328	1			T1	39		T13	4		T19	131
all_values[29]	auto[1]	auto[1]	auto[1]	66726	1			T1	39		T13	2		T19	134
all_values[30]	auto[0]	auto[0]	auto[0]	2708656	1			T1	116		T11	44		T12	31
all_values[30]	auto[0]	auto[0]	auto[1]	4597252	1			T1	987		T13	124		T19	11641
all_values[30]	auto[0]	auto[1]	auto[0]	502478	1			T1	110		T13	9		T15	2
all_values[30]	auto[0]	auto[1]	auto[1]	4579842	1			T1	650		T13	57		T19	10904
all_values[30]	auto[1]	auto[0]	auto[1]	67294	1			T1	44		T13	7		T19	150
all_values[30]	auto[1]	auto[1]	auto[1]	66681	1			T1	28		T13	1		T15	1
all_values[31]	auto[0]	auto[0]	auto[0]	2713088	1			T1	139		T11	44		T12	31
all_values[31]	auto[0]	auto[0]	auto[1]	4621537	1			T1	695		T13	25		T15	2
all_values[31]	auto[0]	auto[1]	auto[0]	493836	1			T1	203		T13	45		T15	2
all_values[31]	auto[0]	auto[1]	auto[1]	4559593	1			T1	827		T13	107		T19	11090
all_values[31]	auto[1]	auto[0]	auto[1]	67586	1			T1	31		T13	1		T19	111
all_values[31]	auto[1]	auto[1]	auto[1]	66563	1			T1	40		T13	3		T15	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal