Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[1]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[2]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[3]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[4]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[5]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[6]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[7]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[8]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[9]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[10]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[11]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[12]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[13]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[14]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[15]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[16]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[17]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[18]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[19]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[20]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[21]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[22]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[23]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[24]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[25]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[26]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[27]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[28]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[29]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[30]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[31]	12356718	1			T1	1829		T11	78		T12	60

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

235428940

1

T1

45119

T11

745

T12

1612

auto[1]

159986036

1

T1

13409

T11

1751

T12

308

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

318753867

1

T1

33037

T11

2340

T12

1684

auto[1]

76661109

1

T1

25491

T11

156

T12

236

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

296344037

1

T1

30042

T11

1706

T12

1338

auto[1]

99070939

1

T1

28486

T11

790

T12

582

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4628274	1			T1	514		T11	7		T12	50
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3425218	1			T1	17		T11	43		T12	6
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1205353	1			T1	446		T11	9		T12	4
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1526032	1			T1	456		T11	6		T13	42
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	373407	1			T1	18		T11	13		T13	3
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1198434	1			T1	378		T13	16		T14	166
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4626256	1			T1	382		T11	22		T12	27
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3428640	1			T1	22		T11	32		T12	7
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1206800	1			T1	382		T11	9		T12	5
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1524705	1			T1	592		T11	7		T12	15
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	375483	1			T1	14		T11	6		T12	2
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1194834	1			T1	437		T11	2		T12	4
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4623354	1			T1	549		T11	23		T12	46
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3430393	1			T1	13		T11	49		T12	8
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1202416	1			T1	441		T11	2		T12	5
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1531437	1			T1	502		T12	1		T13	59
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	375452	1			T1	24		T11	2		T14	147
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1193666	1			T1	300		T11	2		T13	35
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4618417	1			T1	526		T11	13		T12	47
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3429813	1			T1	22		T11	22		T12	5
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1202770	1			T1	414		T11	2		T12	7
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1531745	1			T1	468		T11	6		T12	1
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	376783	1			T1	16		T11	30		T14	208
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1197190	1			T1	383		T11	5		T13	32
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4622527	1			T1	517		T11	16		T12	19
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3429445	1			T1	22		T11	51		T12	1
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1204617	1			T1	452		T11	7		T12	1
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1531586	1			T1	428		T12	30		T13	21
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	373342	1			T1	11		T11	2		T12	7
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1195201	1			T1	399		T11	2		T12	2
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4624790	1			T1	582		T11	10		T12	41
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3427563	1			T1	16		T11	14		T12	10
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1201380	1			T1	384		T11	2		T12	7
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1529087	1			T1	495		T11	12		T12	2
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	376250	1			T1	25		T11	33		T14	136
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1197648	1			T1	327		T11	7		T13	41
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4635894	1			T1	583		T11	25		T12	51
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3426919	1			T1	20		T11	46		T12	8
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1208483	1			T1	435		T11	7		T12	1
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1519799	1			T1	389		T13	46		T17	104
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	371298	1			T1	19		T14	164		T19	4711
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1194325	1			T1	383		T13	45		T14	155
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4629764	1			T1	475		T11	18		T12	47
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3430186	1			T1	19		T11	51		T12	7
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1205310	1			T1	390		T11	9		T12	4
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1526326	1			T1	533		T12	2		T13	38
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	373148	1			T1	24		T13	1		T14	164
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1191984	1			T1	388		T13	22		T14	176
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4619293	1			T1	481		T11	12		T12	44
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3436138	1			T1	19		T11	24		T12	11
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1207575	1			T1	417		T11	2		T12	5
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1525349	1			T1	504		T11	6		T13	69
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	375401	1			T1	24		T11	34		T13	1
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1192962	1			T1	384		T13	65		T14	191
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4627964	1			T1	450		T11	21		T12	18
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3423729	1			T1	22		T11	28		T12	2
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1206338	1			T1	476		T11	4		T12	2
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1529807	1			T1	527		T11	5		T12	29
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	374131	1			T1	6		T11	18		T12	5
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1194749	1			T1	348		T11	2		T12	4
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4615760	1			T1	452		T11	17		T12	26
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3437922	1			T1	20		T11	20		T12	9
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1207418	1			T1	504		T12	5		T13	63
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1527987	1			T1	421		T11	8		T12	19
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	375829	1			T1	29		T11	26		T12	1
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1191802	1			T1	403		T11	7		T13	42
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4624500	1			T1	483		T11	14		T12	17
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3435048	1			T1	13		T11	41		T12	1
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1201036	1			T1	378		T11	7		T12	3
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1525561	1			T1	537		T11	3		T12	31
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	375192	1			T1	18		T11	13		T12	2
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1195381	1			T1	400		T12	6		T13	13
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4621265	1			T1	523		T11	15		T12	17
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3442301	1			T1	19		T11	41		T12	1
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1203293	1			T1	393		T11	7		T12	2
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1527483	1			T1	476		T11	7		T12	35
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	371234	1			T1	11		T11	8		T12	5
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1191142	1			T1	407		T13	8		T14	153
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4613538	1			T1	492		T11	21		T12	43
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3438705	1			T1	15		T11	36		T12	11
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1203015	1			T1	390		T11	2		T12	4
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1532502	1			T1	540		T11	8		T12	2
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	374062	1			T1	21		T11	11		T14	152
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1194896	1			T1	371		T13	43		T14	176
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4621372	1			T1	571		T11	18		T12	36
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3429081	1			T1	17		T11	47		T12	3
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1205222	1			T1	306		T11	9		T12	2
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1530068	1			T1	593		T12	15		T13	45
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	373158	1			T1	11		T11	4		T12	4
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1197817	1			T1	331		T13	82		T14	140
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4614049	1			T1	580		T11	12		T12	17
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3434362	1			T1	25		T11	47		T12	3
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1199355	1			T1	309		T11	4		T13	18
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1535020	1			T1	466		T11	7		T12	32
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	376831	1			T1	14		T11	6		T12	2
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1197101	1			T1	435		T11	2		T12	6
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4630498	1			T1	442		T11	23		T12	29
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3431810	1			T1	23		T11	55		T12	4
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1205455	1			T1	386		T12	7		T13	35
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1527777	1			T1	578		T12	12		T13	52
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	372313	1			T1	21		T12	4		T13	4
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1188865	1			T1	379		T12	4		T13	65
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4633105	1			T1	494		T11	18		T12	15
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3432260	1			T1	14		T11	58		T12	3
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1201492	1			T1	357		T11	2		T12	2
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1527704	1			T1	509		T12	33		T13	25
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	373361	1			T1	24		T12	5		T14	164
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1188796	1			T1	431		T12	2		T13	6
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4631376	1			T1	538		T11	7		T12	25
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3427881	1			T1	29		T11	13		T12	7
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1205687	1			T1	426		T11	2		T12	8
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1530253	1			T1	446		T11	17		T12	8
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	375717	1			T1	9		T11	34		T12	4
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1185804	1			T1	381		T11	5		T12	8
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4626788	1			T1	487		T11	9		T12	29
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3434419	1			T1	36		T11	28		T12	4
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1200451	1			T1	523		T12	7		T13	95
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1528363	1			T1	419		T11	5		T12	11
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	375907	1			T1	10		T11	31		T12	5
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1190790	1			T1	354		T11	5		T12	4
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4617326	1			T1	449		T11	18		T12	40
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3440486	1			T1	18		T11	51		T12	9
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1208192	1			T1	385		T11	5		T12	9
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1527207	1			T1	520		T12	2		T13	61
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	371875	1			T1	23		T11	4		T14	216
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1191632	1			T1	434		T13	60		T14	155
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4634148	1			T1	424		T11	7		T12	37
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3428804	1			T1	27		T11	41		T12	8
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1196354	1			T1	375		T11	5		T12	13
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1531864	1			T1	503		T11	3		T12	2
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	377379	1			T1	10		T11	20		T13	1
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1188169	1			T1	490		T11	2		T13	62
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4621151	1			T1	559		T11	11		T12	13
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3434162	1			T1	28		T11	27		T12	4
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1201837	1			T1	458		T12	3		T13	37
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1536604	1			T1	477		T11	4		T12	27
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	374948	1			T1	2		T11	36		T12	5
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1188016	1			T1	305		T12	8		T13	62
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4626383	1			T1	537		T11	5		T12	31
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3432877	1			T1	15		T11	17		T12	4
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1203177	1			T1	508		T12	5		T13	27
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1530006	1			T1	363		T11	13		T12	17
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	373938	1			T1	18		T11	38		T12	1
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1190337	1			T1	388		T11	5		T12	2
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4632048	1			T1	466		T11	14		T12	25
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3428955	1			T1	20		T11	25		T12	4
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1200147	1			T1	354		T11	2		T12	13
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1527397	1			T1	571		T11	4		T12	13
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	375836	1			T1	21		T11	33		T12	3
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1192335	1			T1	397		T12	2		T13	87
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4635616	1			T1	569		T11	15		T12	16
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3431654	1			T1	19		T11	24		T12	3
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1199014	1			T1	432		T11	3		T12	3
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1525845	1			T1	424		T11	9		T12	23
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	373619	1			T1	25		T11	25		T12	5
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1190970	1			T1	360		T11	2		T12	10
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4622252	1			T1	473		T11	10		T12	36
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3438617	1			T1	21		T11	28		T12	1
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1199304	1			T1	340		T12	3		T13	53
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1529795	1			T1	585		T11	13		T12	17
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	373309	1			T1	11		T11	27		T12	3
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1193441	1			T1	399		T13	34		T14	175
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4622005	1			T1	558		T11	18		T12	28
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3438269	1			T1	16		T11	42		T12	5
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1206058	1			T1	331		T12	7		T13	26
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1528269	1			T1	557		T11	3		T12	16
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	374456	1			T1	15		T11	15		T12	2
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1187661	1			T1	352		T12	2		T13	47
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4620518	1			T1	388		T11	12		T12	43
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3440946	1			T1	23		T11	31		T12	3
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1204909	1			T1	566		T12	12		T13	24
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1530329	1			T1	450		T11	6		T12	2
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	372916	1			T1	14		T11	29		T13	2
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1187100	1			T1	388		T13	61		T14	142
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4623026	1			T1	614		T11	14		T12	50
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3437366	1			T1	16		T11	49		T12	6
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1203062	1			T1	308		T12	4		T13	62
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1527722	1			T1	569		T11	3		T13	22
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	374490	1			T1	16		T11	12		T14	152
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1191052	1			T1	306		T13	60		T14	140
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4622116	1			T1	444		T11	8		T12	31
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3432078	1			T1	19		T11	31		T12	3
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1200972	1			T1	440		T11	3		T12	8
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1534433	1			T1	453		T11	6		T12	14
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	376282	1			T1	29		T11	28		T12	2
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1190837	1			T1	444		T11	2		T12	2
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4623681	1			T1	519		T11	17		T12	14
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3433779	1			T1	25		T11	18		T12	3
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1198665	1			T1	565		T11	2		T12	5
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1536667	1			T1	376		T11	8		T12	27
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	372911	1			T1	6		T11	33		T12	7
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1191015	1			T1	338		T12	4		T13	29

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal