Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[1]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[2]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[3]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[4]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[5]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[6]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[7]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[8]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[9]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[10]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[11]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[12]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[13]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[14]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[15]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[16]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[17]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[18]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[19]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[20]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[21]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[22]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[23]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[24]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[25]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[26]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[27]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[28]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[29]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[30]	12356718	1			T1	1829		T11	78		T12	60
bins_for_gpio_bits[31]	12356718	1			T1	1829		T11	78		T12	60

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

235428940

1

T1

45119

T11

745

T12

1612

auto[1]

159986036

1

T1

13409

T11

1751

T12

308

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

235419811

1

T1

45113

T11

745

T12

1612

auto[1]

159995165

1

T1

13415

T11

1751

T12

308

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7145126	1			T1	1359		T11	19		T12	54
bins_for_gpio_bits[0]	auto[0]	auto[1]	214211	1			T1	57		T11	3		T13	4
bins_for_gpio_bits[0]	auto[1]	auto[0]	214533	1			T1	57		T11	3		T13	4
bins_for_gpio_bits[0]	auto[1]	auto[1]	4782848	1			T1	356		T11	53		T12	6
bins_for_gpio_bits[1]	auto[0]	auto[0]	7143740	1			T1	1292		T11	35		T12	46
bins_for_gpio_bits[1]	auto[0]	auto[1]	213714	1			T1	63		T11	3		T12	1
bins_for_gpio_bits[1]	auto[1]	auto[0]	214021	1			T1	64		T11	3		T12	1
bins_for_gpio_bits[1]	auto[1]	auto[1]	4785243	1			T1	410		T11	37		T12	12
bins_for_gpio_bits[2]	auto[0]	auto[0]	7142831	1			T1	1446		T11	24		T12	52
bins_for_gpio_bits[2]	auto[0]	auto[1]	214096	1			T1	46		T11	1		T13	4
bins_for_gpio_bits[2]	auto[1]	auto[0]	214376	1			T1	46		T11	1		T13	4
bins_for_gpio_bits[2]	auto[1]	auto[1]	4785415	1			T1	291		T11	52		T12	8
bins_for_gpio_bits[3]	auto[0]	auto[0]	7138129	1			T1	1353		T11	20		T12	55
bins_for_gpio_bits[3]	auto[0]	auto[1]	214512	1			T1	54		T11	1		T13	4
bins_for_gpio_bits[3]	auto[1]	auto[0]	214803	1			T1	55		T11	1		T13	4
bins_for_gpio_bits[3]	auto[1]	auto[1]	4789274	1			T1	367		T11	56		T12	5
bins_for_gpio_bits[4]	auto[0]	auto[0]	7144456	1			T1	1340		T11	21		T12	49
bins_for_gpio_bits[4]	auto[0]	auto[1]	213996	1			T1	57		T11	2		T12	1
bins_for_gpio_bits[4]	auto[1]	auto[0]	214274	1			T1	57		T11	2		T12	1
bins_for_gpio_bits[4]	auto[1]	auto[1]	4783992	1			T1	375		T11	53		T12	9
bins_for_gpio_bits[5]	auto[0]	auto[0]	7141164	1			T1	1411		T11	23		T12	50
bins_for_gpio_bits[5]	auto[0]	auto[1]	213796	1			T1	50		T11	1		T13	2
bins_for_gpio_bits[5]	auto[1]	auto[0]	214093	1			T1	50		T11	1		T13	2
bins_for_gpio_bits[5]	auto[1]	auto[1]	4787665	1			T1	318		T11	53		T12	10
bins_for_gpio_bits[6]	auto[0]	auto[0]	7150062	1			T1	1355		T11	30		T12	52
bins_for_gpio_bits[6]	auto[0]	auto[1]	213841	1			T1	52		T11	2		T13	4
bins_for_gpio_bits[6]	auto[1]	auto[0]	214114	1			T1	52		T11	2		T13	4
bins_for_gpio_bits[6]	auto[1]	auto[1]	4778701	1			T1	370		T11	44		T12	8
bins_for_gpio_bits[7]	auto[0]	auto[0]	7147165	1			T1	1340		T11	24		T12	53
bins_for_gpio_bits[7]	auto[0]	auto[1]	213943	1			T1	57		T11	3		T13	3
bins_for_gpio_bits[7]	auto[1]	auto[0]	214235	1			T1	58		T11	3		T13	3
bins_for_gpio_bits[7]	auto[1]	auto[1]	4781375	1			T1	374		T11	48		T12	7
bins_for_gpio_bits[8]	auto[0]	auto[0]	7137484	1			T1	1337		T11	19		T12	49
bins_for_gpio_bits[8]	auto[0]	auto[1]	214488	1			T1	65		T11	1		T13	6
bins_for_gpio_bits[8]	auto[1]	auto[0]	214733	1			T1	65		T11	1		T13	6
bins_for_gpio_bits[8]	auto[1]	auto[1]	4790013	1			T1	362		T11	57		T12	11
bins_for_gpio_bits[9]	auto[0]	auto[0]	7149446	1			T1	1389		T11	28		T12	48
bins_for_gpio_bits[9]	auto[0]	auto[1]	214413	1			T1	64		T11	2		T12	1
bins_for_gpio_bits[9]	auto[1]	auto[0]	214663	1			T1	64		T11	2		T12	1
bins_for_gpio_bits[9]	auto[1]	auto[1]	4778196	1			T1	312		T11	46		T12	10
bins_for_gpio_bits[10]	auto[0]	auto[0]	7137143	1			T1	1320		T11	25		T12	50
bins_for_gpio_bits[10]	auto[0]	auto[1]	213764	1			T1	57		T13	6		T14	44
bins_for_gpio_bits[10]	auto[1]	auto[0]	214022	1			T1	57		T13	6		T14	44
bins_for_gpio_bits[10]	auto[1]	auto[1]	4791789	1			T1	395		T11	53		T12	10
bins_for_gpio_bits[11]	auto[0]	auto[0]	7136992	1			T1	1339		T11	22		T12	49
bins_for_gpio_bits[11]	auto[0]	auto[1]	213826	1			T1	59		T11	2		T12	2
bins_for_gpio_bits[11]	auto[1]	auto[0]	214105	1			T1	59		T11	2		T12	2
bins_for_gpio_bits[11]	auto[1]	auto[1]	4791795	1			T1	372		T11	52		T12	7
bins_for_gpio_bits[12]	auto[0]	auto[0]	7137784	1			T1	1334		T11	27		T12	54
bins_for_gpio_bits[12]	auto[0]	auto[1]	213953	1			T1	58		T11	2		T13	1
bins_for_gpio_bits[12]	auto[1]	auto[0]	214257	1			T1	58		T11	2		T13	1
bins_for_gpio_bits[12]	auto[1]	auto[1]	4790724	1			T1	379		T11	47		T12	6
bins_for_gpio_bits[13]	auto[0]	auto[0]	7134904	1			T1	1362		T11	30		T12	49
bins_for_gpio_bits[13]	auto[0]	auto[1]	213851	1			T1	60		T11	1		T13	8
bins_for_gpio_bits[13]	auto[1]	auto[0]	214151	1			T1	60		T11	1		T13	8
bins_for_gpio_bits[13]	auto[1]	auto[1]	4793812	1			T1	347		T11	46		T12	11
bins_for_gpio_bits[14]	auto[0]	auto[0]	7142088	1			T1	1425		T11	24		T12	53
bins_for_gpio_bits[14]	auto[0]	auto[1]	214280	1			T1	45		T11	3		T13	5
bins_for_gpio_bits[14]	auto[1]	auto[0]	214574	1			T1	45		T11	3		T13	5
bins_for_gpio_bits[14]	auto[1]	auto[1]	4785776	1			T1	314		T11	48		T12	7
bins_for_gpio_bits[15]	auto[0]	auto[0]	7134350	1			T1	1296		T11	21		T12	47
bins_for_gpio_bits[15]	auto[0]	auto[1]	213784	1			T1	58		T11	2		T12	2
bins_for_gpio_bits[15]	auto[1]	auto[0]	214074	1			T1	59		T11	2		T12	2
bins_for_gpio_bits[15]	auto[1]	auto[1]	4794510	1			T1	416		T11	53		T12	9
bins_for_gpio_bits[16]	auto[0]	auto[0]	7149867	1			T1	1341		T11	23		T12	46
bins_for_gpio_bits[16]	auto[0]	auto[1]	213615	1			T1	65		T12	2		T13	8
bins_for_gpio_bits[16]	auto[1]	auto[0]	213863	1			T1	65		T12	2		T13	8
bins_for_gpio_bits[16]	auto[1]	auto[1]	4779373	1			T1	358		T11	55		T12	10
bins_for_gpio_bits[17]	auto[0]	auto[0]	7147939	1			T1	1307		T11	19		T12	49
bins_for_gpio_bits[17]	auto[0]	auto[1]	214061	1			T1	53		T11	1		T12	1
bins_for_gpio_bits[17]	auto[1]	auto[0]	214362	1			T1	53		T11	1		T12	1
bins_for_gpio_bits[17]	auto[1]	auto[1]	4780356	1			T1	416		T11	57		T12	9
bins_for_gpio_bits[18]	auto[0]	auto[0]	7152958	1			T1	1360		T11	25		T12	39
bins_for_gpio_bits[18]	auto[0]	auto[1]	214080	1			T1	49		T11	1		T12	2
bins_for_gpio_bits[18]	auto[1]	auto[0]	214358	1			T1	50		T11	1		T12	2
bins_for_gpio_bits[18]	auto[1]	auto[1]	4775322	1			T1	370		T11	51		T12	17
bins_for_gpio_bits[19]	auto[0]	auto[0]	7141028	1			T1	1372		T11	14		T12	45
bins_for_gpio_bits[19]	auto[0]	auto[1]	214342	1			T1	57		T12	2		T13	8
bins_for_gpio_bits[19]	auto[1]	auto[0]	214574	1			T1	57		T12	2		T13	8
bins_for_gpio_bits[19]	auto[1]	auto[1]	4786774	1			T1	343		T11	64		T12	11
bins_for_gpio_bits[20]	auto[0]	auto[0]	7137818	1			T1	1298		T11	22		T12	51
bins_for_gpio_bits[20]	auto[0]	auto[1]	214597	1			T1	56		T11	1		T13	10
bins_for_gpio_bits[20]	auto[1]	auto[0]	214907	1			T1	56		T11	1		T13	10
bins_for_gpio_bits[20]	auto[1]	auto[1]	4789396	1			T1	419		T11	54		T12	9
bins_for_gpio_bits[21]	auto[0]	auto[0]	7148111	1			T1	1236		T11	13		T12	52
bins_for_gpio_bits[21]	auto[0]	auto[1]	213971	1			T1	66		T11	2		T13	5
bins_for_gpio_bits[21]	auto[1]	auto[0]	214255	1			T1	66		T11	2		T13	5
bins_for_gpio_bits[21]	auto[1]	auto[1]	4780381	1			T1	461		T11	61		T12	8
bins_for_gpio_bits[22]	auto[0]	auto[0]	7145362	1			T1	1449		T11	15		T12	40
bins_for_gpio_bits[22]	auto[0]	auto[1]	213896	1			T1	45		T12	3		T13	6
bins_for_gpio_bits[22]	auto[1]	auto[0]	214230	1			T1	45		T12	3		T13	6
bins_for_gpio_bits[22]	auto[1]	auto[1]	4783230	1			T1	290		T11	63		T12	14
bins_for_gpio_bits[23]	auto[0]	auto[0]	7144798	1			T1	1360		T11	18		T12	52
bins_for_gpio_bits[23]	auto[0]	auto[1]	214489	1			T1	48		T12	1		T13	6
bins_for_gpio_bits[23]	auto[1]	auto[0]	214768	1			T1	48		T12	1		T13	6
bins_for_gpio_bits[23]	auto[1]	auto[1]	4782663	1			T1	373		T11	60		T12	6
bins_for_gpio_bits[24]	auto[0]	auto[0]	7144884	1			T1	1337		T11	19		T12	50
bins_for_gpio_bits[24]	auto[0]	auto[1]	214425	1			T1	54		T11	1		T12	1
bins_for_gpio_bits[24]	auto[1]	auto[0]	214708	1			T1	54		T11	1		T12	1
bins_for_gpio_bits[24]	auto[1]	auto[1]	4782701	1			T1	384		T11	57		T12	8
bins_for_gpio_bits[25]	auto[0]	auto[0]	7146288	1			T1	1370		T11	26		T12	38
bins_for_gpio_bits[25]	auto[0]	auto[1]	213888	1			T1	55		T11	1		T12	4
bins_for_gpio_bits[25]	auto[1]	auto[0]	214187	1			T1	55		T11	1		T12	4
bins_for_gpio_bits[25]	auto[1]	auto[1]	4782355	1			T1	349		T11	50		T12	14
bins_for_gpio_bits[26]	auto[0]	auto[0]	7136620	1			T1	1342		T11	23		T12	56
bins_for_gpio_bits[26]	auto[0]	auto[1]	214455	1			T1	56		T13	5		T14	43
bins_for_gpio_bits[26]	auto[1]	auto[0]	214731	1			T1	56		T13	5		T14	43
bins_for_gpio_bits[26]	auto[1]	auto[1]	4790912	1			T1	375		T11	55		T12	4
bins_for_gpio_bits[27]	auto[0]	auto[0]	7141905	1			T1	1399		T11	21		T12	50
bins_for_gpio_bits[27]	auto[0]	auto[1]	214127	1			T1	47		T12	1		T13	4
bins_for_gpio_bits[27]	auto[1]	auto[0]	214427	1			T1	47		T12	1		T13	4
bins_for_gpio_bits[27]	auto[1]	auto[1]	4786259	1			T1	336		T11	57		T12	8
bins_for_gpio_bits[28]	auto[0]	auto[0]	7140981	1			T1	1340		T11	18		T12	57
bins_for_gpio_bits[28]	auto[0]	auto[1]	214470	1			T1	64		T13	7		T14	41
bins_for_gpio_bits[28]	auto[1]	auto[0]	214775	1			T1	64		T13	7		T14	41
bins_for_gpio_bits[28]	auto[1]	auto[1]	4786492	1			T1	361		T11	60		T12	3
bins_for_gpio_bits[29]	auto[0]	auto[0]	7138996	1			T1	1443		T11	17		T12	54
bins_for_gpio_bits[29]	auto[0]	auto[1]	214556	1			T1	48		T13	10		T14	46
bins_for_gpio_bits[29]	auto[1]	auto[0]	214814	1			T1	48		T13	10		T14	45
bins_for_gpio_bits[29]	auto[1]	auto[1]	4788352	1			T1	290		T11	61		T12	6
bins_for_gpio_bits[30]	auto[0]	auto[0]	7142945	1			T1	1279		T11	16		T12	52
bins_for_gpio_bits[30]	auto[0]	auto[1]	214315	1			T1	58		T11	1		T12	1
bins_for_gpio_bits[30]	auto[1]	auto[0]	214576	1			T1	58		T11	1		T12	1
bins_for_gpio_bits[30]	auto[1]	auto[1]	4784882	1			T1	434		T11	60		T12	6
bins_for_gpio_bits[31]	auto[0]	auto[0]	7144403	1			T1	1415		T11	26		T12	45
bins_for_gpio_bits[31]	auto[0]	auto[1]	214289	1			T1	44		T11	1		T12	1
bins_for_gpio_bits[31]	auto[1]	auto[0]	214610	1			T1	45		T11	1		T12	1
bins_for_gpio_bits[31]	auto[1]	auto[1]	4783416	1			T1	325		T11	50		T12	13