Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7421584 |
1 |
|
|
T1 |
938 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5100619 |
1 |
|
|
T1 |
997 |
|
T13 |
103 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11862191 |
1 |
|
|
T1 |
1902 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
660012 |
1 |
|
|
T1 |
33 |
|
T13 |
1 |
|
T19 |
1501 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7361760 |
1 |
|
|
T1 |
1000 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5160443 |
1 |
|
|
T1 |
935 |
|
T13 |
69 |
|
T19 |
11073 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2272871 |
1 |
|
|
T1 |
476 |
|
T13 |
34 |
|
T19 |
5013 |
| auto[1] |
auto[0] |
auto[1] |
334120 |
1 |
|
|
T1 |
22 |
|
T13 |
1 |
|
T19 |
790 |
| auto[1] |
auto[1] |
auto[0] |
2227560 |
1 |
|
|
T1 |
426 |
|
T13 |
34 |
|
T19 |
4559 |
| auto[1] |
auto[1] |
auto[1] |
325892 |
1 |
|
|
T1 |
11 |
|
T19 |
711 |
|
T105 |
99 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7345092 |
1 |
|
|
T1 |
1073 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5177111 |
1 |
|
|
T1 |
862 |
|
T13 |
57 |
|
T19 |
12772 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11864553 |
1 |
|
|
T1 |
1898 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
657650 |
1 |
|
|
T1 |
37 |
|
T13 |
4 |
|
T19 |
1598 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7377826 |
1 |
|
|
T1 |
933 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5144377 |
1 |
|
|
T1 |
1002 |
|
T13 |
68 |
|
T19 |
11994 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2234494 |
1 |
|
|
T1 |
524 |
|
T13 |
36 |
|
T19 |
5155 |
| auto[1] |
auto[0] |
auto[1] |
327361 |
1 |
|
|
T1 |
22 |
|
T13 |
4 |
|
T19 |
797 |
| auto[1] |
auto[1] |
auto[0] |
2252233 |
1 |
|
|
T1 |
441 |
|
T13 |
28 |
|
T19 |
5241 |
| auto[1] |
auto[1] |
auto[1] |
330289 |
1 |
|
|
T1 |
15 |
|
T19 |
801 |
|
T105 |
104 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7401546 |
1 |
|
|
T1 |
1003 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5120657 |
1 |
|
|
T1 |
932 |
|
T13 |
84 |
|
T19 |
12592 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11871604 |
1 |
|
|
T1 |
1899 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
650599 |
1 |
|
|
T1 |
36 |
|
T13 |
3 |
|
T15 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7416229 |
1 |
|
|
T1 |
1031 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5105974 |
1 |
|
|
T1 |
904 |
|
T13 |
75 |
|
T15 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2252294 |
1 |
|
|
T1 |
499 |
|
T13 |
28 |
|
T15 |
3 |
| auto[1] |
auto[0] |
auto[1] |
330405 |
1 |
|
|
T1 |
19 |
|
T13 |
1 |
|
T15 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2203081 |
1 |
|
|
T1 |
369 |
|
T13 |
44 |
|
T19 |
4728 |
| auto[1] |
auto[1] |
auto[1] |
320194 |
1 |
|
|
T1 |
17 |
|
T13 |
2 |
|
T19 |
735 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7418266 |
1 |
|
|
T1 |
1016 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5103937 |
1 |
|
|
T1 |
919 |
|
T13 |
38 |
|
T19 |
12246 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11862425 |
1 |
|
|
T1 |
1898 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
659778 |
1 |
|
|
T1 |
37 |
|
T13 |
1 |
|
T19 |
1840 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7352819 |
1 |
|
|
T1 |
984 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5169384 |
1 |
|
|
T1 |
951 |
|
T13 |
104 |
|
T19 |
13061 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2284418 |
1 |
|
|
T1 |
431 |
|
T13 |
98 |
|
T19 |
5294 |
| auto[1] |
auto[0] |
auto[1] |
334970 |
1 |
|
|
T1 |
17 |
|
T13 |
1 |
|
T19 |
840 |
| auto[1] |
auto[1] |
auto[0] |
2225188 |
1 |
|
|
T1 |
483 |
|
T13 |
5 |
|
T19 |
5927 |
| auto[1] |
auto[1] |
auto[1] |
324808 |
1 |
|
|
T1 |
20 |
|
T19 |
1000 |
|
T105 |
108 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7344738 |
1 |
|
|
T1 |
882 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5177465 |
1 |
|
|
T1 |
1053 |
|
T13 |
92 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11859227 |
1 |
|
|
T1 |
1895 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
662976 |
1 |
|
|
T1 |
40 |
|
T19 |
1583 |
|
T105 |
225 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7344573 |
1 |
|
|
T1 |
894 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5177630 |
1 |
|
|
T1 |
1041 |
|
T13 |
66 |
|
T19 |
11616 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2246025 |
1 |
|
|
T1 |
440 |
|
T13 |
53 |
|
T19 |
4606 |
| auto[1] |
auto[0] |
auto[1] |
330106 |
1 |
|
|
T1 |
17 |
|
T19 |
733 |
|
T105 |
121 |
| auto[1] |
auto[1] |
auto[0] |
2268629 |
1 |
|
|
T1 |
561 |
|
T13 |
13 |
|
T19 |
5427 |
| auto[1] |
auto[1] |
auto[1] |
332870 |
1 |
|
|
T1 |
23 |
|
T19 |
850 |
|
T105 |
104 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7425977 |
1 |
|
|
T1 |
895 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5096226 |
1 |
|
|
T1 |
1040 |
|
T13 |
135 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11869261 |
1 |
|
|
T1 |
1897 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
652942 |
1 |
|
|
T1 |
38 |
|
T13 |
4 |
|
T19 |
1722 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7399184 |
1 |
|
|
T1 |
931 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5123019 |
1 |
|
|
T1 |
1004 |
|
T13 |
69 |
|
T19 |
12732 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2245869 |
1 |
|
|
T1 |
404 |
|
T13 |
16 |
|
T19 |
5447 |
| auto[1] |
auto[0] |
auto[1] |
328866 |
1 |
|
|
T1 |
9 |
|
T19 |
831 |
|
T105 |
120 |
| auto[1] |
auto[1] |
auto[0] |
2224208 |
1 |
|
|
T1 |
562 |
|
T13 |
49 |
|
T19 |
5563 |
| auto[1] |
auto[1] |
auto[1] |
324076 |
1 |
|
|
T1 |
29 |
|
T13 |
4 |
|
T19 |
891 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7394121 |
1 |
|
|
T1 |
1159 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5128082 |
1 |
|
|
T1 |
776 |
|
T13 |
37 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11866531 |
1 |
|
|
T1 |
1911 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
655672 |
1 |
|
|
T1 |
24 |
|
T13 |
3 |
|
T19 |
1795 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7386281 |
1 |
|
|
T1 |
951 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5135922 |
1 |
|
|
T1 |
984 |
|
T13 |
68 |
|
T19 |
12822 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2244487 |
1 |
|
|
T1 |
575 |
|
T13 |
53 |
|
T19 |
4993 |
| auto[1] |
auto[0] |
auto[1] |
327818 |
1 |
|
|
T1 |
18 |
|
T13 |
3 |
|
T19 |
806 |
| auto[1] |
auto[1] |
auto[0] |
2235763 |
1 |
|
|
T1 |
385 |
|
T13 |
12 |
|
T19 |
6034 |
| auto[1] |
auto[1] |
auto[1] |
327854 |
1 |
|
|
T1 |
6 |
|
T19 |
989 |
|
T105 |
66 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7346487 |
1 |
|
|
T1 |
893 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5175716 |
1 |
|
|
T1 |
1042 |
|
T13 |
125 |
|
T19 |
12914 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11861664 |
1 |
|
|
T1 |
1898 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
660539 |
1 |
|
|
T1 |
37 |
|
T13 |
1 |
|
T19 |
1532 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7361758 |
1 |
|
|
T1 |
972 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5160445 |
1 |
|
|
T1 |
963 |
|
T13 |
52 |
|
T19 |
11737 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2238908 |
1 |
|
|
T1 |
392 |
|
T13 |
15 |
|
T19 |
5100 |
| auto[1] |
auto[0] |
auto[1] |
328260 |
1 |
|
|
T1 |
14 |
|
T19 |
711 |
|
T105 |
100 |
| auto[1] |
auto[1] |
auto[0] |
2260998 |
1 |
|
|
T1 |
534 |
|
T13 |
36 |
|
T19 |
5105 |
| auto[1] |
auto[1] |
auto[1] |
332279 |
1 |
|
|
T1 |
23 |
|
T13 |
1 |
|
T19 |
821 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7383601 |
1 |
|
|
T1 |
888 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5138602 |
1 |
|
|
T1 |
1047 |
|
T13 |
78 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11864661 |
1 |
|
|
T1 |
1888 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
657542 |
1 |
|
|
T1 |
47 |
|
T13 |
4 |
|
T19 |
1725 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7378530 |
1 |
|
|
T1 |
912 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5143673 |
1 |
|
|
T1 |
1023 |
|
T13 |
61 |
|
T19 |
12697 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2251283 |
1 |
|
|
T1 |
448 |
|
T13 |
33 |
|
T19 |
6695 |
| auto[1] |
auto[0] |
auto[1] |
329748 |
1 |
|
|
T1 |
17 |
|
T13 |
2 |
|
T19 |
1052 |
| auto[1] |
auto[1] |
auto[0] |
2234848 |
1 |
|
|
T1 |
528 |
|
T13 |
24 |
|
T19 |
4277 |
| auto[1] |
auto[1] |
auto[1] |
327794 |
1 |
|
|
T1 |
30 |
|
T13 |
2 |
|
T19 |
673 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7394167 |
1 |
|
|
T1 |
934 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5128036 |
1 |
|
|
T1 |
1001 |
|
T13 |
89 |
|
T19 |
12872 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11860591 |
1 |
|
|
T1 |
1896 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
661612 |
1 |
|
|
T1 |
39 |
|
T13 |
1 |
|
T19 |
1744 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7351996 |
1 |
|
|
T1 |
833 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5170207 |
1 |
|
|
T1 |
1102 |
|
T13 |
94 |
|
T19 |
12723 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2261442 |
1 |
|
|
T1 |
450 |
|
T13 |
66 |
|
T19 |
5315 |
| auto[1] |
auto[0] |
auto[1] |
332773 |
1 |
|
|
T1 |
20 |
|
T13 |
1 |
|
T19 |
830 |
| auto[1] |
auto[1] |
auto[0] |
2247153 |
1 |
|
|
T1 |
613 |
|
T13 |
27 |
|
T19 |
5664 |
| auto[1] |
auto[1] |
auto[1] |
328839 |
1 |
|
|
T1 |
19 |
|
T19 |
914 |
|
T105 |
128 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7341793 |
1 |
|
|
T1 |
940 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5180410 |
1 |
|
|
T1 |
995 |
|
T13 |
70 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11866404 |
1 |
|
|
T1 |
1900 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
655799 |
1 |
|
|
T1 |
35 |
|
T19 |
1891 |
|
T105 |
179 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7381844 |
1 |
|
|
T1 |
964 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5140359 |
1 |
|
|
T1 |
971 |
|
T13 |
62 |
|
T19 |
13605 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2223000 |
1 |
|
|
T1 |
384 |
|
T13 |
37 |
|
T19 |
5656 |
| auto[1] |
auto[0] |
auto[1] |
323674 |
1 |
|
|
T1 |
18 |
|
T19 |
892 |
|
T105 |
93 |
| auto[1] |
auto[1] |
auto[0] |
2261560 |
1 |
|
|
T1 |
552 |
|
T13 |
25 |
|
T19 |
6058 |
| auto[1] |
auto[1] |
auto[1] |
332125 |
1 |
|
|
T1 |
17 |
|
T19 |
999 |
|
T105 |
86 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7396137 |
1 |
|
|
T1 |
1082 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5126066 |
1 |
|
|
T1 |
853 |
|
T13 |
102 |
|
T19 |
12632 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11866392 |
1 |
|
|
T1 |
1897 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
655811 |
1 |
|
|
T1 |
38 |
|
T13 |
1 |
|
T19 |
1597 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7382911 |
1 |
|
|
T1 |
884 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5139292 |
1 |
|
|
T1 |
1051 |
|
T13 |
23 |
|
T15 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2257536 |
1 |
|
|
T1 |
520 |
|
T13 |
12 |
|
T15 |
4 |
| auto[1] |
auto[0] |
auto[1] |
330047 |
1 |
|
|
T1 |
22 |
|
T19 |
800 |
|
T105 |
123 |
| auto[1] |
auto[1] |
auto[0] |
2225945 |
1 |
|
|
T1 |
493 |
|
T13 |
10 |
|
T19 |
5454 |
| auto[1] |
auto[1] |
auto[1] |
325764 |
1 |
|
|
T1 |
16 |
|
T13 |
1 |
|
T19 |
797 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7377529 |
1 |
|
|
T1 |
817 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5144674 |
1 |
|
|
T1 |
1118 |
|
T13 |
124 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11867791 |
1 |
|
|
T1 |
1903 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
654412 |
1 |
|
|
T1 |
32 |
|
T13 |
1 |
|
T19 |
1645 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7397648 |
1 |
|
|
T1 |
893 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5124555 |
1 |
|
|
T1 |
1042 |
|
T13 |
75 |
|
T15 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2242684 |
1 |
|
|
T1 |
453 |
|
T13 |
33 |
|
T15 |
4 |
| auto[1] |
auto[0] |
auto[1] |
328671 |
1 |
|
|
T1 |
16 |
|
T19 |
807 |
|
T105 |
109 |
| auto[1] |
auto[1] |
auto[0] |
2227459 |
1 |
|
|
T1 |
557 |
|
T13 |
41 |
|
T19 |
5233 |
| auto[1] |
auto[1] |
auto[1] |
325741 |
1 |
|
|
T1 |
16 |
|
T13 |
1 |
|
T19 |
838 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7349603 |
1 |
|
|
T1 |
928 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5172600 |
1 |
|
|
T1 |
1007 |
|
T13 |
113 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11861018 |
1 |
|
|
T1 |
1908 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
661185 |
1 |
|
|
T1 |
27 |
|
T13 |
2 |
|
T19 |
1954 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7355205 |
1 |
|
|
T1 |
1156 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5166998 |
1 |
|
|
T1 |
779 |
|
T13 |
57 |
|
T19 |
14056 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2232230 |
1 |
|
|
T1 |
324 |
|
T13 |
10 |
|
T19 |
6027 |
| auto[1] |
auto[0] |
auto[1] |
327733 |
1 |
|
|
T1 |
7 |
|
T13 |
1 |
|
T19 |
929 |
| auto[1] |
auto[1] |
auto[0] |
2273583 |
1 |
|
|
T1 |
428 |
|
T13 |
45 |
|
T19 |
6075 |
| auto[1] |
auto[1] |
auto[1] |
333452 |
1 |
|
|
T1 |
20 |
|
T13 |
1 |
|
T19 |
1025 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7370654 |
1 |
|
|
T1 |
964 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5151549 |
1 |
|
|
T1 |
971 |
|
T13 |
117 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11864523 |
1 |
|
|
T1 |
1894 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
657680 |
1 |
|
|
T1 |
41 |
|
T19 |
1684 |
|
T105 |
192 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7383115 |
1 |
|
|
T1 |
1002 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5139088 |
1 |
|
|
T1 |
933 |
|
T13 |
59 |
|
T19 |
12662 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2246975 |
1 |
|
|
T1 |
443 |
|
T13 |
22 |
|
T19 |
5819 |
| auto[1] |
auto[0] |
auto[1] |
330128 |
1 |
|
|
T1 |
17 |
|
T19 |
914 |
|
T105 |
100 |
| auto[1] |
auto[1] |
auto[0] |
2234433 |
1 |
|
|
T1 |
449 |
|
T13 |
37 |
|
T19 |
5159 |
| auto[1] |
auto[1] |
auto[1] |
327552 |
1 |
|
|
T1 |
24 |
|
T19 |
770 |
|
T105 |
92 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7379437 |
1 |
|
|
T1 |
882 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5142766 |
1 |
|
|
T1 |
1053 |
|
T13 |
47 |
|
T19 |
11632 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11868570 |
1 |
|
|
T1 |
1905 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
653633 |
1 |
|
|
T1 |
30 |
|
T13 |
4 |
|
T15 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7395438 |
1 |
|
|
T1 |
1013 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5126765 |
1 |
|
|
T1 |
922 |
|
T13 |
97 |
|
T15 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2242248 |
1 |
|
|
T1 |
391 |
|
T13 |
76 |
|
T15 |
3 |
| auto[1] |
auto[0] |
auto[1] |
327785 |
1 |
|
|
T1 |
15 |
|
T13 |
4 |
|
T15 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2230884 |
1 |
|
|
T1 |
501 |
|
T13 |
17 |
|
T19 |
5382 |
| auto[1] |
auto[1] |
auto[1] |
325848 |
1 |
|
|
T1 |
15 |
|
T19 |
857 |
|
T105 |
97 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7382113 |
1 |
|
|
T1 |
1025 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5140090 |
1 |
|
|
T1 |
910 |
|
T13 |
118 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11859233 |
1 |
|
|
T1 |
1913 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
662970 |
1 |
|
|
T1 |
22 |
|
T13 |
6 |
|
T19 |
1540 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7347245 |
1 |
|
|
T1 |
1024 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5174958 |
1 |
|
|
T1 |
911 |
|
T13 |
112 |
|
T19 |
11989 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2255410 |
1 |
|
|
T1 |
448 |
|
T13 |
30 |
|
T19 |
4924 |
| auto[1] |
auto[0] |
auto[1] |
331066 |
1 |
|
|
T1 |
10 |
|
T13 |
3 |
|
T19 |
708 |
| auto[1] |
auto[1] |
auto[0] |
2256578 |
1 |
|
|
T1 |
441 |
|
T13 |
76 |
|
T19 |
5525 |
| auto[1] |
auto[1] |
auto[1] |
331904 |
1 |
|
|
T1 |
12 |
|
T13 |
3 |
|
T19 |
832 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7358004 |
1 |
|
|
T1 |
978 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5164199 |
1 |
|
|
T1 |
957 |
|
T13 |
39 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11868115 |
1 |
|
|
T1 |
1901 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
654088 |
1 |
|
|
T1 |
34 |
|
T13 |
8 |
|
T19 |
1751 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7396114 |
1 |
|
|
T1 |
986 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5126089 |
1 |
|
|
T1 |
949 |
|
T13 |
115 |
|
T19 |
12788 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2233954 |
1 |
|
|
T1 |
503 |
|
T13 |
89 |
|
T19 |
5029 |
| auto[1] |
auto[0] |
auto[1] |
326175 |
1 |
|
|
T1 |
16 |
|
T13 |
7 |
|
T19 |
859 |
| auto[1] |
auto[1] |
auto[0] |
2238047 |
1 |
|
|
T1 |
412 |
|
T13 |
18 |
|
T19 |
6008 |
| auto[1] |
auto[1] |
auto[1] |
327913 |
1 |
|
|
T1 |
18 |
|
T13 |
1 |
|
T19 |
892 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7388157 |
1 |
|
|
T1 |
1116 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5134046 |
1 |
|
|
T1 |
819 |
|
T13 |
131 |
|
T19 |
12808 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11868088 |
1 |
|
|
T1 |
1897 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
654115 |
1 |
|
|
T1 |
38 |
|
T13 |
3 |
|
T19 |
1648 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7386848 |
1 |
|
|
T1 |
961 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5135355 |
1 |
|
|
T1 |
974 |
|
T13 |
54 |
|
T19 |
12404 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2253603 |
1 |
|
|
T1 |
523 |
|
T13 |
17 |
|
T19 |
4684 |
| auto[1] |
auto[0] |
auto[1] |
328634 |
1 |
|
|
T1 |
19 |
|
T13 |
3 |
|
T19 |
716 |
| auto[1] |
auto[1] |
auto[0] |
2227637 |
1 |
|
|
T1 |
413 |
|
T13 |
34 |
|
T19 |
6072 |
| auto[1] |
auto[1] |
auto[1] |
325481 |
1 |
|
|
T1 |
19 |
|
T19 |
932 |
|
T105 |
147 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |