Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7369553 |
1 |
|
|
T1 |
842 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5152650 |
1 |
|
|
T1 |
1093 |
|
T13 |
74 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11864211 |
1 |
|
|
T1 |
1898 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
657992 |
1 |
|
|
T1 |
37 |
|
T13 |
1 |
|
T19 |
1631 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7374754 |
1 |
|
|
T1 |
945 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5147449 |
1 |
|
|
T1 |
990 |
|
T13 |
27 |
|
T15 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2259772 |
1 |
|
|
T1 |
406 |
|
T13 |
10 |
|
T15 |
4 |
| auto[1] |
auto[0] |
auto[1] |
331236 |
1 |
|
|
T1 |
17 |
|
T19 |
771 |
|
T105 |
81 |
| auto[1] |
auto[1] |
auto[0] |
2229685 |
1 |
|
|
T1 |
547 |
|
T13 |
16 |
|
T19 |
5321 |
| auto[1] |
auto[1] |
auto[1] |
326756 |
1 |
|
|
T1 |
20 |
|
T13 |
1 |
|
T19 |
860 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |