Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7405543 |
1 |
|
|
T1 |
897 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5116660 |
1 |
|
|
T1 |
1038 |
|
T13 |
70 |
|
T19 |
12753 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11867524 |
1 |
|
|
T1 |
1893 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
654679 |
1 |
|
|
T1 |
42 |
|
T19 |
1649 |
|
T105 |
101 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7398763 |
1 |
|
|
T1 |
1000 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5123440 |
1 |
|
|
T1 |
935 |
|
T13 |
28 |
|
T15 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2245592 |
1 |
|
|
T1 |
393 |
|
T13 |
26 |
|
T15 |
4 |
| auto[1] |
auto[0] |
auto[1] |
329794 |
1 |
|
|
T1 |
14 |
|
T19 |
783 |
|
T105 |
54 |
| auto[1] |
auto[1] |
auto[0] |
2223169 |
1 |
|
|
T1 |
500 |
|
T13 |
2 |
|
T19 |
5888 |
| auto[1] |
auto[1] |
auto[1] |
324885 |
1 |
|
|
T1 |
28 |
|
T19 |
866 |
|
T105 |
47 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |