Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7345092 |
1 |
|
|
T1 |
1073 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5177111 |
1 |
|
|
T1 |
862 |
|
T13 |
57 |
|
T19 |
12772 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10403524 |
1 |
|
|
T1 |
1718 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
2118679 |
1 |
|
|
T1 |
217 |
|
T13 |
9 |
|
T15 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7389172 |
1 |
|
|
T1 |
1095 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5133031 |
1 |
|
|
T1 |
840 |
|
T13 |
91 |
|
T15 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1497708 |
1 |
|
|
T1 |
395 |
|
T13 |
51 |
|
T19 |
2579 |
| auto[1] |
auto[0] |
auto[1] |
1060046 |
1 |
|
|
T1 |
107 |
|
T13 |
9 |
|
T15 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1516644 |
1 |
|
|
T1 |
228 |
|
T13 |
31 |
|
T19 |
2634 |
| auto[1] |
auto[1] |
auto[1] |
1058633 |
1 |
|
|
T1 |
110 |
|
T19 |
4217 |
|
T105 |
333 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |