Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7425977 |
1 |
|
|
T1 |
895 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5096226 |
1 |
|
|
T1 |
1040 |
|
T13 |
135 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10405108 |
1 |
|
|
T1 |
1756 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
2117095 |
1 |
|
|
T1 |
179 |
|
T13 |
3 |
|
T19 |
8143 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7391165 |
1 |
|
|
T1 |
1011 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5131038 |
1 |
|
|
T1 |
924 |
|
T13 |
86 |
|
T15 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1517440 |
1 |
|
|
T1 |
362 |
|
T13 |
31 |
|
T15 |
2 |
| auto[1] |
auto[0] |
auto[1] |
1064923 |
1 |
|
|
T1 |
90 |
|
T19 |
3729 |
|
T105 |
268 |
| auto[1] |
auto[1] |
auto[0] |
1496503 |
1 |
|
|
T1 |
383 |
|
T13 |
52 |
|
T19 |
2871 |
| auto[1] |
auto[1] |
auto[1] |
1052172 |
1 |
|
|
T1 |
89 |
|
T13 |
3 |
|
T19 |
4414 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |