Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7394121 |
1 |
|
|
T1 |
1159 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5128082 |
1 |
|
|
T1 |
776 |
|
T13 |
37 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10410445 |
1 |
|
|
T1 |
1725 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
2111758 |
1 |
|
|
T1 |
210 |
|
T13 |
12 |
|
T15 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7406982 |
1 |
|
|
T1 |
1055 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5115221 |
1 |
|
|
T1 |
880 |
|
T13 |
29 |
|
T15 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1512276 |
1 |
|
|
T1 |
397 |
|
T13 |
15 |
|
T15 |
1 |
| auto[1] |
auto[0] |
auto[1] |
1065051 |
1 |
|
|
T1 |
127 |
|
T13 |
12 |
|
T15 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1491187 |
1 |
|
|
T1 |
273 |
|
T13 |
2 |
|
T19 |
2345 |
| auto[1] |
auto[1] |
auto[1] |
1046707 |
1 |
|
|
T1 |
83 |
|
T19 |
3179 |
|
T105 |
175 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |