Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7394167 |
1 |
|
|
T1 |
934 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5128036 |
1 |
|
|
T1 |
1001 |
|
T13 |
89 |
|
T19 |
12872 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10398320 |
1 |
|
|
T1 |
1749 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
2123883 |
1 |
|
|
T1 |
186 |
|
T15 |
1 |
|
T19 |
7293 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7374761 |
1 |
|
|
T1 |
969 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5147442 |
1 |
|
|
T1 |
966 |
|
T13 |
59 |
|
T15 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1519642 |
1 |
|
|
T1 |
348 |
|
T13 |
12 |
|
T15 |
1 |
| auto[1] |
auto[0] |
auto[1] |
1067757 |
1 |
|
|
T1 |
95 |
|
T15 |
1 |
|
T19 |
3984 |
| auto[1] |
auto[1] |
auto[0] |
1503917 |
1 |
|
|
T1 |
432 |
|
T13 |
47 |
|
T19 |
2376 |
| auto[1] |
auto[1] |
auto[1] |
1056126 |
1 |
|
|
T1 |
91 |
|
T19 |
3309 |
|
T105 |
190 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |