Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7341793 |
1 |
|
|
T1 |
940 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5180410 |
1 |
|
|
T1 |
995 |
|
T13 |
70 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10400688 |
1 |
|
|
T1 |
1696 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
2121515 |
1 |
|
|
T1 |
239 |
|
T13 |
22 |
|
T19 |
6916 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7373827 |
1 |
|
|
T1 |
761 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5148376 |
1 |
|
|
T1 |
1174 |
|
T13 |
48 |
|
T19 |
11974 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1496482 |
1 |
|
|
T1 |
432 |
|
T13 |
18 |
|
T19 |
2461 |
| auto[1] |
auto[0] |
auto[1] |
1054004 |
1 |
|
|
T1 |
108 |
|
T13 |
22 |
|
T19 |
3242 |
| auto[1] |
auto[1] |
auto[0] |
1530379 |
1 |
|
|
T1 |
503 |
|
T13 |
8 |
|
T19 |
2597 |
| auto[1] |
auto[1] |
auto[1] |
1067511 |
1 |
|
|
T1 |
131 |
|
T19 |
3674 |
|
T105 |
212 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |