Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7377529 |
1 |
|
|
T1 |
817 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5144674 |
1 |
|
|
T1 |
1118 |
|
T13 |
124 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10405653 |
1 |
|
|
T1 |
1742 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
2116550 |
1 |
|
|
T1 |
193 |
|
T13 |
26 |
|
T19 |
7143 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7405084 |
1 |
|
|
T1 |
706 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5117119 |
1 |
|
|
T1 |
1229 |
|
T13 |
106 |
|
T19 |
11727 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1490787 |
1 |
|
|
T1 |
461 |
|
T13 |
35 |
|
T19 |
2327 |
| auto[1] |
auto[0] |
auto[1] |
1054343 |
1 |
|
|
T1 |
96 |
|
T13 |
13 |
|
T19 |
3622 |
| auto[1] |
auto[1] |
auto[0] |
1509782 |
1 |
|
|
T1 |
575 |
|
T13 |
45 |
|
T19 |
2257 |
| auto[1] |
auto[1] |
auto[1] |
1062207 |
1 |
|
|
T1 |
97 |
|
T13 |
13 |
|
T19 |
3521 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |