Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7397101 |
1 |
|
|
T1 |
877 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5125102 |
1 |
|
|
T1 |
1058 |
|
T13 |
136 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11870489 |
1 |
|
|
T1 |
1911 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
651714 |
1 |
|
|
T1 |
24 |
|
T13 |
3 |
|
T19 |
1781 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7415994 |
1 |
|
|
T1 |
1170 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5106209 |
1 |
|
|
T1 |
765 |
|
T13 |
60 |
|
T19 |
12800 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2240694 |
1 |
|
|
T1 |
296 |
|
T13 |
30 |
|
T19 |
5356 |
| auto[1] |
auto[0] |
auto[1] |
327950 |
1 |
|
|
T1 |
12 |
|
T13 |
2 |
|
T19 |
915 |
| auto[1] |
auto[1] |
auto[0] |
2213801 |
1 |
|
|
T1 |
445 |
|
T13 |
27 |
|
T19 |
5663 |
| auto[1] |
auto[1] |
auto[1] |
323764 |
1 |
|
|
T1 |
12 |
|
T13 |
1 |
|
T19 |
866 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |