Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7358004 |
1 |
|
|
T1 |
978 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5164199 |
1 |
|
|
T1 |
957 |
|
T13 |
39 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10397398 |
1 |
|
|
T1 |
1710 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
2124805 |
1 |
|
|
T1 |
225 |
|
T13 |
60 |
|
T19 |
7464 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7378069 |
1 |
|
|
T1 |
810 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5144134 |
1 |
|
|
T1 |
1125 |
|
T13 |
91 |
|
T19 |
12631 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1512355 |
1 |
|
|
T1 |
472 |
|
T13 |
26 |
|
T19 |
2713 |
| auto[1] |
auto[0] |
auto[1] |
1064636 |
1 |
|
|
T1 |
101 |
|
T13 |
47 |
|
T19 |
3510 |
| auto[1] |
auto[1] |
auto[0] |
1506974 |
1 |
|
|
T1 |
428 |
|
T13 |
5 |
|
T19 |
2454 |
| auto[1] |
auto[1] |
auto[1] |
1060169 |
1 |
|
|
T1 |
124 |
|
T13 |
13 |
|
T19 |
3954 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |