Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7377726 |
1 |
|
|
T1 |
1025 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5144477 |
1 |
|
|
T1 |
910 |
|
T13 |
150 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11862721 |
1 |
|
|
T1 |
1896 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
659482 |
1 |
|
|
T1 |
39 |
|
T13 |
1 |
|
T19 |
1833 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7359097 |
1 |
|
|
T1 |
897 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5163106 |
1 |
|
|
T1 |
1038 |
|
T13 |
47 |
|
T15 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2251331 |
1 |
|
|
T1 |
476 |
|
T13 |
13 |
|
T15 |
4 |
| auto[1] |
auto[0] |
auto[1] |
328875 |
1 |
|
|
T1 |
20 |
|
T19 |
921 |
|
T105 |
124 |
| auto[1] |
auto[1] |
auto[0] |
2252293 |
1 |
|
|
T1 |
523 |
|
T13 |
33 |
|
T19 |
5924 |
| auto[1] |
auto[1] |
auto[1] |
330607 |
1 |
|
|
T1 |
19 |
|
T13 |
1 |
|
T19 |
912 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |