Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7402211 |
1 |
|
|
T1 |
865 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5119992 |
1 |
|
|
T1 |
1070 |
|
T13 |
155 |
|
T15 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11865629 |
1 |
|
|
T1 |
1904 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
656574 |
1 |
|
|
T1 |
31 |
|
T19 |
1869 |
|
T105 |
186 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7378114 |
1 |
|
|
T1 |
958 |
|
T11 |
44 |
|
T12 |
31 |
| auto[1] |
5144089 |
1 |
|
|
T1 |
977 |
|
T13 |
94 |
|
T19 |
13432 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2248955 |
1 |
|
|
T1 |
394 |
|
T13 |
17 |
|
T19 |
6045 |
| auto[1] |
auto[0] |
auto[1] |
328753 |
1 |
|
|
T1 |
14 |
|
T19 |
963 |
|
T105 |
108 |
| auto[1] |
auto[1] |
auto[0] |
2238560 |
1 |
|
|
T1 |
552 |
|
T13 |
77 |
|
T19 |
5518 |
| auto[1] |
auto[1] |
auto[1] |
327821 |
1 |
|
|
T1 |
17 |
|
T19 |
906 |
|
T105 |
78 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |