Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7388157 |
1 |
|
|
T1 |
1116 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5134046 |
1 |
|
|
T1 |
819 |
|
T13 |
131 |
|
T19 |
12808 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10397982 |
1 |
|
|
T1 |
1727 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
2124221 |
1 |
|
|
T1 |
208 |
|
T13 |
39 |
|
T15 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7374425 |
1 |
|
|
T1 |
1025 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5147778 |
1 |
|
|
T1 |
910 |
|
T13 |
110 |
|
T15 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1514679 |
1 |
|
|
T1 |
346 |
|
T13 |
18 |
|
T15 |
1 |
auto[1] |
auto[0] |
auto[1] |
1066913 |
1 |
|
|
T1 |
107 |
|
T13 |
21 |
|
T15 |
1 |
auto[1] |
auto[1] |
auto[0] |
1508878 |
1 |
|
|
T1 |
356 |
|
T13 |
53 |
|
T19 |
2604 |
auto[1] |
auto[1] |
auto[1] |
1057308 |
1 |
|
|
T1 |
101 |
|
T13 |
18 |
|
T19 |
3587 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7378606 |
1 |
|
|
T1 |
1039 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5143597 |
1 |
|
|
T1 |
896 |
|
T13 |
129 |
|
T19 |
13317 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10405356 |
1 |
|
|
T1 |
1660 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
2116847 |
1 |
|
|
T1 |
275 |
|
T13 |
26 |
|
T19 |
7593 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7398247 |
1 |
|
|
T1 |
979 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5123956 |
1 |
|
|
T1 |
956 |
|
T13 |
62 |
|
T19 |
12554 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1496843 |
1 |
|
|
T1 |
341 |
|
T13 |
7 |
|
T19 |
2404 |
auto[1] |
auto[0] |
auto[1] |
1054867 |
1 |
|
|
T1 |
153 |
|
T13 |
10 |
|
T19 |
3589 |
auto[1] |
auto[1] |
auto[0] |
1510266 |
1 |
|
|
T1 |
340 |
|
T13 |
29 |
|
T19 |
2557 |
auto[1] |
auto[1] |
auto[1] |
1061980 |
1 |
|
|
T1 |
122 |
|
T13 |
16 |
|
T19 |
4004 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7397101 |
1 |
|
|
T1 |
877 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5125102 |
1 |
|
|
T1 |
1058 |
|
T13 |
136 |
|
T15 |
3 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10397974 |
1 |
|
|
T1 |
1741 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
2124229 |
1 |
|
|
T1 |
194 |
|
T13 |
39 |
|
T19 |
6850 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7379601 |
1 |
|
|
T1 |
1059 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5142602 |
1 |
|
|
T1 |
876 |
|
T13 |
63 |
|
T19 |
11610 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1520976 |
1 |
|
|
T1 |
286 |
|
T13 |
9 |
|
T19 |
2230 |
auto[1] |
auto[0] |
auto[1] |
1067742 |
1 |
|
|
T1 |
89 |
|
T13 |
15 |
|
T19 |
3127 |
auto[1] |
auto[1] |
auto[0] |
1497397 |
1 |
|
|
T1 |
396 |
|
T13 |
15 |
|
T19 |
2530 |
auto[1] |
auto[1] |
auto[1] |
1056487 |
1 |
|
|
T1 |
105 |
|
T13 |
24 |
|
T19 |
3723 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7389047 |
1 |
|
|
T1 |
956 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5133156 |
1 |
|
|
T1 |
979 |
|
T13 |
43 |
|
T19 |
12187 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10403444 |
1 |
|
|
T1 |
1736 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
2118759 |
1 |
|
|
T1 |
199 |
|
T13 |
33 |
|
T19 |
6476 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7387367 |
1 |
|
|
T1 |
983 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5134836 |
1 |
|
|
T1 |
952 |
|
T13 |
67 |
|
T19 |
11194 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1526772 |
1 |
|
|
T1 |
378 |
|
T13 |
11 |
|
T19 |
2284 |
auto[1] |
auto[0] |
auto[1] |
1069165 |
1 |
|
|
T1 |
97 |
|
T13 |
21 |
|
T19 |
3098 |
auto[1] |
auto[1] |
auto[0] |
1489305 |
1 |
|
|
T1 |
375 |
|
T13 |
23 |
|
T19 |
2434 |
auto[1] |
auto[1] |
auto[1] |
1049594 |
1 |
|
|
T1 |
102 |
|
T13 |
12 |
|
T19 |
3378 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7389873 |
1 |
|
|
T1 |
998 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5132330 |
1 |
|
|
T1 |
937 |
|
T13 |
88 |
|
T19 |
11965 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10406508 |
1 |
|
|
T1 |
1762 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
2115695 |
1 |
|
|
T1 |
173 |
|
T13 |
42 |
|
T19 |
7211 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7400323 |
1 |
|
|
T1 |
783 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5121880 |
1 |
|
|
T1 |
1152 |
|
T13 |
100 |
|
T19 |
12456 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1504073 |
1 |
|
|
T1 |
523 |
|
T13 |
49 |
|
T19 |
2641 |
auto[1] |
auto[0] |
auto[1] |
1056839 |
1 |
|
|
T1 |
116 |
|
T13 |
15 |
|
T19 |
3626 |
auto[1] |
auto[1] |
auto[0] |
1502112 |
1 |
|
|
T1 |
456 |
|
T13 |
9 |
|
T19 |
2604 |
auto[1] |
auto[1] |
auto[1] |
1058856 |
1 |
|
|
T1 |
57 |
|
T13 |
27 |
|
T19 |
3585 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7377726 |
1 |
|
|
T1 |
1025 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5144477 |
1 |
|
|
T1 |
910 |
|
T13 |
150 |
|
T15 |
3 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10397187 |
1 |
|
|
T1 |
1739 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
2125016 |
1 |
|
|
T1 |
196 |
|
T13 |
18 |
|
T19 |
8160 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7387692 |
1 |
|
|
T1 |
1016 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5134511 |
1 |
|
|
T1 |
919 |
|
T13 |
142 |
|
T19 |
13436 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1509866 |
1 |
|
|
T1 |
376 |
|
T13 |
42 |
|
T19 |
2418 |
auto[1] |
auto[0] |
auto[1] |
1067413 |
1 |
|
|
T1 |
119 |
|
T19 |
3838 |
|
T105 |
339 |
auto[1] |
auto[1] |
auto[0] |
1499629 |
1 |
|
|
T1 |
347 |
|
T13 |
82 |
|
T19 |
2858 |
auto[1] |
auto[1] |
auto[1] |
1057603 |
1 |
|
|
T1 |
77 |
|
T13 |
18 |
|
T19 |
4322 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7373202 |
1 |
|
|
T1 |
1147 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5149001 |
1 |
|
|
T1 |
788 |
|
T13 |
67 |
|
T15 |
3 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10405944 |
1 |
|
|
T1 |
1656 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
2116259 |
1 |
|
|
T1 |
279 |
|
T13 |
29 |
|
T19 |
7883 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7410209 |
1 |
|
|
T1 |
927 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5111994 |
1 |
|
|
T1 |
1008 |
|
T13 |
115 |
|
T19 |
12837 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1510148 |
1 |
|
|
T1 |
423 |
|
T13 |
52 |
|
T19 |
2772 |
auto[1] |
auto[0] |
auto[1] |
1066210 |
1 |
|
|
T1 |
160 |
|
T13 |
13 |
|
T19 |
4220 |
auto[1] |
auto[1] |
auto[0] |
1485587 |
1 |
|
|
T1 |
306 |
|
T13 |
34 |
|
T19 |
2182 |
auto[1] |
auto[1] |
auto[1] |
1050049 |
1 |
|
|
T1 |
119 |
|
T13 |
16 |
|
T19 |
3663 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7402211 |
1 |
|
|
T1 |
865 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5119992 |
1 |
|
|
T1 |
1070 |
|
T13 |
155 |
|
T15 |
3 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10406895 |
1 |
|
|
T1 |
1769 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
2115308 |
1 |
|
|
T1 |
166 |
|
T13 |
21 |
|
T15 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7389244 |
1 |
|
|
T1 |
981 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5132959 |
1 |
|
|
T1 |
954 |
|
T13 |
138 |
|
T15 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1513522 |
1 |
|
|
T1 |
355 |
|
T13 |
30 |
|
T15 |
1 |
auto[1] |
auto[0] |
auto[1] |
1054116 |
1 |
|
|
T1 |
67 |
|
T13 |
5 |
|
T15 |
1 |
auto[1] |
auto[1] |
auto[0] |
1504129 |
1 |
|
|
T1 |
433 |
|
T13 |
87 |
|
T19 |
2674 |
auto[1] |
auto[1] |
auto[1] |
1061192 |
1 |
|
|
T1 |
99 |
|
T13 |
16 |
|
T19 |
3649 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7385048 |
1 |
|
|
T1 |
865 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5137155 |
1 |
|
|
T1 |
1070 |
|
T13 |
137 |
|
T19 |
12441 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10394179 |
1 |
|
|
T1 |
1674 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
2128024 |
1 |
|
|
T1 |
261 |
|
T13 |
14 |
|
T19 |
7696 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7366474 |
1 |
|
|
T1 |
843 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5155729 |
1 |
|
|
T1 |
1092 |
|
T13 |
98 |
|
T19 |
12859 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1526275 |
1 |
|
|
T1 |
334 |
|
T13 |
15 |
|
T19 |
2649 |
auto[1] |
auto[0] |
auto[1] |
1071880 |
1 |
|
|
T1 |
110 |
|
T13 |
10 |
|
T19 |
3738 |
auto[1] |
auto[1] |
auto[0] |
1501430 |
1 |
|
|
T1 |
497 |
|
T13 |
69 |
|
T19 |
2514 |
auto[1] |
auto[1] |
auto[1] |
1056144 |
1 |
|
|
T1 |
151 |
|
T13 |
4 |
|
T19 |
3958 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7381702 |
1 |
|
|
T1 |
899 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5140501 |
1 |
|
|
T1 |
1036 |
|
T13 |
86 |
|
T15 |
3 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10395476 |
1 |
|
|
T1 |
1710 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
2126727 |
1 |
|
|
T1 |
225 |
|
T13 |
7 |
|
T19 |
7558 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7371111 |
1 |
|
|
T1 |
916 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5151092 |
1 |
|
|
T1 |
1019 |
|
T13 |
90 |
|
T19 |
12322 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1506463 |
1 |
|
|
T1 |
359 |
|
T13 |
48 |
|
T19 |
2404 |
auto[1] |
auto[0] |
auto[1] |
1062450 |
1 |
|
|
T1 |
111 |
|
T13 |
3 |
|
T19 |
3755 |
auto[1] |
auto[1] |
auto[0] |
1517902 |
1 |
|
|
T1 |
435 |
|
T13 |
35 |
|
T19 |
2360 |
auto[1] |
auto[1] |
auto[1] |
1064277 |
1 |
|
|
T1 |
114 |
|
T13 |
4 |
|
T19 |
3803 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7362377 |
1 |
|
|
T1 |
971 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5159826 |
1 |
|
|
T1 |
964 |
|
T13 |
76 |
|
T19 |
11145 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10398576 |
1 |
|
|
T1 |
1736 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
2123627 |
1 |
|
|
T1 |
199 |
|
T13 |
6 |
|
T19 |
7668 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7372948 |
1 |
|
|
T1 |
1082 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5149255 |
1 |
|
|
T1 |
853 |
|
T13 |
51 |
|
T19 |
12923 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1516555 |
1 |
|
|
T1 |
335 |
|
T13 |
19 |
|
T19 |
2881 |
auto[1] |
auto[0] |
auto[1] |
1063762 |
1 |
|
|
T1 |
121 |
|
T19 |
4333 |
|
T105 |
295 |
auto[1] |
auto[1] |
auto[0] |
1509073 |
1 |
|
|
T1 |
319 |
|
T13 |
26 |
|
T19 |
2374 |
auto[1] |
auto[1] |
auto[1] |
1059865 |
1 |
|
|
T1 |
78 |
|
T13 |
6 |
|
T19 |
3335 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7369553 |
1 |
|
|
T1 |
842 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5152650 |
1 |
|
|
T1 |
1093 |
|
T13 |
74 |
|
T15 |
3 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10394891 |
1 |
|
|
T1 |
1683 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
2127312 |
1 |
|
|
T1 |
252 |
|
T13 |
17 |
|
T19 |
6725 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7365714 |
1 |
|
|
T1 |
968 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5156489 |
1 |
|
|
T1 |
967 |
|
T13 |
54 |
|
T19 |
11376 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1518831 |
1 |
|
|
T1 |
327 |
|
T13 |
19 |
|
T19 |
1788 |
auto[1] |
auto[0] |
auto[1] |
1064365 |
1 |
|
|
T1 |
118 |
|
T13 |
16 |
|
T19 |
2808 |
auto[1] |
auto[1] |
auto[0] |
1510346 |
1 |
|
|
T1 |
388 |
|
T13 |
18 |
|
T19 |
2863 |
auto[1] |
auto[1] |
auto[1] |
1062947 |
1 |
|
|
T1 |
134 |
|
T13 |
1 |
|
T19 |
3917 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7405543 |
1 |
|
|
T1 |
897 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5116660 |
1 |
|
|
T1 |
1038 |
|
T13 |
70 |
|
T19 |
12753 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10404784 |
1 |
|
|
T1 |
1684 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
2117419 |
1 |
|
|
T1 |
251 |
|
T13 |
10 |
|
T19 |
7037 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7392976 |
1 |
|
|
T1 |
884 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5129227 |
1 |
|
|
T1 |
1051 |
|
T13 |
27 |
|
T15 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1519685 |
1 |
|
|
T1 |
399 |
|
T13 |
15 |
|
T15 |
2 |
auto[1] |
auto[0] |
auto[1] |
1063924 |
1 |
|
|
T1 |
112 |
|
T13 |
10 |
|
T19 |
3619 |
auto[1] |
auto[1] |
auto[0] |
1492123 |
1 |
|
|
T1 |
401 |
|
T13 |
2 |
|
T19 |
2375 |
auto[1] |
auto[1] |
auto[1] |
1053495 |
1 |
|
|
T1 |
139 |
|
T19 |
3418 |
|
T105 |
204 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7378985 |
1 |
|
|
T1 |
811 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5143218 |
1 |
|
|
T1 |
1124 |
|
T13 |
102 |
|
T19 |
12553 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10389951 |
1 |
|
|
T1 |
1805 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
2132252 |
1 |
|
|
T1 |
130 |
|
T13 |
46 |
|
T15 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7358384 |
1 |
|
|
T1 |
1183 |
|
T11 |
44 |
|
T12 |
31 |
auto[1] |
5163819 |
1 |
|
|
T1 |
752 |
|
T13 |
106 |
|
T15 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1514357 |
1 |
|
|
T1 |
218 |
|
T13 |
40 |
|
T15 |
1 |
auto[1] |
auto[0] |
auto[1] |
1067909 |
1 |
|
|
T1 |
61 |
|
T13 |
8 |
|
T15 |
1 |
auto[1] |
auto[1] |
auto[0] |
1517210 |
1 |
|
|
T1 |
404 |
|
T13 |
20 |
|
T19 |
2460 |
auto[1] |
auto[1] |
auto[1] |
1064343 |
1 |
|
|
T1 |
69 |
|
T13 |
38 |
|
T19 |
3818 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |