Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 939
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T762 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.4193989828 Jul 14 05:05:30 PM PDT 24 Jul 14 05:05:32 PM PDT 24 93259202 ps
T763 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.695852435 Jul 14 05:06:08 PM PDT 24 Jul 14 05:06:10 PM PDT 24 87606651 ps
T764 /workspace/coverage/cover_reg_top/3.gpio_intr_test.3209590426 Jul 14 05:05:00 PM PDT 24 Jul 14 05:05:01 PM PDT 24 14038218 ps
T765 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.4145791601 Jul 14 05:04:29 PM PDT 24 Jul 14 05:04:32 PM PDT 24 58900748 ps
T104 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.4272811401 Jul 14 05:05:45 PM PDT 24 Jul 14 05:05:47 PM PDT 24 79620567 ps
T766 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.44342733 Jul 14 05:06:01 PM PDT 24 Jul 14 05:06:02 PM PDT 24 11911230 ps
T767 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2678932032 Jul 14 05:04:53 PM PDT 24 Jul 14 05:04:54 PM PDT 24 198950256 ps
T768 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.652767989 Jul 14 05:05:08 PM PDT 24 Jul 14 05:05:10 PM PDT 24 21910125 ps
T769 /workspace/coverage/cover_reg_top/27.gpio_intr_test.1620321488 Jul 14 05:06:08 PM PDT 24 Jul 14 05:06:09 PM PDT 24 50082552 ps
T770 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.4063491975 Jul 14 05:05:08 PM PDT 24 Jul 14 05:05:10 PM PDT 24 45933669 ps
T771 /workspace/coverage/cover_reg_top/39.gpio_intr_test.551755971 Jul 14 05:06:17 PM PDT 24 Jul 14 05:06:19 PM PDT 24 43947826 ps
T772 /workspace/coverage/cover_reg_top/38.gpio_intr_test.201500492 Jul 14 05:06:15 PM PDT 24 Jul 14 05:06:17 PM PDT 24 17449491 ps
T38 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1468230219 Jul 14 05:05:55 PM PDT 24 Jul 14 05:05:57 PM PDT 24 156089375 ps
T773 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2084077801 Jul 14 05:04:40 PM PDT 24 Jul 14 05:04:42 PM PDT 24 69914651 ps
T774 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1180923957 Jul 14 05:04:21 PM PDT 24 Jul 14 05:04:23 PM PDT 24 17041256 ps
T775 /workspace/coverage/cover_reg_top/21.gpio_intr_test.2865703344 Jul 14 05:06:07 PM PDT 24 Jul 14 05:06:08 PM PDT 24 44933890 ps
T776 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1800529839 Jul 14 05:06:09 PM PDT 24 Jul 14 05:06:11 PM PDT 24 18613871 ps
T777 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3972081476 Jul 14 05:05:40 PM PDT 24 Jul 14 05:05:42 PM PDT 24 14457822 ps
T778 /workspace/coverage/cover_reg_top/18.gpio_intr_test.1875212497 Jul 14 05:06:03 PM PDT 24 Jul 14 05:06:04 PM PDT 24 39864395 ps
T85 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2061724029 Jul 14 05:05:00 PM PDT 24 Jul 14 05:05:02 PM PDT 24 37746403 ps
T103 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.315736170 Jul 14 05:06:00 PM PDT 24 Jul 14 05:06:02 PM PDT 24 130448122 ps
T779 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.950507264 Jul 14 05:05:49 PM PDT 24 Jul 14 05:05:51 PM PDT 24 79741462 ps
T780 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1629842643 Jul 14 05:05:24 PM PDT 24 Jul 14 05:05:26 PM PDT 24 112198363 ps
T781 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2869309698 Jul 14 05:04:36 PM PDT 24 Jul 14 05:04:38 PM PDT 24 29733270 ps
T782 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2765743449 Jul 14 05:04:55 PM PDT 24 Jul 14 05:04:56 PM PDT 24 154710370 ps
T783 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.659508212 Jul 14 05:05:25 PM PDT 24 Jul 14 05:05:26 PM PDT 24 26598820 ps
T784 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1323321117 Jul 14 05:05:31 PM PDT 24 Jul 14 05:05:32 PM PDT 24 13151992 ps
T86 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3921728587 Jul 14 05:06:01 PM PDT 24 Jul 14 05:06:02 PM PDT 24 35006610 ps
T785 /workspace/coverage/cover_reg_top/22.gpio_intr_test.870703483 Jul 14 05:06:09 PM PDT 24 Jul 14 05:06:10 PM PDT 24 37352194 ps
T786 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.872086937 Jul 14 05:05:10 PM PDT 24 Jul 14 05:05:11 PM PDT 24 18863979 ps
T787 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.993111248 Jul 14 05:05:53 PM PDT 24 Jul 14 05:05:56 PM PDT 24 555554531 ps
T788 /workspace/coverage/cover_reg_top/40.gpio_intr_test.2686825663 Jul 14 05:06:16 PM PDT 24 Jul 14 05:06:17 PM PDT 24 17176540 ps
T789 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2717855531 Jul 14 05:05:24 PM PDT 24 Jul 14 05:05:27 PM PDT 24 177548927 ps
T790 /workspace/coverage/cover_reg_top/17.gpio_intr_test.279550962 Jul 14 05:06:00 PM PDT 24 Jul 14 05:06:02 PM PDT 24 53201309 ps
T791 /workspace/coverage/cover_reg_top/43.gpio_intr_test.446871293 Jul 14 05:06:15 PM PDT 24 Jul 14 05:06:16 PM PDT 24 27089753 ps
T792 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.4146000436 Jul 14 05:05:38 PM PDT 24 Jul 14 05:05:40 PM PDT 24 34981975 ps
T793 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1316348243 Jul 14 05:05:34 PM PDT 24 Jul 14 05:05:35 PM PDT 24 280248583 ps
T794 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.4272035484 Jul 14 05:05:00 PM PDT 24 Jul 14 05:05:02 PM PDT 24 71354116 ps
T795 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.539061826 Jul 14 05:05:31 PM PDT 24 Jul 14 05:05:33 PM PDT 24 379291160 ps
T87 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2302110945 Jul 14 05:05:29 PM PDT 24 Jul 14 05:05:30 PM PDT 24 11236549 ps
T796 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.687239408 Jul 14 05:05:18 PM PDT 24 Jul 14 05:05:20 PM PDT 24 37899347 ps
T797 /workspace/coverage/cover_reg_top/4.gpio_intr_test.2111905101 Jul 14 05:05:09 PM PDT 24 Jul 14 05:05:10 PM PDT 24 27534327 ps
T798 /workspace/coverage/cover_reg_top/48.gpio_intr_test.872338997 Jul 14 05:06:23 PM PDT 24 Jul 14 05:06:24 PM PDT 24 92518276 ps
T799 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.745195717 Jul 14 05:06:01 PM PDT 24 Jul 14 05:06:03 PM PDT 24 37273760 ps
T800 /workspace/coverage/cover_reg_top/1.gpio_intr_test.218941663 Jul 14 05:04:44 PM PDT 24 Jul 14 05:04:45 PM PDT 24 39311469 ps
T801 /workspace/coverage/cover_reg_top/2.gpio_intr_test.2024945497 Jul 14 05:04:52 PM PDT 24 Jul 14 05:04:53 PM PDT 24 15769050 ps
T802 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1134516941 Jul 14 05:05:46 PM PDT 24 Jul 14 05:05:48 PM PDT 24 11132804 ps
T88 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.658291826 Jul 14 05:04:46 PM PDT 24 Jul 14 05:04:46 PM PDT 24 83708753 ps
T803 /workspace/coverage/cover_reg_top/11.gpio_intr_test.2348647256 Jul 14 05:05:38 PM PDT 24 Jul 14 05:05:39 PM PDT 24 28483019 ps
T804 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1366549633 Jul 14 05:05:40 PM PDT 24 Jul 14 05:05:41 PM PDT 24 39477810 ps
T805 /workspace/coverage/cover_reg_top/32.gpio_intr_test.2086957300 Jul 14 05:06:08 PM PDT 24 Jul 14 05:06:09 PM PDT 24 56211109 ps
T806 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2095388369 Jul 14 05:05:00 PM PDT 24 Jul 14 05:05:03 PM PDT 24 344548296 ps
T807 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3013625873 Jul 14 05:06:00 PM PDT 24 Jul 14 05:06:02 PM PDT 24 75556677 ps
T808 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3133859369 Jul 14 05:04:53 PM PDT 24 Jul 14 05:04:57 PM PDT 24 260042092 ps
T809 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3013945761 Jul 14 05:05:08 PM PDT 24 Jul 14 05:05:10 PM PDT 24 120935948 ps
T810 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.850969809 Jul 14 05:04:37 PM PDT 24 Jul 14 05:04:38 PM PDT 24 116014048 ps
T811 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2078057045 Jul 14 05:05:30 PM PDT 24 Jul 14 05:05:31 PM PDT 24 40349050 ps
T812 /workspace/coverage/cover_reg_top/41.gpio_intr_test.1445087872 Jul 14 05:06:16 PM PDT 24 Jul 14 05:06:17 PM PDT 24 42074112 ps
T813 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3924625053 Jul 14 05:05:16 PM PDT 24 Jul 14 05:05:18 PM PDT 24 147984191 ps
T814 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1310498109 Jul 14 05:05:38 PM PDT 24 Jul 14 05:05:40 PM PDT 24 61118287 ps
T815 /workspace/coverage/cover_reg_top/10.gpio_intr_test.3839251173 Jul 14 05:05:32 PM PDT 24 Jul 14 05:05:33 PM PDT 24 28807147 ps
T816 /workspace/coverage/cover_reg_top/34.gpio_intr_test.66632926 Jul 14 05:06:14 PM PDT 24 Jul 14 05:06:15 PM PDT 24 32953407 ps
T817 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2031055550 Jul 14 05:05:08 PM PDT 24 Jul 14 05:05:09 PM PDT 24 70474796 ps
T818 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.920701844 Jul 14 05:05:46 PM PDT 24 Jul 14 05:05:49 PM PDT 24 46475380 ps
T819 /workspace/coverage/cover_reg_top/5.gpio_intr_test.2911120281 Jul 14 05:05:08 PM PDT 24 Jul 14 05:05:09 PM PDT 24 22808177 ps
T89 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3237736006 Jul 14 05:04:53 PM PDT 24 Jul 14 05:04:54 PM PDT 24 23779295 ps
T820 /workspace/coverage/cover_reg_top/47.gpio_intr_test.917564790 Jul 14 05:06:23 PM PDT 24 Jul 14 05:06:23 PM PDT 24 12996043 ps
T821 /workspace/coverage/cover_reg_top/15.gpio_intr_test.3115100027 Jul 14 05:05:46 PM PDT 24 Jul 14 05:05:48 PM PDT 24 69221523 ps
T822 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.469727292 Jul 14 05:05:15 PM PDT 24 Jul 14 05:05:16 PM PDT 24 53449761 ps
T90 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1242780510 Jul 14 05:04:54 PM PDT 24 Jul 14 05:04:55 PM PDT 24 20111588 ps
T823 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2921323802 Jul 14 05:05:32 PM PDT 24 Jul 14 05:05:33 PM PDT 24 45868230 ps
T91 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2671076079 Jul 14 05:04:21 PM PDT 24 Jul 14 05:04:22 PM PDT 24 18969547 ps
T824 /workspace/coverage/cover_reg_top/20.gpio_intr_test.1231621252 Jul 14 05:06:09 PM PDT 24 Jul 14 05:06:11 PM PDT 24 18028639 ps
T825 /workspace/coverage/cover_reg_top/16.gpio_intr_test.1180514006 Jul 14 05:05:52 PM PDT 24 Jul 14 05:05:54 PM PDT 24 13173429 ps
T826 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3341539449 Jul 14 05:05:46 PM PDT 24 Jul 14 05:05:47 PM PDT 24 46471928 ps
T92 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.887971822 Jul 14 05:05:08 PM PDT 24 Jul 14 05:05:09 PM PDT 24 56988300 ps
T827 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.634435490 Jul 14 05:05:53 PM PDT 24 Jul 14 05:05:55 PM PDT 24 13860054 ps
T828 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1369134688 Jul 14 05:04:22 PM PDT 24 Jul 14 05:04:23 PM PDT 24 89427418 ps
T829 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3567653940 Jul 14 05:04:37 PM PDT 24 Jul 14 05:04:39 PM PDT 24 17500313 ps
T830 /workspace/coverage/cover_reg_top/12.gpio_intr_test.1531966446 Jul 14 05:05:39 PM PDT 24 Jul 14 05:05:40 PM PDT 24 18655271 ps
T831 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2815795359 Jul 14 05:05:53 PM PDT 24 Jul 14 05:05:54 PM PDT 24 32636857 ps
T832 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3723615940 Jul 14 05:05:39 PM PDT 24 Jul 14 05:05:41 PM PDT 24 806225345 ps
T833 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.4055870320 Jul 14 05:05:38 PM PDT 24 Jul 14 05:05:39 PM PDT 24 88884687 ps
T834 /workspace/coverage/cover_reg_top/9.gpio_intr_test.2651039075 Jul 14 05:05:32 PM PDT 24 Jul 14 05:05:34 PM PDT 24 40559135 ps
T835 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1521747785 Jul 14 05:05:46 PM PDT 24 Jul 14 05:05:47 PM PDT 24 15645867 ps
T836 /workspace/coverage/cover_reg_top/0.gpio_intr_test.3312401064 Jul 14 05:04:29 PM PDT 24 Jul 14 05:04:30 PM PDT 24 13863298 ps
T837 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.4129234177 Jul 14 05:05:40 PM PDT 24 Jul 14 05:05:41 PM PDT 24 107689058 ps
T838 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3030120577 Jul 14 05:05:10 PM PDT 24 Jul 14 05:05:12 PM PDT 24 37362159 ps
T839 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1975349926 Jul 14 05:06:00 PM PDT 24 Jul 14 05:06:04 PM PDT 24 736176434 ps
T840 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3104741337 Jul 14 04:22:45 PM PDT 24 Jul 14 04:22:49 PM PDT 24 105051581 ps
T841 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3491847861 Jul 14 04:22:25 PM PDT 24 Jul 14 04:22:27 PM PDT 24 60245724 ps
T842 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1851057196 Jul 14 04:18:03 PM PDT 24 Jul 14 04:18:05 PM PDT 24 42188583 ps
T843 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.236317119 Jul 14 04:23:29 PM PDT 24 Jul 14 04:23:32 PM PDT 24 176461699 ps
T844 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.903547884 Jul 14 04:23:18 PM PDT 24 Jul 14 04:23:20 PM PDT 24 101485510 ps
T845 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2997649456 Jul 14 04:23:22 PM PDT 24 Jul 14 04:23:25 PM PDT 24 65904873 ps
T846 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1210699147 Jul 14 04:22:27 PM PDT 24 Jul 14 04:22:31 PM PDT 24 224439869 ps
T847 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1700759220 Jul 14 04:22:40 PM PDT 24 Jul 14 04:22:43 PM PDT 24 207027324 ps
T848 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2896731566 Jul 14 04:23:16 PM PDT 24 Jul 14 04:23:18 PM PDT 24 47958920 ps
T849 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1887517192 Jul 14 04:23:22 PM PDT 24 Jul 14 04:23:25 PM PDT 24 37350144 ps
T850 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3259207755 Jul 14 04:23:28 PM PDT 24 Jul 14 04:23:30 PM PDT 24 190527780 ps
T851 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1863768749 Jul 14 04:23:27 PM PDT 24 Jul 14 04:23:29 PM PDT 24 51129835 ps
T852 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1040699204 Jul 14 04:23:23 PM PDT 24 Jul 14 04:23:26 PM PDT 24 76862073 ps
T853 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2559083531 Jul 14 04:23:27 PM PDT 24 Jul 14 04:23:29 PM PDT 24 398775664 ps
T854 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2460591594 Jul 14 04:22:18 PM PDT 24 Jul 14 04:22:20 PM PDT 24 225662616 ps
T855 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2288698618 Jul 14 04:23:28 PM PDT 24 Jul 14 04:23:31 PM PDT 24 70503274 ps
T856 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3013979285 Jul 14 04:23:23 PM PDT 24 Jul 14 04:23:25 PM PDT 24 64841633 ps
T857 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1216213668 Jul 14 04:21:44 PM PDT 24 Jul 14 04:21:47 PM PDT 24 272143449 ps
T858 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.407388056 Jul 14 04:22:07 PM PDT 24 Jul 14 04:22:09 PM PDT 24 161816842 ps
T859 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.156711044 Jul 14 04:23:13 PM PDT 24 Jul 14 04:23:15 PM PDT 24 158625066 ps
T860 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.459513491 Jul 14 04:22:17 PM PDT 24 Jul 14 04:22:19 PM PDT 24 153915362 ps
T861 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3670216402 Jul 14 04:23:18 PM PDT 24 Jul 14 04:23:20 PM PDT 24 129533338 ps
T862 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3388918174 Jul 14 04:23:12 PM PDT 24 Jul 14 04:23:14 PM PDT 24 525858320 ps
T863 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.426768717 Jul 14 04:18:16 PM PDT 24 Jul 14 04:18:17 PM PDT 24 138293078 ps
T864 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3304973592 Jul 14 04:23:13 PM PDT 24 Jul 14 04:23:16 PM PDT 24 266040379 ps
T865 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2137631649 Jul 14 04:22:29 PM PDT 24 Jul 14 04:22:31 PM PDT 24 38844701 ps
T866 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1436787585 Jul 14 04:23:21 PM PDT 24 Jul 14 04:23:23 PM PDT 24 380162715 ps
T867 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3972678592 Jul 14 04:23:15 PM PDT 24 Jul 14 04:23:17 PM PDT 24 53147125 ps
T868 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1304808086 Jul 14 04:23:28 PM PDT 24 Jul 14 04:23:30 PM PDT 24 426372627 ps
T869 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2901808900 Jul 14 04:23:13 PM PDT 24 Jul 14 04:23:15 PM PDT 24 104832379 ps
T870 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1741848411 Jul 14 04:18:06 PM PDT 24 Jul 14 04:18:08 PM PDT 24 77934860 ps
T871 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1441647048 Jul 14 04:23:20 PM PDT 24 Jul 14 04:23:22 PM PDT 24 197053073 ps
T872 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1554884203 Jul 14 04:23:30 PM PDT 24 Jul 14 04:23:33 PM PDT 24 53027488 ps
T873 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1743334299 Jul 14 04:23:23 PM PDT 24 Jul 14 04:23:26 PM PDT 24 114602815 ps
T874 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.4185791047 Jul 14 04:23:13 PM PDT 24 Jul 14 04:23:14 PM PDT 24 29297250 ps
T875 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1084797053 Jul 14 04:17:48 PM PDT 24 Jul 14 04:17:50 PM PDT 24 185588382 ps
T876 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.4023942907 Jul 14 04:23:30 PM PDT 24 Jul 14 04:23:33 PM PDT 24 450604515 ps
T877 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2515422843 Jul 14 04:23:22 PM PDT 24 Jul 14 04:23:25 PM PDT 24 108664621 ps
T878 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1760922813 Jul 14 04:23:17 PM PDT 24 Jul 14 04:23:19 PM PDT 24 680240333 ps
T879 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2515530966 Jul 14 04:22:20 PM PDT 24 Jul 14 04:22:22 PM PDT 24 42531321 ps
T880 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1611395085 Jul 14 04:23:01 PM PDT 24 Jul 14 04:23:04 PM PDT 24 34477007 ps
T881 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2836387223 Jul 14 04:21:11 PM PDT 24 Jul 14 04:21:12 PM PDT 24 151090257 ps
T882 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.107127054 Jul 14 04:22:40 PM PDT 24 Jul 14 04:22:43 PM PDT 24 395381019 ps
T883 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.765218796 Jul 14 04:23:21 PM PDT 24 Jul 14 04:23:23 PM PDT 24 333746075 ps
T884 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3861161231 Jul 14 04:20:21 PM PDT 24 Jul 14 04:20:22 PM PDT 24 76277204 ps
T885 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3598776332 Jul 14 04:23:23 PM PDT 24 Jul 14 04:23:25 PM PDT 24 125468856 ps
T886 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3369276537 Jul 14 04:23:21 PM PDT 24 Jul 14 04:23:23 PM PDT 24 147444219 ps
T887 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1988864334 Jul 14 04:23:20 PM PDT 24 Jul 14 04:23:22 PM PDT 24 33534853 ps
T888 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.559246456 Jul 14 04:23:23 PM PDT 24 Jul 14 04:23:25 PM PDT 24 65153226 ps
T889 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3638435685 Jul 14 04:23:26 PM PDT 24 Jul 14 04:23:27 PM PDT 24 204377965 ps
T890 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.783573745 Jul 14 04:23:19 PM PDT 24 Jul 14 04:23:22 PM PDT 24 28916089 ps
T891 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3427498879 Jul 14 04:22:31 PM PDT 24 Jul 14 04:22:35 PM PDT 24 142043870 ps
T892 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.670061683 Jul 14 04:22:46 PM PDT 24 Jul 14 04:22:48 PM PDT 24 39274896 ps
T893 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2876774996 Jul 14 04:23:21 PM PDT 24 Jul 14 04:23:23 PM PDT 24 87681370 ps
T894 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3879748117 Jul 14 04:23:22 PM PDT 24 Jul 14 04:23:25 PM PDT 24 57854263 ps
T895 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2314629802 Jul 14 04:17:28 PM PDT 24 Jul 14 04:17:30 PM PDT 24 48960781 ps
T896 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.623160063 Jul 14 04:23:13 PM PDT 24 Jul 14 04:23:16 PM PDT 24 74650700 ps
T897 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.177250588 Jul 14 04:23:29 PM PDT 24 Jul 14 04:23:32 PM PDT 24 48542606 ps
T898 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1534179696 Jul 14 04:21:34 PM PDT 24 Jul 14 04:21:35 PM PDT 24 162642752 ps
T899 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.974765455 Jul 14 04:23:08 PM PDT 24 Jul 14 04:23:10 PM PDT 24 914262222 ps
T900 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1685039721 Jul 14 04:23:19 PM PDT 24 Jul 14 04:23:22 PM PDT 24 140656885 ps
T901 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1192648698 Jul 14 04:23:30 PM PDT 24 Jul 14 04:23:33 PM PDT 24 61023729 ps
T902 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1070166598 Jul 14 04:21:53 PM PDT 24 Jul 14 04:21:57 PM PDT 24 130652978 ps
T903 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.756338345 Jul 14 04:23:26 PM PDT 24 Jul 14 04:23:28 PM PDT 24 156790957 ps
T904 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2960225548 Jul 14 04:23:20 PM PDT 24 Jul 14 04:23:22 PM PDT 24 612948922 ps
T905 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1399647349 Jul 14 04:20:57 PM PDT 24 Jul 14 04:20:58 PM PDT 24 225606803 ps
T906 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2198172861 Jul 14 04:23:23 PM PDT 24 Jul 14 04:23:25 PM PDT 24 226184724 ps
T907 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2081618800 Jul 14 04:23:31 PM PDT 24 Jul 14 04:23:35 PM PDT 24 172801405 ps
T908 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1579344429 Jul 14 04:23:28 PM PDT 24 Jul 14 04:23:30 PM PDT 24 78878977 ps
T909 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2525217911 Jul 14 04:21:59 PM PDT 24 Jul 14 04:22:02 PM PDT 24 286445933 ps
T910 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.904367519 Jul 14 04:23:13 PM PDT 24 Jul 14 04:23:16 PM PDT 24 123741577 ps
T911 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2613159854 Jul 14 04:22:20 PM PDT 24 Jul 14 04:22:22 PM PDT 24 26258379 ps
T912 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.80167490 Jul 14 04:23:28 PM PDT 24 Jul 14 04:23:30 PM PDT 24 33298127 ps
T913 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.217778769 Jul 14 04:18:36 PM PDT 24 Jul 14 04:18:38 PM PDT 24 311091615 ps
T914 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.762991786 Jul 14 04:18:51 PM PDT 24 Jul 14 04:18:52 PM PDT 24 68731450 ps
T915 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2552812204 Jul 14 04:23:31 PM PDT 24 Jul 14 04:23:35 PM PDT 24 222755388 ps
T916 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.4150705958 Jul 14 04:22:29 PM PDT 24 Jul 14 04:22:31 PM PDT 24 38943047 ps
T917 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2486452224 Jul 14 04:23:21 PM PDT 24 Jul 14 04:23:23 PM PDT 24 30159036 ps
T918 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.132064613 Jul 14 04:23:24 PM PDT 24 Jul 14 04:23:26 PM PDT 24 48831331 ps
T919 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3501276137 Jul 14 04:23:15 PM PDT 24 Jul 14 04:23:17 PM PDT 24 379565054 ps
T920 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.725647916 Jul 14 04:22:18 PM PDT 24 Jul 14 04:22:20 PM PDT 24 140822030 ps
T921 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.507042446 Jul 14 04:23:17 PM PDT 24 Jul 14 04:23:20 PM PDT 24 95135794 ps
T922 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2455366946 Jul 14 04:22:33 PM PDT 24 Jul 14 04:22:36 PM PDT 24 123590639 ps
T923 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4119964985 Jul 14 04:23:21 PM PDT 24 Jul 14 04:23:24 PM PDT 24 307752116 ps
T924 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2655392050 Jul 14 04:23:22 PM PDT 24 Jul 14 04:23:25 PM PDT 24 479658894 ps
T925 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3093557659 Jul 14 04:22:49 PM PDT 24 Jul 14 04:22:51 PM PDT 24 105011890 ps
T926 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1752491447 Jul 14 04:23:18 PM PDT 24 Jul 14 04:23:21 PM PDT 24 88082638 ps
T927 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.548195719 Jul 14 04:17:55 PM PDT 24 Jul 14 04:17:57 PM PDT 24 170714113 ps
T928 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.130594174 Jul 14 04:21:53 PM PDT 24 Jul 14 04:21:56 PM PDT 24 165983015 ps
T929 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.415337018 Jul 14 04:21:58 PM PDT 24 Jul 14 04:22:01 PM PDT 24 134072571 ps
T930 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.222738768 Jul 14 04:21:45 PM PDT 24 Jul 14 04:21:47 PM PDT 24 172020152 ps
T931 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2121065395 Jul 14 04:18:46 PM PDT 24 Jul 14 04:18:48 PM PDT 24 68384165 ps
T932 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1623220940 Jul 14 04:21:45 PM PDT 24 Jul 14 04:21:47 PM PDT 24 220475669 ps
T933 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.530211114 Jul 14 04:23:27 PM PDT 24 Jul 14 04:23:29 PM PDT 24 236718290 ps
T934 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1665456942 Jul 14 04:23:31 PM PDT 24 Jul 14 04:23:35 PM PDT 24 84569452 ps
T935 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2584925317 Jul 14 04:23:13 PM PDT 24 Jul 14 04:23:16 PM PDT 24 299012436 ps
T936 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1996071398 Jul 14 04:23:13 PM PDT 24 Jul 14 04:23:16 PM PDT 24 310354081 ps
T937 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1170470851 Jul 14 04:23:13 PM PDT 24 Jul 14 04:23:15 PM PDT 24 31948294 ps
T938 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1466796370 Jul 14 04:23:25 PM PDT 24 Jul 14 04:23:27 PM PDT 24 625769609 ps
T939 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3701475164 Jul 14 04:23:01 PM PDT 24 Jul 14 04:23:04 PM PDT 24 78784876 ps

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.624963106
Short name T1
Test name
Test status
Simulation time 933567838 ps
CPU time 5.31 seconds
Started Jul 14 05:19:25 PM PDT 24
Finished Jul 14 05:19:32 PM PDT 24
Peak memory 198516 kb
Host smart-01bdfcea-b350-458d-9ae2-1695a10a961b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624963106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ran
dom_long_reg_writes_reg_reads.624963106
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.2887071535
Short name T16
Test name
Test status
Simulation time 45424191 ps
CPU time 1.88 seconds
Started Jul 14 05:18:53 PM PDT 24
Finished Jul 14 05:18:55 PM PDT 24
Peak memory 197396 kb
Host smart-822fc7fc-187d-465b-9394-074dde60a309
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887071535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.2887071535
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.2361869776
Short name T23
Test name
Test status
Simulation time 9615212199 ps
CPU time 170.5 seconds
Started Jul 14 05:22:10 PM PDT 24
Finished Jul 14 05:25:01 PM PDT 24
Peak memory 206968 kb
Host smart-3aed7f4a-91b3-47f1-840e-ec240abfd497
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2361869776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.2361869776
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.1979397830
Short name T29
Test name
Test status
Simulation time 102726883 ps
CPU time 1 seconds
Started Jul 14 05:17:17 PM PDT 24
Finished Jul 14 05:17:18 PM PDT 24
Peak memory 215328 kb
Host smart-baaa5ba5-722f-4184-9ef2-4aeca5a43ce4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979397830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.1979397830
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3137745835
Short name T77
Test name
Test status
Simulation time 20364931 ps
CPU time 0.66 seconds
Started Jul 14 05:04:54 PM PDT 24
Finished Jul 14 05:04:56 PM PDT 24
Peak memory 196076 kb
Host smart-c59c09ae-abe0-4c32-9d0c-cd96b3166c1d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137745835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.3137745835
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2278832282
Short name T28
Test name
Test status
Simulation time 207075103 ps
CPU time 1.46 seconds
Started Jul 14 05:05:45 PM PDT 24
Finished Jul 14 05:05:48 PM PDT 24
Peak memory 198628 kb
Host smart-335ced27-e853-4b59-be47-aa144e2ed72e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278832282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2278832282
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/12.gpio_alert_test.14322880
Short name T236
Test name
Test status
Simulation time 14217113 ps
CPU time 0.6 seconds
Started Jul 14 05:18:52 PM PDT 24
Finished Jul 14 05:18:53 PM PDT 24
Peak memory 194756 kb
Host smart-75ed23f7-912a-430a-a2f9-b62387305268
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14322880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.14322880
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.4229907530
Short name T100
Test name
Test status
Simulation time 23602625 ps
CPU time 0.67 seconds
Started Jul 14 05:05:31 PM PDT 24
Finished Jul 14 05:05:33 PM PDT 24
Peak memory 195456 kb
Host smart-97c7bc9d-1007-44f0-ad5f-c049fe6d9acd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229907530 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.4229907530
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1612709799
Short name T36
Test name
Test status
Simulation time 585048892 ps
CPU time 1.45 seconds
Started Jul 14 05:06:02 PM PDT 24
Finished Jul 14 05:06:04 PM PDT 24
Peak memory 198592 kb
Host smart-0fde7160-935b-4b14-a2aa-cff68bb1186a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612709799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1612709799
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1180923957
Short name T774
Test name
Test status
Simulation time 17041256 ps
CPU time 0.82 seconds
Started Jul 14 05:04:21 PM PDT 24
Finished Jul 14 05:04:23 PM PDT 24
Peak memory 196448 kb
Host smart-b4e8ecb5-af4e-47db-ab3c-59359ad20efa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180923957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1180923957
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3618971021
Short name T738
Test name
Test status
Simulation time 373435451 ps
CPU time 1.47 seconds
Started Jul 14 05:04:29 PM PDT 24
Finished Jul 14 05:04:31 PM PDT 24
Peak memory 197256 kb
Host smart-313c93ac-fc29-4855-88fc-fd80127ca47b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618971021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3618971021
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2089948860
Short name T731
Test name
Test status
Simulation time 48813734 ps
CPU time 0.61 seconds
Started Jul 14 05:04:30 PM PDT 24
Finished Jul 14 05:04:31 PM PDT 24
Peak memory 195384 kb
Host smart-d533f1a8-a10c-4482-8ace-42762e42e4cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089948860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2089948860
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1403344622
Short name T715
Test name
Test status
Simulation time 117631159 ps
CPU time 0.94 seconds
Started Jul 14 05:04:30 PM PDT 24
Finished Jul 14 05:04:31 PM PDT 24
Peak memory 198576 kb
Host smart-4ea20f80-7fb0-4466-a3f0-975723b4545e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403344622 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1403344622
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2671076079
Short name T91
Test name
Test status
Simulation time 18969547 ps
CPU time 0.6 seconds
Started Jul 14 05:04:21 PM PDT 24
Finished Jul 14 05:04:22 PM PDT 24
Peak memory 195640 kb
Host smart-a0e73b95-a8a2-47fd-86f2-5c4c229b3901
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671076079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2671076079
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3312401064
Short name T836
Test name
Test status
Simulation time 13863298 ps
CPU time 0.59 seconds
Started Jul 14 05:04:29 PM PDT 24
Finished Jul 14 05:04:30 PM PDT 24
Peak memory 194836 kb
Host smart-e7f281e6-67b8-4e27-8454-1ff0a14fa448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312401064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3312401064
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1369134688
Short name T828
Test name
Test status
Simulation time 89427418 ps
CPU time 0.79 seconds
Started Jul 14 05:04:22 PM PDT 24
Finished Jul 14 05:04:23 PM PDT 24
Peak memory 196776 kb
Host smart-5e6191cd-0e42-4737-bbc5-9fe9764b083e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369134688 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1369134688
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.4145791601
Short name T765
Test name
Test status
Simulation time 58900748 ps
CPU time 2.93 seconds
Started Jul 14 05:04:29 PM PDT 24
Finished Jul 14 05:04:32 PM PDT 24
Peak memory 198688 kb
Host smart-99ed7f04-eb27-4b04-8d56-6e249ca9d5ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145791601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.4145791601
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.569972397
Short name T39
Test name
Test status
Simulation time 112676616 ps
CPU time 1.16 seconds
Started Jul 14 05:04:29 PM PDT 24
Finished Jul 14 05:04:31 PM PDT 24
Peak memory 198724 kb
Host smart-45c6bb5d-83ce-42f9-9ac3-8aed60985f11
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569972397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.gpio_tl_intg_err.569972397
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.850969809
Short name T810
Test name
Test status
Simulation time 116014048 ps
CPU time 0.84 seconds
Started Jul 14 05:04:37 PM PDT 24
Finished Jul 14 05:04:38 PM PDT 24
Peak memory 196540 kb
Host smart-8c6ad197-8729-4d1e-8cbf-16d9b7f46f1d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850969809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.850969809
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1606221011
Short name T732
Test name
Test status
Simulation time 81482319 ps
CPU time 3.04 seconds
Started Jul 14 05:04:46 PM PDT 24
Finished Jul 14 05:04:49 PM PDT 24
Peak memory 197700 kb
Host smart-a5a7b5e8-bee1-47f6-86ed-9821a91b8668
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606221011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.1606221011
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1378861141
Short name T101
Test name
Test status
Simulation time 26716171 ps
CPU time 0.6 seconds
Started Jul 14 05:04:44 PM PDT 24
Finished Jul 14 05:04:45 PM PDT 24
Peak memory 194892 kb
Host smart-0a5a5562-3f94-4147-9049-ebc73c6dfe39
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378861141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.1378861141
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2201010609
Short name T759
Test name
Test status
Simulation time 289091198 ps
CPU time 0.83 seconds
Started Jul 14 05:04:44 PM PDT 24
Finished Jul 14 05:04:46 PM PDT 24
Peak memory 198412 kb
Host smart-781c33ad-8774-4068-ba01-e6e0dc72bfb5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201010609 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.2201010609
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2869309698
Short name T781
Test name
Test status
Simulation time 29733270 ps
CPU time 0.6 seconds
Started Jul 14 05:04:36 PM PDT 24
Finished Jul 14 05:04:38 PM PDT 24
Peak memory 196256 kb
Host smart-cf3de606-aaca-42a4-8da4-674cbbef5386
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869309698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2869309698
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.218941663
Short name T800
Test name
Test status
Simulation time 39311469 ps
CPU time 0.58 seconds
Started Jul 14 05:04:44 PM PDT 24
Finished Jul 14 05:04:45 PM PDT 24
Peak memory 194988 kb
Host smart-2ba56aed-4b39-4cfc-adc0-ad4bf2333f83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218941663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.218941663
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3567653940
Short name T829
Test name
Test status
Simulation time 17500313 ps
CPU time 0.86 seconds
Started Jul 14 05:04:37 PM PDT 24
Finished Jul 14 05:04:39 PM PDT 24
Peak memory 197660 kb
Host smart-6d8eb977-a696-47ec-8933-f4e37954153a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567653940 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3567653940
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2084077801
Short name T773
Test name
Test status
Simulation time 69914651 ps
CPU time 1.67 seconds
Started Jul 14 05:04:40 PM PDT 24
Finished Jul 14 05:04:42 PM PDT 24
Peak memory 198632 kb
Host smart-d338797a-3ce1-49e6-a13f-d3f1c126b25b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084077801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2084077801
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3180599566
Short name T750
Test name
Test status
Simulation time 156047724 ps
CPU time 1.15 seconds
Started Jul 14 05:04:36 PM PDT 24
Finished Jul 14 05:04:37 PM PDT 24
Peak memory 198664 kb
Host smart-2c25d9d1-386e-4a5a-ba78-4d5a509a011e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180599566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3180599566
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2078057045
Short name T811
Test name
Test status
Simulation time 40349050 ps
CPU time 0.78 seconds
Started Jul 14 05:05:30 PM PDT 24
Finished Jul 14 05:05:31 PM PDT 24
Peak memory 198492 kb
Host smart-301e1f80-abd6-459f-a13d-8261a9889543
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078057045 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2078057045
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2921323802
Short name T823
Test name
Test status
Simulation time 45868230 ps
CPU time 0.65 seconds
Started Jul 14 05:05:32 PM PDT 24
Finished Jul 14 05:05:33 PM PDT 24
Peak memory 195332 kb
Host smart-1282b1d2-3e6f-4782-826d-078624fff1a9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921323802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2921323802
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3839251173
Short name T815
Test name
Test status
Simulation time 28807147 ps
CPU time 0.64 seconds
Started Jul 14 05:05:32 PM PDT 24
Finished Jul 14 05:05:33 PM PDT 24
Peak memory 194220 kb
Host smart-826711d7-5e60-492e-b7d1-10b88b9ba57e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839251173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3839251173
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1001720063
Short name T748
Test name
Test status
Simulation time 108829287 ps
CPU time 2.96 seconds
Started Jul 14 05:05:31 PM PDT 24
Finished Jul 14 05:05:34 PM PDT 24
Peak memory 198588 kb
Host smart-f1c00cdc-1eb6-42eb-b90c-a524a5ddb8d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001720063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1001720063
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.539061826
Short name T795
Test name
Test status
Simulation time 379291160 ps
CPU time 0.84 seconds
Started Jul 14 05:05:31 PM PDT 24
Finished Jul 14 05:05:33 PM PDT 24
Peak memory 197800 kb
Host smart-7ae9c853-bb4c-4a3c-88f2-9fef1eeaefa3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539061826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.gpio_tl_intg_err.539061826
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2371554655
Short name T722
Test name
Test status
Simulation time 84693980 ps
CPU time 0.92 seconds
Started Jul 14 05:05:38 PM PDT 24
Finished Jul 14 05:05:40 PM PDT 24
Peak memory 198480 kb
Host smart-4e662895-ba97-4f04-aa75-6148e4611449
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371554655 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2371554655
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2302110945
Short name T87
Test name
Test status
Simulation time 11236549 ps
CPU time 0.6 seconds
Started Jul 14 05:05:29 PM PDT 24
Finished Jul 14 05:05:30 PM PDT 24
Peak memory 194980 kb
Host smart-7beae6e0-08d3-48c8-ad3a-420b460007f3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302110945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.2302110945
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2348647256
Short name T803
Test name
Test status
Simulation time 28483019 ps
CPU time 0.58 seconds
Started Jul 14 05:05:38 PM PDT 24
Finished Jul 14 05:05:39 PM PDT 24
Peak memory 194224 kb
Host smart-c2c76544-0269-43eb-904d-63b9ac601bbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348647256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2348647256
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.4129234177
Short name T837
Test name
Test status
Simulation time 107689058 ps
CPU time 0.81 seconds
Started Jul 14 05:05:40 PM PDT 24
Finished Jul 14 05:05:41 PM PDT 24
Peak memory 197408 kb
Host smart-abc28f73-49de-4825-93bc-ba660fc48f37
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129234177 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.4129234177
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.4032005185
Short name T758
Test name
Test status
Simulation time 29978468 ps
CPU time 1.54 seconds
Started Jul 14 05:05:38 PM PDT 24
Finished Jul 14 05:05:40 PM PDT 24
Peak memory 198560 kb
Host smart-f63aa361-5c1c-4370-bb6c-acd7c864ac34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032005185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.4032005185
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.135448948
Short name T26
Test name
Test status
Simulation time 208813761 ps
CPU time 1.4 seconds
Started Jul 14 05:05:38 PM PDT 24
Finished Jul 14 05:05:41 PM PDT 24
Peak memory 198676 kb
Host smart-2565b586-6a8e-4a1b-82c7-3e3077e0273c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135448948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.135448948
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2704221041
Short name T723
Test name
Test status
Simulation time 75571122 ps
CPU time 0.81 seconds
Started Jul 14 05:05:40 PM PDT 24
Finished Jul 14 05:05:42 PM PDT 24
Peak memory 198496 kb
Host smart-a2d696d7-0d23-4f52-9303-20cc5b3ce327
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704221041 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2704221041
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3972081476
Short name T777
Test name
Test status
Simulation time 14457822 ps
CPU time 0.62 seconds
Started Jul 14 05:05:40 PM PDT 24
Finished Jul 14 05:05:42 PM PDT 24
Peak memory 195216 kb
Host smart-66c4f5b1-50ac-4a1e-ad01-d62d2454d504
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972081476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.3972081476
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1531966446
Short name T830
Test name
Test status
Simulation time 18655271 ps
CPU time 0.64 seconds
Started Jul 14 05:05:39 PM PDT 24
Finished Jul 14 05:05:40 PM PDT 24
Peak memory 194256 kb
Host smart-9df790ae-3fad-4a5f-96ba-57b41d751787
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531966446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1531966446
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2324439579
Short name T94
Test name
Test status
Simulation time 78779542 ps
CPU time 0.68 seconds
Started Jul 14 05:05:40 PM PDT 24
Finished Jul 14 05:05:42 PM PDT 24
Peak memory 196044 kb
Host smart-f2f0f641-d3a0-4dae-b84b-3e98a78a93d8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324439579 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2324439579
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3723615940
Short name T832
Test name
Test status
Simulation time 806225345 ps
CPU time 1.37 seconds
Started Jul 14 05:05:39 PM PDT 24
Finished Jul 14 05:05:41 PM PDT 24
Peak memory 198696 kb
Host smart-8e2a167d-5dbc-4be4-ae40-c4ef49f7b318
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723615940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3723615940
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.4055870320
Short name T833
Test name
Test status
Simulation time 88884687 ps
CPU time 1.18 seconds
Started Jul 14 05:05:38 PM PDT 24
Finished Jul 14 05:05:39 PM PDT 24
Peak memory 198636 kb
Host smart-9f57150f-84ae-4d50-bbb5-20083c84421d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055870320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.4055870320
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.4146000436
Short name T792
Test name
Test status
Simulation time 34981975 ps
CPU time 0.95 seconds
Started Jul 14 05:05:38 PM PDT 24
Finished Jul 14 05:05:40 PM PDT 24
Peak memory 198440 kb
Host smart-1228079e-3dd4-4d8e-8f7d-204bf0872aac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146000436 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.4146000436
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1310498109
Short name T814
Test name
Test status
Simulation time 61118287 ps
CPU time 0.58 seconds
Started Jul 14 05:05:38 PM PDT 24
Finished Jul 14 05:05:40 PM PDT 24
Peak memory 193852 kb
Host smart-57456add-dec9-412d-b776-1280a2b19e3f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310498109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.1310498109
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1396037798
Short name T724
Test name
Test status
Simulation time 42860957 ps
CPU time 0.59 seconds
Started Jul 14 05:05:46 PM PDT 24
Finished Jul 14 05:05:48 PM PDT 24
Peak memory 194332 kb
Host smart-1749fa54-cc68-44fa-84c6-d572e328f40f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396037798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1396037798
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1366549633
Short name T804
Test name
Test status
Simulation time 39477810 ps
CPU time 0.66 seconds
Started Jul 14 05:05:40 PM PDT 24
Finished Jul 14 05:05:41 PM PDT 24
Peak memory 195440 kb
Host smart-9359f1c7-815e-427b-98f6-234f62b16b8f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366549633 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1366549633
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3922767558
Short name T730
Test name
Test status
Simulation time 1389531711 ps
CPU time 2.11 seconds
Started Jul 14 05:05:46 PM PDT 24
Finished Jul 14 05:05:50 PM PDT 24
Peak memory 198608 kb
Host smart-fbf22adc-13bf-4afb-9995-80e7b14ea27b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922767558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.3922767558
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3341539449
Short name T826
Test name
Test status
Simulation time 46471928 ps
CPU time 0.83 seconds
Started Jul 14 05:05:46 PM PDT 24
Finished Jul 14 05:05:47 PM PDT 24
Peak memory 193128 kb
Host smart-ed5a5e96-1563-455f-801b-74fb2ebb6949
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341539449 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3341539449
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1134516941
Short name T802
Test name
Test status
Simulation time 11132804 ps
CPU time 0.59 seconds
Started Jul 14 05:05:46 PM PDT 24
Finished Jul 14 05:05:48 PM PDT 24
Peak memory 196068 kb
Host smart-05302375-1da8-472c-9945-55295cfb851b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134516941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.1134516941
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1317686773
Short name T756
Test name
Test status
Simulation time 14345190 ps
CPU time 0.59 seconds
Started Jul 14 05:05:46 PM PDT 24
Finished Jul 14 05:05:48 PM PDT 24
Peak memory 194876 kb
Host smart-85a695b8-7c53-4723-acb1-bcf491f1cf8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317686773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1317686773
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.342632790
Short name T98
Test name
Test status
Simulation time 30448005 ps
CPU time 0.67 seconds
Started Jul 14 05:05:49 PM PDT 24
Finished Jul 14 05:05:50 PM PDT 24
Peak memory 195452 kb
Host smart-55e2bd8b-4509-4d44-a2a5-cab85074a63d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342632790 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 14.gpio_same_csr_outstanding.342632790
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2539122850
Short name T749
Test name
Test status
Simulation time 58518549 ps
CPU time 2.87 seconds
Started Jul 14 05:05:45 PM PDT 24
Finished Jul 14 05:05:49 PM PDT 24
Peak memory 198668 kb
Host smart-659ae905-9dfe-4872-8936-0841c6a8c181
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539122850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2539122850
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.4272811401
Short name T104
Test name
Test status
Simulation time 79620567 ps
CPU time 1.21 seconds
Started Jul 14 05:05:45 PM PDT 24
Finished Jul 14 05:05:47 PM PDT 24
Peak memory 198672 kb
Host smart-c8d8551b-4c9c-41dc-8739-b8665466d038
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272811401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.4272811401
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2422394943
Short name T737
Test name
Test status
Simulation time 28633968 ps
CPU time 0.84 seconds
Started Jul 14 05:05:48 PM PDT 24
Finished Jul 14 05:05:50 PM PDT 24
Peak memory 198480 kb
Host smart-df1e54b8-4372-436d-929a-953d049c91ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422394943 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2422394943
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2266183271
Short name T735
Test name
Test status
Simulation time 118313691 ps
CPU time 0.6 seconds
Started Jul 14 05:05:44 PM PDT 24
Finished Jul 14 05:05:45 PM PDT 24
Peak memory 195076 kb
Host smart-2144229a-c32f-455a-9d20-7a99d3c015d2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266183271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2266183271
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3115100027
Short name T821
Test name
Test status
Simulation time 69221523 ps
CPU time 0.57 seconds
Started Jul 14 05:05:46 PM PDT 24
Finished Jul 14 05:05:48 PM PDT 24
Peak memory 194372 kb
Host smart-2067f399-d5d2-45b8-9489-2631125aa23c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115100027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3115100027
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2642397865
Short name T78
Test name
Test status
Simulation time 85715468 ps
CPU time 0.8 seconds
Started Jul 14 05:05:49 PM PDT 24
Finished Jul 14 05:05:50 PM PDT 24
Peak memory 197432 kb
Host smart-a42e9203-6aff-4a75-9470-f932867ba21a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642397865 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2642397865
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.920701844
Short name T818
Test name
Test status
Simulation time 46475380 ps
CPU time 1.25 seconds
Started Jul 14 05:05:46 PM PDT 24
Finished Jul 14 05:05:49 PM PDT 24
Peak memory 198600 kb
Host smart-8ecc87ea-bfc3-4d54-ae2f-de9a0bbf850c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920701844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.920701844
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.950507264
Short name T779
Test name
Test status
Simulation time 79741462 ps
CPU time 1.22 seconds
Started Jul 14 05:05:49 PM PDT 24
Finished Jul 14 05:05:51 PM PDT 24
Peak memory 198608 kb
Host smart-f3ada314-5763-4f1c-a940-64e073ebb4c3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950507264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.gpio_tl_intg_err.950507264
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3854907540
Short name T728
Test name
Test status
Simulation time 32733207 ps
CPU time 1.39 seconds
Started Jul 14 05:05:53 PM PDT 24
Finished Jul 14 05:05:55 PM PDT 24
Peak memory 198704 kb
Host smart-0b33c0ef-0a2b-4f62-82a8-31ac1016a49f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854907540 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3854907540
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1521747785
Short name T835
Test name
Test status
Simulation time 15645867 ps
CPU time 0.64 seconds
Started Jul 14 05:05:46 PM PDT 24
Finished Jul 14 05:05:47 PM PDT 24
Peak memory 196032 kb
Host smart-941f3f89-1850-4b98-8dcc-85cf9a5de161
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521747785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.1521747785
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.1180514006
Short name T825
Test name
Test status
Simulation time 13173429 ps
CPU time 0.64 seconds
Started Jul 14 05:05:52 PM PDT 24
Finished Jul 14 05:05:54 PM PDT 24
Peak memory 194244 kb
Host smart-86aa82b8-30ec-4c66-9203-f60016c5d90d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180514006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.1180514006
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2815795359
Short name T831
Test name
Test status
Simulation time 32636857 ps
CPU time 0.64 seconds
Started Jul 14 05:05:53 PM PDT 24
Finished Jul 14 05:05:54 PM PDT 24
Peak memory 195292 kb
Host smart-f7852dbe-79cf-414d-8f91-0012a8592d1c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815795359 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2815795359
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.993111248
Short name T787
Test name
Test status
Simulation time 555554531 ps
CPU time 2.37 seconds
Started Jul 14 05:05:53 PM PDT 24
Finished Jul 14 05:05:56 PM PDT 24
Peak memory 198632 kb
Host smart-72778e40-a08e-4178-8171-969b9695e957
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993111248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.993111248
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1468230219
Short name T38
Test name
Test status
Simulation time 156089375 ps
CPU time 1.12 seconds
Started Jul 14 05:05:55 PM PDT 24
Finished Jul 14 05:05:57 PM PDT 24
Peak memory 198172 kb
Host smart-a10cae01-3445-4d4f-8d70-ffc8f1c40293
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468230219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.1468230219
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1234356009
Short name T761
Test name
Test status
Simulation time 46527704 ps
CPU time 0.69 seconds
Started Jul 14 05:06:01 PM PDT 24
Finished Jul 14 05:06:02 PM PDT 24
Peak memory 198336 kb
Host smart-5ba20319-bb56-433b-acaf-89fe527504c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234356009 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.1234356009
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.634435490
Short name T827
Test name
Test status
Simulation time 13860054 ps
CPU time 0.59 seconds
Started Jul 14 05:05:53 PM PDT 24
Finished Jul 14 05:05:55 PM PDT 24
Peak memory 193868 kb
Host smart-0455dcf5-1114-4235-8020-b6d6cf725994
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634435490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.634435490
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.279550962
Short name T790
Test name
Test status
Simulation time 53201309 ps
CPU time 0.63 seconds
Started Jul 14 05:06:00 PM PDT 24
Finished Jul 14 05:06:02 PM PDT 24
Peak memory 194216 kb
Host smart-9ec62350-174d-4357-bb28-4cbc9d3aac0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279550962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.279550962
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3013625873
Short name T807
Test name
Test status
Simulation time 75556677 ps
CPU time 0.84 seconds
Started Jul 14 05:06:00 PM PDT 24
Finished Jul 14 05:06:02 PM PDT 24
Peak memory 196668 kb
Host smart-6615d10d-b892-4464-b5c6-f6f6bae5f29f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013625873 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3013625873
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.566103068
Short name T721
Test name
Test status
Simulation time 40668184 ps
CPU time 1.93 seconds
Started Jul 14 05:06:01 PM PDT 24
Finished Jul 14 05:06:03 PM PDT 24
Peak memory 198600 kb
Host smart-9e77a3d1-6925-4f25-9b71-e27bf380fb63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566103068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.566103068
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.315736170
Short name T103
Test name
Test status
Simulation time 130448122 ps
CPU time 1.43 seconds
Started Jul 14 05:06:00 PM PDT 24
Finished Jul 14 05:06:02 PM PDT 24
Peak memory 198556 kb
Host smart-6db37a61-5309-4b4d-8d5d-824d4e774758
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315736170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.gpio_tl_intg_err.315736170
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.745195717
Short name T799
Test name
Test status
Simulation time 37273760 ps
CPU time 0.73 seconds
Started Jul 14 05:06:01 PM PDT 24
Finished Jul 14 05:06:03 PM PDT 24
Peak memory 198460 kb
Host smart-43d6e529-3505-41ba-a093-03eff06e8a8e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745195717 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.745195717
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.44342733
Short name T766
Test name
Test status
Simulation time 11911230 ps
CPU time 0.6 seconds
Started Jul 14 05:06:01 PM PDT 24
Finished Jul 14 05:06:02 PM PDT 24
Peak memory 193820 kb
Host smart-3000716b-8de0-4e6c-abf7-39fdca61b42d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44342733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_
csr_rw.44342733
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.1875212497
Short name T778
Test name
Test status
Simulation time 39864395 ps
CPU time 0.61 seconds
Started Jul 14 05:06:03 PM PDT 24
Finished Jul 14 05:06:04 PM PDT 24
Peak memory 194896 kb
Host smart-f8a74637-22e7-430d-8bdd-ad493093070c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875212497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1875212497
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3532014463
Short name T81
Test name
Test status
Simulation time 207065239 ps
CPU time 0.9 seconds
Started Jul 14 05:06:00 PM PDT 24
Finished Jul 14 05:06:01 PM PDT 24
Peak memory 196944 kb
Host smart-3e12a705-eb06-4056-9f2a-5a17e4beefe2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532014463 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3532014463
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1975349926
Short name T839
Test name
Test status
Simulation time 736176434 ps
CPU time 3.09 seconds
Started Jul 14 05:06:00 PM PDT 24
Finished Jul 14 05:06:04 PM PDT 24
Peak memory 198580 kb
Host smart-b83d3e71-7c4b-47f1-81a5-1fc8f29f9250
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975349926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.1975349926
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2118642394
Short name T736
Test name
Test status
Simulation time 47293454 ps
CPU time 1.19 seconds
Started Jul 14 05:06:09 PM PDT 24
Finished Jul 14 05:06:11 PM PDT 24
Peak memory 198776 kb
Host smart-543ca10c-d600-4ae3-9914-772753efe633
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118642394 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2118642394
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3921728587
Short name T86
Test name
Test status
Simulation time 35006610 ps
CPU time 0.62 seconds
Started Jul 14 05:06:01 PM PDT 24
Finished Jul 14 05:06:02 PM PDT 24
Peak memory 195448 kb
Host smart-9e53e2a4-550b-4582-bb81-060ddf0f445d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921728587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.3921728587
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.2433456635
Short name T760
Test name
Test status
Simulation time 17602485 ps
CPU time 0.61 seconds
Started Jul 14 05:06:09 PM PDT 24
Finished Jul 14 05:06:10 PM PDT 24
Peak memory 194192 kb
Host smart-9e88adc4-00a9-4423-b04c-bff0f572bc35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433456635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.2433456635
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.695852435
Short name T763
Test name
Test status
Simulation time 87606651 ps
CPU time 0.78 seconds
Started Jul 14 05:06:08 PM PDT 24
Finished Jul 14 05:06:10 PM PDT 24
Peak memory 196848 kb
Host smart-e3cab148-2920-4212-809c-7a4d8b0f0b4b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695852435 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.695852435
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1800529839
Short name T776
Test name
Test status
Simulation time 18613871 ps
CPU time 0.91 seconds
Started Jul 14 05:06:09 PM PDT 24
Finished Jul 14 05:06:11 PM PDT 24
Peak memory 198376 kb
Host smart-8210d56e-93f6-41b2-9444-87c58c6a4cb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800529839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1800529839
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2500029577
Short name T35
Test name
Test status
Simulation time 277558836 ps
CPU time 1.18 seconds
Started Jul 14 05:06:08 PM PDT 24
Finished Jul 14 05:06:10 PM PDT 24
Peak memory 198560 kb
Host smart-02fd7434-c6da-48ff-8bfa-0ea957ed1436
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500029577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2500029577
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1210580800
Short name T80
Test name
Test status
Simulation time 143897926 ps
CPU time 0.86 seconds
Started Jul 14 05:04:48 PM PDT 24
Finished Jul 14 05:04:50 PM PDT 24
Peak memory 196644 kb
Host smart-bb4c7eac-c6f0-423b-bd22-23c1c3387907
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210580800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1210580800
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3133859369
Short name T808
Test name
Test status
Simulation time 260042092 ps
CPU time 3.17 seconds
Started Jul 14 05:04:53 PM PDT 24
Finished Jul 14 05:04:57 PM PDT 24
Peak memory 197456 kb
Host smart-069a3efd-286e-43ce-a76b-b8b6cbc98a66
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133859369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3133859369
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2678932032
Short name T767
Test name
Test status
Simulation time 198950256 ps
CPU time 0.88 seconds
Started Jul 14 05:04:53 PM PDT 24
Finished Jul 14 05:04:54 PM PDT 24
Peak memory 198584 kb
Host smart-5d4b44e4-2be8-47b6-a69f-e84241fece09
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678932032 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2678932032
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.658291826
Short name T88
Test name
Test status
Simulation time 83708753 ps
CPU time 0.58 seconds
Started Jul 14 05:04:46 PM PDT 24
Finished Jul 14 05:04:46 PM PDT 24
Peak memory 194188 kb
Host smart-b6204729-c189-4ded-bf3c-223714452f9b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658291826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_
csr_rw.658291826
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2024945497
Short name T801
Test name
Test status
Simulation time 15769050 ps
CPU time 0.6 seconds
Started Jul 14 05:04:52 PM PDT 24
Finished Jul 14 05:04:53 PM PDT 24
Peak memory 194876 kb
Host smart-b360ba7c-505b-4584-a226-7f326408884e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024945497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2024945497
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1630851142
Short name T97
Test name
Test status
Simulation time 37877638 ps
CPU time 0.87 seconds
Started Jul 14 05:04:45 PM PDT 24
Finished Jul 14 05:04:47 PM PDT 24
Peak memory 198400 kb
Host smart-31ebab36-641e-4b31-ac6a-faaf938bcb3f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630851142 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.1630851142
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.579767413
Short name T713
Test name
Test status
Simulation time 156717193 ps
CPU time 2.07 seconds
Started Jul 14 05:04:54 PM PDT 24
Finished Jul 14 05:04:56 PM PDT 24
Peak memory 198580 kb
Host smart-6aa2f887-761f-4ec8-9cf0-0fde57347ce2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579767413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.579767413
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.510630979
Short name T40
Test name
Test status
Simulation time 87091402 ps
CPU time 1.16 seconds
Started Jul 14 05:04:52 PM PDT 24
Finished Jul 14 05:04:54 PM PDT 24
Peak memory 198556 kb
Host smart-5598f297-dc2d-4378-8a45-212e16cb8e67
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510630979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.510630979
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.1231621252
Short name T824
Test name
Test status
Simulation time 18028639 ps
CPU time 0.61 seconds
Started Jul 14 05:06:09 PM PDT 24
Finished Jul 14 05:06:11 PM PDT 24
Peak memory 194976 kb
Host smart-dc89d6a6-64f7-4bde-b76e-26838b1fc5e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231621252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.1231621252
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2865703344
Short name T775
Test name
Test status
Simulation time 44933890 ps
CPU time 0.63 seconds
Started Jul 14 05:06:07 PM PDT 24
Finished Jul 14 05:06:08 PM PDT 24
Peak memory 194348 kb
Host smart-b750b76c-c8a7-4b4c-9dea-19f74d9cf115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865703344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2865703344
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.870703483
Short name T785
Test name
Test status
Simulation time 37352194 ps
CPU time 0.57 seconds
Started Jul 14 05:06:09 PM PDT 24
Finished Jul 14 05:06:10 PM PDT 24
Peak memory 194308 kb
Host smart-e83842ce-990d-4c52-95e4-5c8155173592
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870703483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.870703483
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.841873204
Short name T717
Test name
Test status
Simulation time 11298216 ps
CPU time 0.58 seconds
Started Jul 14 05:06:10 PM PDT 24
Finished Jul 14 05:06:11 PM PDT 24
Peak memory 194148 kb
Host smart-c611f775-fc5d-4195-818b-c7c79a20ad92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841873204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.841873204
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.2344132625
Short name T755
Test name
Test status
Simulation time 65283251 ps
CPU time 0.61 seconds
Started Jul 14 05:06:11 PM PDT 24
Finished Jul 14 05:06:12 PM PDT 24
Peak memory 194960 kb
Host smart-4895f9b6-b012-47ea-834a-eb87ea30821e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344132625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.2344132625
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1097798195
Short name T744
Test name
Test status
Simulation time 47098686 ps
CPU time 0.61 seconds
Started Jul 14 05:06:08 PM PDT 24
Finished Jul 14 05:06:09 PM PDT 24
Peak memory 194884 kb
Host smart-986bcd47-fb47-4f03-a410-ae8a4c73fb7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097798195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1097798195
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.703322596
Short name T742
Test name
Test status
Simulation time 12848759 ps
CPU time 0.57 seconds
Started Jul 14 05:06:10 PM PDT 24
Finished Jul 14 05:06:12 PM PDT 24
Peak memory 194212 kb
Host smart-97e28f61-f9ef-421b-8ca7-10c226b1c36f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703322596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.703322596
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1620321488
Short name T769
Test name
Test status
Simulation time 50082552 ps
CPU time 0.59 seconds
Started Jul 14 05:06:08 PM PDT 24
Finished Jul 14 05:06:09 PM PDT 24
Peak memory 194360 kb
Host smart-54b29879-4433-4505-9820-74b22ec5b00d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620321488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1620321488
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2449021197
Short name T733
Test name
Test status
Simulation time 44953024 ps
CPU time 0.63 seconds
Started Jul 14 05:06:08 PM PDT 24
Finished Jul 14 05:06:09 PM PDT 24
Peak memory 194976 kb
Host smart-bf2ad113-d811-49ce-977b-cf62ba5ad2b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449021197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2449021197
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.834556168
Short name T727
Test name
Test status
Simulation time 26846391 ps
CPU time 0.6 seconds
Started Jul 14 05:06:10 PM PDT 24
Finished Jul 14 05:06:12 PM PDT 24
Peak memory 194212 kb
Host smart-450f4394-66fe-4f03-90e0-9d9808e9978d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834556168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.834556168
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3237736006
Short name T89
Test name
Test status
Simulation time 23779295 ps
CPU time 0.8 seconds
Started Jul 14 05:04:53 PM PDT 24
Finished Jul 14 05:04:54 PM PDT 24
Peak memory 196520 kb
Host smart-720af130-f458-4fe8-b8f9-df514daa4c3f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237736006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.3237736006
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2631053702
Short name T102
Test name
Test status
Simulation time 81778126 ps
CPU time 2.98 seconds
Started Jul 14 05:05:02 PM PDT 24
Finished Jul 14 05:05:05 PM PDT 24
Peak memory 197728 kb
Host smart-276be592-b352-4fab-9016-075e835d240b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631053702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2631053702
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2913578174
Short name T82
Test name
Test status
Simulation time 29961395 ps
CPU time 0.68 seconds
Started Jul 14 05:05:00 PM PDT 24
Finished Jul 14 05:05:01 PM PDT 24
Peak memory 196356 kb
Host smart-0e82447d-d3a4-4ac7-b1a8-89da069c0298
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913578174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.2913578174
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2765743449
Short name T782
Test name
Test status
Simulation time 154710370 ps
CPU time 1 seconds
Started Jul 14 05:04:55 PM PDT 24
Finished Jul 14 05:04:56 PM PDT 24
Peak memory 198524 kb
Host smart-9eac8a7a-33aa-454c-ab71-3b746bed0f29
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765743449 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2765743449
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1242780510
Short name T90
Test name
Test status
Simulation time 20111588 ps
CPU time 0.58 seconds
Started Jul 14 05:04:54 PM PDT 24
Finished Jul 14 05:04:55 PM PDT 24
Peak memory 193868 kb
Host smart-91a6f657-9bf7-441b-92c8-e92214219b6c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242780510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1242780510
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3209590426
Short name T764
Test name
Test status
Simulation time 14038218 ps
CPU time 0.58 seconds
Started Jul 14 05:05:00 PM PDT 24
Finished Jul 14 05:05:01 PM PDT 24
Peak memory 194264 kb
Host smart-3ae46f19-8242-4cfe-952b-f1f8843fbe6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209590426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3209590426
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1658320934
Short name T99
Test name
Test status
Simulation time 157416126 ps
CPU time 0.9 seconds
Started Jul 14 05:04:53 PM PDT 24
Finished Jul 14 05:04:54 PM PDT 24
Peak memory 196944 kb
Host smart-fbc8e91a-285c-418b-9061-dc938474623a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658320934 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.1658320934
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.841949476
Short name T729
Test name
Test status
Simulation time 165567920 ps
CPU time 2.39 seconds
Started Jul 14 05:04:55 PM PDT 24
Finished Jul 14 05:04:58 PM PDT 24
Peak memory 198672 kb
Host smart-0a0f5c13-f186-4515-9b4a-f372efc8a631
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841949476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.841949476
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2044692691
Short name T37
Test name
Test status
Simulation time 453369748 ps
CPU time 0.86 seconds
Started Jul 14 05:04:55 PM PDT 24
Finished Jul 14 05:04:56 PM PDT 24
Peak memory 197468 kb
Host smart-7b92962a-8862-4320-9384-09aa2ca966d8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044692691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.2044692691
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.881707967
Short name T716
Test name
Test status
Simulation time 63123495 ps
CPU time 0.57 seconds
Started Jul 14 05:06:10 PM PDT 24
Finished Jul 14 05:06:11 PM PDT 24
Peak memory 194808 kb
Host smart-9ffbf891-721a-412d-ab5d-c79ab68a8ea7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881707967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.881707967
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1035253768
Short name T751
Test name
Test status
Simulation time 11772136 ps
CPU time 0.59 seconds
Started Jul 14 05:06:09 PM PDT 24
Finished Jul 14 05:06:11 PM PDT 24
Peak memory 194924 kb
Host smart-a7f0ed63-d3a0-4c76-9728-9495c33b67c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035253768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1035253768
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.2086957300
Short name T805
Test name
Test status
Simulation time 56211109 ps
CPU time 0.62 seconds
Started Jul 14 05:06:08 PM PDT 24
Finished Jul 14 05:06:09 PM PDT 24
Peak memory 194956 kb
Host smart-b16d2486-e7a2-487c-943b-54ba3f5e28b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086957300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2086957300
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.2645746451
Short name T753
Test name
Test status
Simulation time 37634622 ps
CPU time 0.6 seconds
Started Jul 14 05:06:14 PM PDT 24
Finished Jul 14 05:06:15 PM PDT 24
Peak memory 194288 kb
Host smart-0262fd4c-137f-4a44-acfd-d725843b829f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645746451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.2645746451
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.66632926
Short name T816
Test name
Test status
Simulation time 32953407 ps
CPU time 0.62 seconds
Started Jul 14 05:06:14 PM PDT 24
Finished Jul 14 05:06:15 PM PDT 24
Peak memory 194252 kb
Host smart-e342ca0a-3fe9-41d6-850c-868ba1cdc189
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66632926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.66632926
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.2494387951
Short name T747
Test name
Test status
Simulation time 43777989 ps
CPU time 0.58 seconds
Started Jul 14 05:06:16 PM PDT 24
Finished Jul 14 05:06:17 PM PDT 24
Peak memory 194872 kb
Host smart-5a784127-48b7-4f2d-a81a-e17e60eef24d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494387951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2494387951
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.1309258467
Short name T725
Test name
Test status
Simulation time 46500111 ps
CPU time 0.59 seconds
Started Jul 14 05:06:14 PM PDT 24
Finished Jul 14 05:06:16 PM PDT 24
Peak memory 194868 kb
Host smart-350f0950-ae93-4747-a171-bcf91cdc2503
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309258467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.1309258467
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1294067199
Short name T734
Test name
Test status
Simulation time 39410085 ps
CPU time 0.58 seconds
Started Jul 14 05:06:17 PM PDT 24
Finished Jul 14 05:06:19 PM PDT 24
Peak memory 194188 kb
Host smart-8d881dd0-48fb-4ab2-8690-c8058cc6a505
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294067199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1294067199
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.201500492
Short name T772
Test name
Test status
Simulation time 17449491 ps
CPU time 0.58 seconds
Started Jul 14 05:06:15 PM PDT 24
Finished Jul 14 05:06:17 PM PDT 24
Peak memory 194876 kb
Host smart-3300b3b9-463c-4f70-ab9d-5f94f9951cd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201500492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.201500492
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.551755971
Short name T771
Test name
Test status
Simulation time 43947826 ps
CPU time 0.63 seconds
Started Jul 14 05:06:17 PM PDT 24
Finished Jul 14 05:06:19 PM PDT 24
Peak memory 194256 kb
Host smart-b885b086-1862-474f-bd0a-c23e96c7a2e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551755971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.551755971
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2061724029
Short name T85
Test name
Test status
Simulation time 37746403 ps
CPU time 0.87 seconds
Started Jul 14 05:05:00 PM PDT 24
Finished Jul 14 05:05:02 PM PDT 24
Peak memory 196608 kb
Host smart-ed33ddcb-efad-41ee-94b9-eb2662689da8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061724029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2061724029
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2441237220
Short name T79
Test name
Test status
Simulation time 329123415 ps
CPU time 1.37 seconds
Started Jul 14 05:05:08 PM PDT 24
Finished Jul 14 05:05:10 PM PDT 24
Peak memory 197280 kb
Host smart-861de569-468f-422c-8170-c66317ccd087
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441237220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2441237220
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.887971822
Short name T92
Test name
Test status
Simulation time 56988300 ps
CPU time 0.64 seconds
Started Jul 14 05:05:08 PM PDT 24
Finished Jul 14 05:05:09 PM PDT 24
Peak memory 196208 kb
Host smart-a740be4c-f45e-47e7-9d7c-59e9c2c33b64
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887971822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.887971822
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1535265421
Short name T739
Test name
Test status
Simulation time 106295345 ps
CPU time 0.93 seconds
Started Jul 14 05:05:01 PM PDT 24
Finished Jul 14 05:05:03 PM PDT 24
Peak memory 198508 kb
Host smart-4ca4e421-c154-40d7-8a09-b2fbc9789a68
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535265421 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1535265421
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.125991473
Short name T83
Test name
Test status
Simulation time 13900841 ps
CPU time 0.63 seconds
Started Jul 14 05:05:01 PM PDT 24
Finished Jul 14 05:05:02 PM PDT 24
Peak memory 195576 kb
Host smart-e9b3874e-c092-49fc-883f-da9a3f8f4f49
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125991473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.125991473
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.2111905101
Short name T797
Test name
Test status
Simulation time 27534327 ps
CPU time 0.6 seconds
Started Jul 14 05:05:09 PM PDT 24
Finished Jul 14 05:05:10 PM PDT 24
Peak memory 194300 kb
Host smart-e8f3a4bf-9667-4190-a20b-94cfd1cef6a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111905101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2111905101
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.4272035484
Short name T794
Test name
Test status
Simulation time 71354116 ps
CPU time 0.68 seconds
Started Jul 14 05:05:00 PM PDT 24
Finished Jul 14 05:05:02 PM PDT 24
Peak memory 195352 kb
Host smart-b5edbf2d-fa78-4f9a-93a1-84575005e32d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272035484 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.4272035484
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2095388369
Short name T806
Test name
Test status
Simulation time 344548296 ps
CPU time 1.97 seconds
Started Jul 14 05:05:00 PM PDT 24
Finished Jul 14 05:05:03 PM PDT 24
Peak memory 198660 kb
Host smart-ccea7894-f437-4119-8f98-3625d13b688e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095388369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2095388369
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.348389901
Short name T41
Test name
Test status
Simulation time 84230796 ps
CPU time 1.1 seconds
Started Jul 14 05:05:00 PM PDT 24
Finished Jul 14 05:05:02 PM PDT 24
Peak memory 198664 kb
Host smart-03212513-c51b-4a8a-8165-a9df1c3c7820
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348389901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.348389901
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.2686825663
Short name T788
Test name
Test status
Simulation time 17176540 ps
CPU time 0.61 seconds
Started Jul 14 05:06:16 PM PDT 24
Finished Jul 14 05:06:17 PM PDT 24
Peak memory 194244 kb
Host smart-9aaf3429-e042-4854-9e20-8790c6a9614d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686825663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2686825663
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1445087872
Short name T812
Test name
Test status
Simulation time 42074112 ps
CPU time 0.56 seconds
Started Jul 14 05:06:16 PM PDT 24
Finished Jul 14 05:06:17 PM PDT 24
Peak memory 194852 kb
Host smart-5fb94d0a-81a3-4d5e-a7e2-775dec9f96d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445087872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1445087872
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.683369339
Short name T757
Test name
Test status
Simulation time 14609839 ps
CPU time 0.59 seconds
Started Jul 14 05:06:15 PM PDT 24
Finished Jul 14 05:06:17 PM PDT 24
Peak memory 194856 kb
Host smart-01b63d24-002f-451f-9d48-d44b54ceb697
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683369339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.683369339
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.446871293
Short name T791
Test name
Test status
Simulation time 27089753 ps
CPU time 0.62 seconds
Started Jul 14 05:06:15 PM PDT 24
Finished Jul 14 05:06:16 PM PDT 24
Peak memory 194860 kb
Host smart-7ccc0148-f70c-403c-bece-03b7dee318f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446871293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.446871293
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.3199124609
Short name T718
Test name
Test status
Simulation time 13414210 ps
CPU time 0.61 seconds
Started Jul 14 05:06:16 PM PDT 24
Finished Jul 14 05:06:18 PM PDT 24
Peak memory 194952 kb
Host smart-dfe1e1a0-409d-46ed-b52c-c634e868b1dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199124609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.3199124609
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.3721782030
Short name T743
Test name
Test status
Simulation time 30242822 ps
CPU time 0.65 seconds
Started Jul 14 05:06:17 PM PDT 24
Finished Jul 14 05:06:18 PM PDT 24
Peak memory 194300 kb
Host smart-a65f9ef7-2f8c-40cb-90d9-d31364d5254c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721782030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3721782030
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.3056616421
Short name T746
Test name
Test status
Simulation time 12321312 ps
CPU time 0.6 seconds
Started Jul 14 05:06:17 PM PDT 24
Finished Jul 14 05:06:19 PM PDT 24
Peak memory 194908 kb
Host smart-ef2bb455-f1e6-4684-a4bf-d23da06b6b54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056616421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.3056616421
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.917564790
Short name T820
Test name
Test status
Simulation time 12996043 ps
CPU time 0.59 seconds
Started Jul 14 05:06:23 PM PDT 24
Finished Jul 14 05:06:23 PM PDT 24
Peak memory 194280 kb
Host smart-c541199b-c4d0-46d2-8a96-283a04929645
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917564790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.917564790
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.872338997
Short name T798
Test name
Test status
Simulation time 92518276 ps
CPU time 0.6 seconds
Started Jul 14 05:06:23 PM PDT 24
Finished Jul 14 05:06:24 PM PDT 24
Peak memory 194424 kb
Host smart-555cf737-5406-47a3-aca8-dc14c9b5a172
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872338997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.872338997
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.804279700
Short name T719
Test name
Test status
Simulation time 60985400 ps
CPU time 0.63 seconds
Started Jul 14 05:06:22 PM PDT 24
Finished Jul 14 05:06:23 PM PDT 24
Peak memory 194972 kb
Host smart-d00cb2d0-ceb6-4e0b-b88b-f1e8e57e0dbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804279700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.804279700
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.652767989
Short name T768
Test name
Test status
Simulation time 21910125 ps
CPU time 0.74 seconds
Started Jul 14 05:05:08 PM PDT 24
Finished Jul 14 05:05:10 PM PDT 24
Peak memory 198440 kb
Host smart-96623437-f12f-4da5-8fdd-010cb1608f03
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652767989 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.652767989
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.148287987
Short name T720
Test name
Test status
Simulation time 12744938 ps
CPU time 0.58 seconds
Started Jul 14 05:05:09 PM PDT 24
Finished Jul 14 05:05:10 PM PDT 24
Peak memory 195264 kb
Host smart-e35c0295-2b51-4fe3-9093-58241af6cbd9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148287987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.148287987
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2911120281
Short name T819
Test name
Test status
Simulation time 22808177 ps
CPU time 0.57 seconds
Started Jul 14 05:05:08 PM PDT 24
Finished Jul 14 05:05:09 PM PDT 24
Peak memory 194204 kb
Host smart-f0bd0c95-fa67-42c7-bd67-edd70240f7b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911120281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2911120281
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2031055550
Short name T817
Test name
Test status
Simulation time 70474796 ps
CPU time 0.7 seconds
Started Jul 14 05:05:08 PM PDT 24
Finished Jul 14 05:05:09 PM PDT 24
Peak memory 195504 kb
Host smart-d8d0e728-615f-49b2-be13-f710cd86a0f5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031055550 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.2031055550
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3013945761
Short name T809
Test name
Test status
Simulation time 120935948 ps
CPU time 1.47 seconds
Started Jul 14 05:05:08 PM PDT 24
Finished Jul 14 05:05:10 PM PDT 24
Peak memory 198720 kb
Host smart-2e3b2999-ad51-4247-8beb-d88bddb54724
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013945761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3013945761
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.4063491975
Short name T770
Test name
Test status
Simulation time 45933669 ps
CPU time 0.87 seconds
Started Jul 14 05:05:08 PM PDT 24
Finished Jul 14 05:05:10 PM PDT 24
Peak memory 197780 kb
Host smart-b7076f87-6826-4aeb-8f7c-f4211886f07d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063491975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.4063491975
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.469727292
Short name T822
Test name
Test status
Simulation time 53449761 ps
CPU time 0.68 seconds
Started Jul 14 05:05:15 PM PDT 24
Finished Jul 14 05:05:16 PM PDT 24
Peak memory 198428 kb
Host smart-b0781839-ee7b-4b68-8cba-f919e0bf62ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469727292 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.469727292
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.872086937
Short name T786
Test name
Test status
Simulation time 18863979 ps
CPU time 0.65 seconds
Started Jul 14 05:05:10 PM PDT 24
Finished Jul 14 05:05:11 PM PDT 24
Peak memory 195140 kb
Host smart-6b40d682-b879-40dc-8a8a-ee0231480b96
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872086937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.872086937
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2444452248
Short name T754
Test name
Test status
Simulation time 30818264 ps
CPU time 0.62 seconds
Started Jul 14 05:05:17 PM PDT 24
Finished Jul 14 05:05:18 PM PDT 24
Peak memory 194260 kb
Host smart-4252c896-5c55-49f0-b3d9-7f1f1fd52d98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444452248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2444452248
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3030120577
Short name T838
Test name
Test status
Simulation time 37362159 ps
CPU time 0.82 seconds
Started Jul 14 05:05:10 PM PDT 24
Finished Jul 14 05:05:12 PM PDT 24
Peak memory 197020 kb
Host smart-dd2fbb9e-2d37-49bc-bac9-92f47e4cf553
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030120577 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3030120577
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.687239408
Short name T796
Test name
Test status
Simulation time 37899347 ps
CPU time 1.96 seconds
Started Jul 14 05:05:18 PM PDT 24
Finished Jul 14 05:05:20 PM PDT 24
Peak memory 198588 kb
Host smart-73fab909-e097-4fa6-ab3e-ccf19685cd1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687239408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.687239408
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3924625053
Short name T813
Test name
Test status
Simulation time 147984191 ps
CPU time 1.17 seconds
Started Jul 14 05:05:16 PM PDT 24
Finished Jul 14 05:05:18 PM PDT 24
Peak memory 198596 kb
Host smart-b7676730-52e1-4c33-8602-8ce3233002e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924625053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3924625053
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.615492701
Short name T752
Test name
Test status
Simulation time 32383077 ps
CPU time 0.91 seconds
Started Jul 14 05:05:24 PM PDT 24
Finished Jul 14 05:05:26 PM PDT 24
Peak memory 198596 kb
Host smart-8c3e5774-42e6-4055-a0a1-83295429b6c4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615492701 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.615492701
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3227495521
Short name T84
Test name
Test status
Simulation time 37978822 ps
CPU time 0.6 seconds
Started Jul 14 05:05:15 PM PDT 24
Finished Jul 14 05:05:16 PM PDT 24
Peak memory 195408 kb
Host smart-89d5f2dc-e01d-4201-954b-6e22d0756e84
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227495521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3227495521
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1868291641
Short name T714
Test name
Test status
Simulation time 14563826 ps
CPU time 0.66 seconds
Started Jul 14 05:05:23 PM PDT 24
Finished Jul 14 05:05:25 PM PDT 24
Peak memory 194432 kb
Host smart-ec94a87d-8f9f-4eb1-b3fb-c7fe5d0bc795
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868291641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1868291641
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1473421329
Short name T93
Test name
Test status
Simulation time 14482260 ps
CPU time 0.66 seconds
Started Jul 14 05:05:24 PM PDT 24
Finished Jul 14 05:05:25 PM PDT 24
Peak memory 194928 kb
Host smart-979929d1-90f4-438e-94b3-45987b63555e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473421329 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1473421329
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1035204658
Short name T741
Test name
Test status
Simulation time 30137376 ps
CPU time 0.92 seconds
Started Jul 14 05:05:23 PM PDT 24
Finished Jul 14 05:05:25 PM PDT 24
Peak memory 198512 kb
Host smart-b36ff66f-016d-4cbf-b44d-bc34898eee7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035204658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.1035204658
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.968698003
Short name T27
Test name
Test status
Simulation time 127286900 ps
CPU time 0.84 seconds
Started Jul 14 05:05:23 PM PDT 24
Finished Jul 14 05:05:24 PM PDT 24
Peak memory 197468 kb
Host smart-b7717812-386c-4d83-aa6d-61ef05d0022e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968698003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.968698003
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.659508212
Short name T783
Test name
Test status
Simulation time 26598820 ps
CPU time 0.82 seconds
Started Jul 14 05:05:25 PM PDT 24
Finished Jul 14 05:05:26 PM PDT 24
Peak memory 198484 kb
Host smart-09a9c09d-8ef0-4800-863f-1f0f35d54caa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659508212 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.659508212
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2249293138
Short name T740
Test name
Test status
Simulation time 15266767 ps
CPU time 0.6 seconds
Started Jul 14 05:05:26 PM PDT 24
Finished Jul 14 05:05:27 PM PDT 24
Peak memory 194948 kb
Host smart-d693bacc-42dc-48a9-b8b9-d9683cc9ae7a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249293138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2249293138
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.1154695952
Short name T726
Test name
Test status
Simulation time 29614682 ps
CPU time 0.6 seconds
Started Jul 14 05:05:23 PM PDT 24
Finished Jul 14 05:05:24 PM PDT 24
Peak memory 194252 kb
Host smart-fabe583b-f7fa-4fce-847b-6a35e8754735
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154695952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.1154695952
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3853415780
Short name T96
Test name
Test status
Simulation time 15847969 ps
CPU time 0.64 seconds
Started Jul 14 05:05:24 PM PDT 24
Finished Jul 14 05:05:25 PM PDT 24
Peak memory 195304 kb
Host smart-a1ce96a2-75bb-462e-869b-98af6066e336
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853415780 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3853415780
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2717855531
Short name T789
Test name
Test status
Simulation time 177548927 ps
CPU time 2.53 seconds
Started Jul 14 05:05:24 PM PDT 24
Finished Jul 14 05:05:27 PM PDT 24
Peak memory 198620 kb
Host smart-2ede08cd-7e94-4c07-bafb-4b63c48c5323
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717855531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2717855531
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1629842643
Short name T780
Test name
Test status
Simulation time 112198363 ps
CPU time 1.47 seconds
Started Jul 14 05:05:24 PM PDT 24
Finished Jul 14 05:05:26 PM PDT 24
Peak memory 198668 kb
Host smart-cfd0b497-c78d-495c-a208-9b45badd9acf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629842643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1629842643
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2258651396
Short name T745
Test name
Test status
Simulation time 93398976 ps
CPU time 0.76 seconds
Started Jul 14 05:05:34 PM PDT 24
Finished Jul 14 05:05:35 PM PDT 24
Peak memory 198468 kb
Host smart-15ca5575-043b-4606-9a86-dfd908ebf4d1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258651396 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.2258651396
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1323321117
Short name T784
Test name
Test status
Simulation time 13151992 ps
CPU time 0.6 seconds
Started Jul 14 05:05:31 PM PDT 24
Finished Jul 14 05:05:32 PM PDT 24
Peak memory 195356 kb
Host smart-9e7da801-3a05-4678-8278-978ae4c21caa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323321117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1323321117
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2651039075
Short name T834
Test name
Test status
Simulation time 40559135 ps
CPU time 0.6 seconds
Started Jul 14 05:05:32 PM PDT 24
Finished Jul 14 05:05:34 PM PDT 24
Peak memory 194272 kb
Host smart-fb32ecc7-43d3-40ea-84d9-23fc5708b79d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651039075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2651039075
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.4171781971
Short name T95
Test name
Test status
Simulation time 31417666 ps
CPU time 0.78 seconds
Started Jul 14 05:05:31 PM PDT 24
Finished Jul 14 05:05:32 PM PDT 24
Peak memory 196728 kb
Host smart-0fcbc8fa-42ca-4d91-a5b2-2d0b2d7391fc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171781971 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.4171781971
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.4193989828
Short name T762
Test name
Test status
Simulation time 93259202 ps
CPU time 1.36 seconds
Started Jul 14 05:05:30 PM PDT 24
Finished Jul 14 05:05:32 PM PDT 24
Peak memory 198680 kb
Host smart-1d3468a3-0194-4d0b-b24d-2fc1464536c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193989828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.4193989828
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1316348243
Short name T793
Test name
Test status
Simulation time 280248583 ps
CPU time 1.12 seconds
Started Jul 14 05:05:34 PM PDT 24
Finished Jul 14 05:05:35 PM PDT 24
Peak memory 198684 kb
Host smart-25ea32c4-a57f-4374-a9c3-ba510b335727
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316348243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1316348243
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.65607102
Short name T538
Test name
Test status
Simulation time 15411580 ps
CPU time 0.6 seconds
Started Jul 14 05:17:01 PM PDT 24
Finished Jul 14 05:17:02 PM PDT 24
Peak memory 195380 kb
Host smart-56b6fb80-a020-4632-962c-b7fafd8d69de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65607102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.65607102
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3422136338
Short name T683
Test name
Test status
Simulation time 289331030 ps
CPU time 0.68 seconds
Started Jul 14 05:16:42 PM PDT 24
Finished Jul 14 05:16:43 PM PDT 24
Peak memory 194632 kb
Host smart-846738b8-7c1d-45c1-adc0-10a9fd5864de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422136338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3422136338
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.731013782
Short name T398
Test name
Test status
Simulation time 400988473 ps
CPU time 11.07 seconds
Started Jul 14 05:16:50 PM PDT 24
Finished Jul 14 05:17:02 PM PDT 24
Peak memory 198604 kb
Host smart-11cce4d8-fe33-43bb-b2fe-ad471354174b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731013782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.731013782
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.3750175006
Short name T202
Test name
Test status
Simulation time 82874006 ps
CPU time 1.08 seconds
Started Jul 14 05:16:56 PM PDT 24
Finished Jul 14 05:16:58 PM PDT 24
Peak memory 198356 kb
Host smart-214e072d-1c31-424c-992f-1a1b82b1ac12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750175006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3750175006
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1804020674
Short name T243
Test name
Test status
Simulation time 147967820 ps
CPU time 1.11 seconds
Started Jul 14 05:16:51 PM PDT 24
Finished Jul 14 05:16:52 PM PDT 24
Peak memory 196624 kb
Host smart-64c9acb5-7aaf-4ff3-995f-cdc5dce9afeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804020674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1804020674
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3089047855
Short name T330
Test name
Test status
Simulation time 79277232 ps
CPU time 3.12 seconds
Started Jul 14 05:16:49 PM PDT 24
Finished Jul 14 05:16:53 PM PDT 24
Peak memory 198624 kb
Host smart-3fe65903-285f-4cd2-b49f-a9d561000804
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089047855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3089047855
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1340074345
Short name T66
Test name
Test status
Simulation time 2356155563 ps
CPU time 2.89 seconds
Started Jul 14 05:16:52 PM PDT 24
Finished Jul 14 05:16:55 PM PDT 24
Peak memory 197828 kb
Host smart-de11bc16-3fad-469e-8062-43e4cd6940f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340074345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1340074345
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3873072642
Short name T308
Test name
Test status
Simulation time 31717014 ps
CPU time 0.71 seconds
Started Jul 14 05:16:44 PM PDT 24
Finished Jul 14 05:16:45 PM PDT 24
Peak memory 196576 kb
Host smart-74bda0b2-c115-41d5-8739-2dc7917881c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873072642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3873072642
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.413898576
Short name T593
Test name
Test status
Simulation time 99496896 ps
CPU time 1.21 seconds
Started Jul 14 05:16:43 PM PDT 24
Finished Jul 14 05:16:44 PM PDT 24
Peak memory 196556 kb
Host smart-ea740822-9a4a-422e-86e4-8744f9804cb0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413898576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.413898576
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2822735566
Short name T256
Test name
Test status
Simulation time 345239684 ps
CPU time 5.57 seconds
Started Jul 14 05:16:51 PM PDT 24
Finished Jul 14 05:16:57 PM PDT 24
Peak memory 198548 kb
Host smart-ad2043d5-4a32-40b1-9829-e218fa05eb41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822735566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2822735566
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.1386478301
Short name T44
Test name
Test status
Simulation time 116994887 ps
CPU time 0.78 seconds
Started Jul 14 05:17:04 PM PDT 24
Finished Jul 14 05:17:05 PM PDT 24
Peak memory 214104 kb
Host smart-ee4cd2c2-4fdb-43cc-b08f-81a5bc58f00f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386478301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1386478301
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.3923298217
Short name T383
Test name
Test status
Simulation time 191902296 ps
CPU time 1.12 seconds
Started Jul 14 05:16:39 PM PDT 24
Finished Jul 14 05:16:41 PM PDT 24
Peak memory 196924 kb
Host smart-34eb7612-4b4f-4394-adb9-2fa0860f2520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923298217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.3923298217
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.1804102332
Short name T310
Test name
Test status
Simulation time 194693105 ps
CPU time 1.32 seconds
Started Jul 14 05:16:42 PM PDT 24
Finished Jul 14 05:16:43 PM PDT 24
Peak memory 196100 kb
Host smart-bc1a5040-5e10-4e4b-9fe5-3179801bad57
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804102332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.1804102332
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.3226328387
Short name T336
Test name
Test status
Simulation time 3225369539 ps
CPU time 44.72 seconds
Started Jul 14 05:16:59 PM PDT 24
Finished Jul 14 05:17:44 PM PDT 24
Peak memory 198648 kb
Host smart-dfac44d1-75bc-4685-b0ef-38a0933f4a28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226328387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.3226328387
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.1531750145
Short name T426
Test name
Test status
Simulation time 35508800 ps
CPU time 0.62 seconds
Started Jul 14 05:17:20 PM PDT 24
Finished Jul 14 05:17:21 PM PDT 24
Peak memory 194720 kb
Host smart-ba97360a-a679-43fc-8839-09d01f86b03f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531750145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.1531750145
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.57203944
Short name T64
Test name
Test status
Simulation time 35815453 ps
CPU time 0.78 seconds
Started Jul 14 05:17:08 PM PDT 24
Finished Jul 14 05:17:09 PM PDT 24
Peak memory 196448 kb
Host smart-ccd1b7ab-a27b-492c-b12d-0172c65781ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57203944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.57203944
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3647487104
Short name T412
Test name
Test status
Simulation time 1053579552 ps
CPU time 25.17 seconds
Started Jul 14 05:17:18 PM PDT 24
Finished Jul 14 05:17:43 PM PDT 24
Peak memory 196776 kb
Host smart-75cf7640-b753-4074-87f7-eebf5f451e09
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647487104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3647487104
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.4140511814
Short name T541
Test name
Test status
Simulation time 67436013 ps
CPU time 0.65 seconds
Started Jul 14 05:17:17 PM PDT 24
Finished Jul 14 05:17:18 PM PDT 24
Peak memory 195764 kb
Host smart-db89a82b-2991-4bfb-986e-ed8e3843371a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140511814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.4140511814
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.738230578
Short name T540
Test name
Test status
Simulation time 297725636 ps
CPU time 1.36 seconds
Started Jul 14 05:17:11 PM PDT 24
Finished Jul 14 05:17:13 PM PDT 24
Peak memory 198632 kb
Host smart-a6970791-06bf-4f01-bf1f-49e0b03cafe6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738230578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.738230578
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.867761757
Short name T611
Test name
Test status
Simulation time 233034925 ps
CPU time 2.39 seconds
Started Jul 14 05:17:17 PM PDT 24
Finished Jul 14 05:17:20 PM PDT 24
Peak memory 198716 kb
Host smart-0e7fc66d-b79b-4d22-a8b8-efd7fc470f24
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867761757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.gpio_intr_with_filter_rand_intr_event.867761757
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2790174073
Short name T110
Test name
Test status
Simulation time 174680323 ps
CPU time 2.21 seconds
Started Jul 14 05:17:10 PM PDT 24
Finished Jul 14 05:17:12 PM PDT 24
Peak memory 196384 kb
Host smart-59efeca0-c8ab-4797-9184-496d55887fad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790174073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2790174073
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.4040335824
Short name T225
Test name
Test status
Simulation time 98246763 ps
CPU time 1.06 seconds
Started Jul 14 05:17:12 PM PDT 24
Finished Jul 14 05:17:14 PM PDT 24
Peak memory 197292 kb
Host smart-e3d3b5bd-cfc2-4926-9f8d-d2a775beb10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040335824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.4040335824
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.415303059
Short name T397
Test name
Test status
Simulation time 66110166 ps
CPU time 1.3 seconds
Started Jul 14 05:17:09 PM PDT 24
Finished Jul 14 05:17:11 PM PDT 24
Peak memory 196688 kb
Host smart-529e5caa-f574-4634-a345-c237147f6d66
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415303059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.415303059
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.4103132594
Short name T574
Test name
Test status
Simulation time 50111323 ps
CPU time 2.32 seconds
Started Jul 14 05:17:19 PM PDT 24
Finished Jul 14 05:17:22 PM PDT 24
Peak memory 198524 kb
Host smart-14eb43da-9a30-4d4b-8573-7c0d44c35bf9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103132594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.4103132594
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_smoke.419447956
Short name T224
Test name
Test status
Simulation time 44353482 ps
CPU time 1.24 seconds
Started Jul 14 05:17:11 PM PDT 24
Finished Jul 14 05:17:13 PM PDT 24
Peak memory 196512 kb
Host smart-bd01afb7-a71c-4d03-bfbf-18ebd5da3ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419447956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.419447956
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3698940637
Short name T660
Test name
Test status
Simulation time 20474241 ps
CPU time 0.76 seconds
Started Jul 14 05:17:12 PM PDT 24
Finished Jul 14 05:17:14 PM PDT 24
Peak memory 195432 kb
Host smart-5ed92b88-f965-4064-a9c0-68082456fbeb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698940637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3698940637
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.2022351747
Short name T135
Test name
Test status
Simulation time 3000327548 ps
CPU time 15.59 seconds
Started Jul 14 05:17:17 PM PDT 24
Finished Jul 14 05:17:33 PM PDT 24
Peak memory 198660 kb
Host smart-338ffddd-79ce-4811-9010-eb6031bf6e2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022351747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.2022351747
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.522388141
Short name T539
Test name
Test status
Simulation time 33774431 ps
CPU time 0.56 seconds
Started Jul 14 05:18:40 PM PDT 24
Finished Jul 14 05:18:41 PM PDT 24
Peak memory 194808 kb
Host smart-442b39fc-b88f-4bea-a165-cb3a1a1ddae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522388141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.522388141
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1095987402
Short name T659
Test name
Test status
Simulation time 161949718 ps
CPU time 0.95 seconds
Started Jul 14 05:18:40 PM PDT 24
Finished Jul 14 05:18:42 PM PDT 24
Peak memory 196452 kb
Host smart-d9b36034-b37e-4914-987c-0b515e2f3e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095987402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1095987402
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1316325949
Short name T191
Test name
Test status
Simulation time 514835687 ps
CPU time 18.34 seconds
Started Jul 14 05:18:40 PM PDT 24
Finished Jul 14 05:19:00 PM PDT 24
Peak memory 196072 kb
Host smart-df18fc0c-515d-4129-9dd9-e74bee2a1498
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316325949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1316325949
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1754329767
Short name T409
Test name
Test status
Simulation time 206760360 ps
CPU time 0.97 seconds
Started Jul 14 05:18:41 PM PDT 24
Finished Jul 14 05:18:43 PM PDT 24
Peak memory 197728 kb
Host smart-569eb913-8b7a-4990-bcdc-9af8ed1cd5e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754329767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1754329767
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.399409815
Short name T247
Test name
Test status
Simulation time 190564762 ps
CPU time 1.34 seconds
Started Jul 14 05:18:39 PM PDT 24
Finished Jul 14 05:18:41 PM PDT 24
Peak memory 198608 kb
Host smart-efd6b7bb-0ee1-4024-994a-b7c7cfc6e4a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399409815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.399409815
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.4226058848
Short name T210
Test name
Test status
Simulation time 59697636 ps
CPU time 2.45 seconds
Started Jul 14 05:18:40 PM PDT 24
Finished Jul 14 05:18:44 PM PDT 24
Peak memory 198576 kb
Host smart-f8e51355-185b-4ba3-bbf9-31b764b1b552
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226058848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.4226058848
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.648070853
Short name T321
Test name
Test status
Simulation time 330624981 ps
CPU time 3.39 seconds
Started Jul 14 05:18:39 PM PDT 24
Finished Jul 14 05:18:43 PM PDT 24
Peak memory 197932 kb
Host smart-2d5b94c6-4199-41fe-a88b-5be981c36128
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648070853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.
648070853
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2843036011
Short name T389
Test name
Test status
Simulation time 52304570 ps
CPU time 1.25 seconds
Started Jul 14 05:18:33 PM PDT 24
Finished Jul 14 05:18:35 PM PDT 24
Peak memory 198616 kb
Host smart-f521746a-759a-4690-b6a8-0270db1e5729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843036011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2843036011
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2794369109
Short name T140
Test name
Test status
Simulation time 64501479 ps
CPU time 0.85 seconds
Started Jul 14 05:18:32 PM PDT 24
Finished Jul 14 05:18:34 PM PDT 24
Peak memory 196076 kb
Host smart-70360851-7054-426d-937b-94e8ad79a857
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794369109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2794369109
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3096735744
Short name T213
Test name
Test status
Simulation time 25530221 ps
CPU time 1.13 seconds
Started Jul 14 05:18:39 PM PDT 24
Finished Jul 14 05:18:41 PM PDT 24
Peak memory 198516 kb
Host smart-0d1c1b41-a25c-48ee-b3d0-03bf7cbe734a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096735744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3096735744
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.632022304
Short name T270
Test name
Test status
Simulation time 352889883 ps
CPU time 1.49 seconds
Started Jul 14 05:18:32 PM PDT 24
Finished Jul 14 05:18:34 PM PDT 24
Peak memory 196208 kb
Host smart-ad6da176-a188-4296-917a-ef42b5eea48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632022304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.632022304
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.2047620202
Short name T312
Test name
Test status
Simulation time 42119060 ps
CPU time 1.1 seconds
Started Jul 14 05:18:34 PM PDT 24
Finished Jul 14 05:18:35 PM PDT 24
Peak memory 196492 kb
Host smart-fd48c980-a2f3-4282-9c04-e5b6046a33ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047620202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2047620202
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2917899512
Short name T496
Test name
Test status
Simulation time 14675140085 ps
CPU time 184.49 seconds
Started Jul 14 05:18:40 PM PDT 24
Finished Jul 14 05:21:45 PM PDT 24
Peak memory 198676 kb
Host smart-a1bb528f-ef88-4ac2-a2fa-6f4ae37b996f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917899512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2917899512
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.951379347
Short name T666
Test name
Test status
Simulation time 60296083622 ps
CPU time 1486.13 seconds
Started Jul 14 05:18:38 PM PDT 24
Finished Jul 14 05:43:25 PM PDT 24
Peak memory 198936 kb
Host smart-1fdbd87f-2784-4f0c-82e7-9e742aa70070
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=951379347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.951379347
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.600864198
Short name T568
Test name
Test status
Simulation time 29378887 ps
CPU time 0.53 seconds
Started Jul 14 05:18:48 PM PDT 24
Finished Jul 14 05:18:49 PM PDT 24
Peak memory 194528 kb
Host smart-b309d476-879f-4c68-bd1e-28a1765dd0fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600864198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.600864198
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.1004158371
Short name T493
Test name
Test status
Simulation time 30290531 ps
CPU time 0.9 seconds
Started Jul 14 05:18:42 PM PDT 24
Finished Jul 14 05:18:44 PM PDT 24
Peak memory 196272 kb
Host smart-8aa94f5c-c026-476a-b735-ac0d30137813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004158371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.1004158371
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2639458824
Short name T618
Test name
Test status
Simulation time 341075863 ps
CPU time 18.26 seconds
Started Jul 14 05:18:45 PM PDT 24
Finished Jul 14 05:19:04 PM PDT 24
Peak memory 197196 kb
Host smart-2231b26a-a745-454b-9b85-22dec9f07704
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639458824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2639458824
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.453761421
Short name T696
Test name
Test status
Simulation time 43591794 ps
CPU time 0.79 seconds
Started Jul 14 05:18:44 PM PDT 24
Finished Jul 14 05:18:45 PM PDT 24
Peak memory 196428 kb
Host smart-53a8656d-73f1-427e-b463-57baf1157e03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453761421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.453761421
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3941469563
Short name T113
Test name
Test status
Simulation time 240708508 ps
CPU time 1.36 seconds
Started Jul 14 05:18:38 PM PDT 24
Finished Jul 14 05:18:40 PM PDT 24
Peak memory 197724 kb
Host smart-3eff9baf-47f0-47ab-b99f-a9ef90503447
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941469563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3941469563
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3835858225
Short name T448
Test name
Test status
Simulation time 73152988 ps
CPU time 2.83 seconds
Started Jul 14 05:18:58 PM PDT 24
Finished Jul 14 05:19:01 PM PDT 24
Peak memory 198604 kb
Host smart-b28f87b7-055d-4b7e-90e4-217c17083d6d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835858225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3835858225
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.890565957
Short name T208
Test name
Test status
Simulation time 789331291 ps
CPU time 3.14 seconds
Started Jul 14 05:18:40 PM PDT 24
Finished Jul 14 05:18:44 PM PDT 24
Peak memory 198692 kb
Host smart-d666afd5-8928-48bd-a938-bf11a74388e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890565957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.
890565957
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.3083241743
Short name T643
Test name
Test status
Simulation time 221436333 ps
CPU time 1.3 seconds
Started Jul 14 05:18:40 PM PDT 24
Finished Jul 14 05:18:42 PM PDT 24
Peak memory 196452 kb
Host smart-83d6e67f-ec41-4bf4-958c-78d87befcc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083241743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.3083241743
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.309739196
Short name T264
Test name
Test status
Simulation time 109406849 ps
CPU time 0.85 seconds
Started Jul 14 05:18:39 PM PDT 24
Finished Jul 14 05:18:41 PM PDT 24
Peak memory 196676 kb
Host smart-ed078703-22fe-4f48-bc95-118966f9b40e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309739196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup
_pulldown.309739196
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.559721116
Short name T471
Test name
Test status
Simulation time 243018152 ps
CPU time 2.69 seconds
Started Jul 14 05:18:45 PM PDT 24
Finished Jul 14 05:18:48 PM PDT 24
Peak memory 198524 kb
Host smart-36749696-2fd8-41a2-89f5-203c92f1a65e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559721116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.559721116
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.412766692
Short name T155
Test name
Test status
Simulation time 129231399 ps
CPU time 1.48 seconds
Started Jul 14 05:18:39 PM PDT 24
Finished Jul 14 05:18:41 PM PDT 24
Peak memory 197336 kb
Host smart-cece2f42-13f6-48e3-8645-237deea58cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412766692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.412766692
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2818769758
Short name T237
Test name
Test status
Simulation time 211207960 ps
CPU time 1.42 seconds
Started Jul 14 05:18:41 PM PDT 24
Finished Jul 14 05:18:43 PM PDT 24
Peak memory 198620 kb
Host smart-17f1e33d-5e95-4780-a54d-c20a1c0a4ac2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818769758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2818769758
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.979700479
Short name T421
Test name
Test status
Simulation time 12019475885 ps
CPU time 171.12 seconds
Started Jul 14 05:18:46 PM PDT 24
Finished Jul 14 05:21:37 PM PDT 24
Peak memory 198716 kb
Host smart-fd9fddf9-7988-44c5-88f2-f93264d74ce3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979700479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.979700479
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3267604617
Short name T285
Test name
Test status
Simulation time 38803381 ps
CPU time 0.7 seconds
Started Jul 14 05:19:06 PM PDT 24
Finished Jul 14 05:19:08 PM PDT 24
Peak memory 195392 kb
Host smart-7bd34762-e1cb-4d7d-9b2d-8faef5cc6e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267604617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3267604617
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2156336580
Short name T633
Test name
Test status
Simulation time 1904099625 ps
CPU time 10.78 seconds
Started Jul 14 05:19:06 PM PDT 24
Finished Jul 14 05:19:18 PM PDT 24
Peak memory 198540 kb
Host smart-8b5ce253-f2ad-4eed-8dd5-638fc2252d58
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156336580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2156336580
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.3099369188
Short name T402
Test name
Test status
Simulation time 87039813 ps
CPU time 0.74 seconds
Started Jul 14 05:18:52 PM PDT 24
Finished Jul 14 05:18:54 PM PDT 24
Peak memory 196468 kb
Host smart-fe78ef90-311d-4b9f-a98d-04027550d6b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099369188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3099369188
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.1449774235
Short name T687
Test name
Test status
Simulation time 31441340 ps
CPU time 0.85 seconds
Started Jul 14 05:19:08 PM PDT 24
Finished Jul 14 05:19:09 PM PDT 24
Peak memory 196080 kb
Host smart-f010485f-0c10-4d10-beeb-60ed5608ce2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449774235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.1449774235
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2634450345
Short name T625
Test name
Test status
Simulation time 776571510 ps
CPU time 2.71 seconds
Started Jul 14 05:18:52 PM PDT 24
Finished Jul 14 05:18:55 PM PDT 24
Peak memory 197848 kb
Host smart-8b923ed9-ab3e-4c87-b7e1-936f85ce503b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634450345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2634450345
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1727595576
Short name T595
Test name
Test status
Simulation time 70085569 ps
CPU time 1.46 seconds
Started Jul 14 05:18:53 PM PDT 24
Finished Jul 14 05:18:56 PM PDT 24
Peak memory 198676 kb
Host smart-c8b1bf40-3100-4c69-8a89-4ca2243ad4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727595576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1727595576
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3439697081
Short name T505
Test name
Test status
Simulation time 295099711 ps
CPU time 1.12 seconds
Started Jul 14 05:18:53 PM PDT 24
Finished Jul 14 05:18:56 PM PDT 24
Peak memory 196580 kb
Host smart-926099cf-b750-42b0-b726-6a1cf5b98067
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439697081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3439697081
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.1032565986
Short name T706
Test name
Test status
Simulation time 1596792216 ps
CPU time 5.4 seconds
Started Jul 14 05:19:08 PM PDT 24
Finished Jul 14 05:19:14 PM PDT 24
Peak memory 198520 kb
Host smart-5e02e930-a0aa-405f-a088-d127b229aa76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032565986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.1032565986
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1458391155
Short name T528
Test name
Test status
Simulation time 83455452 ps
CPU time 1.28 seconds
Started Jul 14 05:19:07 PM PDT 24
Finished Jul 14 05:19:09 PM PDT 24
Peak memory 196132 kb
Host smart-78351ae2-c01a-4c22-bb3b-e35115ae6c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458391155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1458391155
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3802730251
Short name T131
Test name
Test status
Simulation time 150067078 ps
CPU time 1.5 seconds
Started Jul 14 05:18:52 PM PDT 24
Finished Jul 14 05:18:54 PM PDT 24
Peak memory 196820 kb
Host smart-aa3c60ac-e66e-4d20-8998-f944a5e80bd0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802730251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3802730251
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.404384443
Short name T198
Test name
Test status
Simulation time 6264811316 ps
CPU time 37.47 seconds
Started Jul 14 05:19:08 PM PDT 24
Finished Jul 14 05:19:46 PM PDT 24
Peak memory 198688 kb
Host smart-f18467a9-6970-48ba-9e7d-3933f1e67bf3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404384443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.g
pio_stress_all.404384443
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.930986620
Short name T76
Test name
Test status
Simulation time 186418033554 ps
CPU time 2189.45 seconds
Started Jul 14 05:19:09 PM PDT 24
Finished Jul 14 05:55:39 PM PDT 24
Peak memory 198844 kb
Host smart-2d526413-5544-431d-a373-eab4e84d6d2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=930986620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.930986620
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.98772080
Short name T379
Test name
Test status
Simulation time 14427818 ps
CPU time 0.55 seconds
Started Jul 14 05:19:03 PM PDT 24
Finished Jul 14 05:19:03 PM PDT 24
Peak memory 195192 kb
Host smart-a05880bd-e16e-49ef-afbc-becffe93b9b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98772080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.98772080
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3288297961
Short name T266
Test name
Test status
Simulation time 32093363 ps
CPU time 0.94 seconds
Started Jul 14 05:19:00 PM PDT 24
Finished Jul 14 05:19:01 PM PDT 24
Peak memory 197016 kb
Host smart-45da6b99-4295-4128-8c1b-68e743e9bf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288297961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3288297961
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.1835171954
Short name T526
Test name
Test status
Simulation time 724003530 ps
CPU time 11.03 seconds
Started Jul 14 05:19:00 PM PDT 24
Finished Jul 14 05:19:11 PM PDT 24
Peak memory 196088 kb
Host smart-08f593ae-ef70-4853-9466-543ec24ea8ba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835171954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.1835171954
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.3760548202
Short name T678
Test name
Test status
Simulation time 259508341 ps
CPU time 0.99 seconds
Started Jul 14 05:18:57 PM PDT 24
Finished Jul 14 05:18:58 PM PDT 24
Peak memory 196900 kb
Host smart-ec13a5d0-d1ef-4511-9385-f3ea16b42c37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760548202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3760548202
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1099243073
Short name T667
Test name
Test status
Simulation time 186905327 ps
CPU time 0.98 seconds
Started Jul 14 05:19:01 PM PDT 24
Finished Jul 14 05:19:03 PM PDT 24
Peak memory 198064 kb
Host smart-608ab529-915c-4fb7-8562-5d4fbfe52be8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099243073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1099243073
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1651136108
Short name T382
Test name
Test status
Simulation time 85808839 ps
CPU time 3.61 seconds
Started Jul 14 05:18:57 PM PDT 24
Finished Jul 14 05:19:01 PM PDT 24
Peak memory 198608 kb
Host smart-da9cf88e-8261-4dd3-9743-e66e55137c69
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651136108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1651136108
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.1965234637
Short name T347
Test name
Test status
Simulation time 856558205 ps
CPU time 3.01 seconds
Started Jul 14 05:18:57 PM PDT 24
Finished Jul 14 05:19:01 PM PDT 24
Peak memory 196332 kb
Host smart-6d271053-d3b3-41b9-9785-676fc73e280f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965234637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.1965234637
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2019406593
Short name T488
Test name
Test status
Simulation time 290648993 ps
CPU time 1.27 seconds
Started Jul 14 05:18:50 PM PDT 24
Finished Jul 14 05:18:52 PM PDT 24
Peak memory 197668 kb
Host smart-0ee8733c-4f00-4135-8f22-daf146c78e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019406593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2019406593
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3928935976
Short name T562
Test name
Test status
Simulation time 27886477 ps
CPU time 1.09 seconds
Started Jul 14 05:18:59 PM PDT 24
Finished Jul 14 05:19:01 PM PDT 24
Peak memory 197340 kb
Host smart-53ea4b4e-dd84-425c-a739-2385bb88d1b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928935976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3928935976
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.4080066616
Short name T238
Test name
Test status
Simulation time 357127000 ps
CPU time 3.26 seconds
Started Jul 14 05:18:58 PM PDT 24
Finished Jul 14 05:19:02 PM PDT 24
Peak memory 198524 kb
Host smart-1fd3e3fb-98d9-4d62-b974-005657376dea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080066616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.4080066616
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3757903142
Short name T229
Test name
Test status
Simulation time 29961145 ps
CPU time 0.85 seconds
Started Jul 14 05:18:52 PM PDT 24
Finished Jul 14 05:18:53 PM PDT 24
Peak memory 196552 kb
Host smart-691d0b7c-e5a6-42a7-ad4e-f0c144b54b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757903142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3757903142
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1528351372
Short name T615
Test name
Test status
Simulation time 96724257 ps
CPU time 1.02 seconds
Started Jul 14 05:18:51 PM PDT 24
Finished Jul 14 05:18:53 PM PDT 24
Peak memory 196424 kb
Host smart-bb02bba6-fc71-4dfd-9d06-2755709eb1b8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528351372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1528351372
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1289716830
Short name T650
Test name
Test status
Simulation time 83313245489 ps
CPU time 164.48 seconds
Started Jul 14 05:19:00 PM PDT 24
Finished Jul 14 05:21:45 PM PDT 24
Peak memory 198660 kb
Host smart-8224b075-a212-4eca-88b2-471daef4fd4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289716830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1289716830
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.1687925144
Short name T56
Test name
Test status
Simulation time 74445528370 ps
CPU time 1738.73 seconds
Started Jul 14 05:19:02 PM PDT 24
Finished Jul 14 05:48:02 PM PDT 24
Peak memory 198924 kb
Host smart-adecdb1e-ef5f-4150-8972-7b2fc29d9a2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1687925144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.1687925144
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2499602157
Short name T545
Test name
Test status
Simulation time 39519247 ps
CPU time 0.57 seconds
Started Jul 14 05:19:04 PM PDT 24
Finished Jul 14 05:19:05 PM PDT 24
Peak memory 195236 kb
Host smart-93925740-799c-422d-95eb-faa3a93740d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499602157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2499602157
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2412035526
Short name T227
Test name
Test status
Simulation time 32205403 ps
CPU time 0.95 seconds
Started Jul 14 05:19:05 PM PDT 24
Finished Jul 14 05:19:06 PM PDT 24
Peak memory 196516 kb
Host smart-edc27c0d-10ca-46d8-933a-4a2d38d69064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412035526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2412035526
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.3291918302
Short name T377
Test name
Test status
Simulation time 683300054 ps
CPU time 18.02 seconds
Started Jul 14 05:19:02 PM PDT 24
Finished Jul 14 05:19:21 PM PDT 24
Peak memory 197152 kb
Host smart-dd440d74-3419-4b0d-b076-a5a44272e768
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291918302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.3291918302
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.3012243190
Short name T443
Test name
Test status
Simulation time 24372334 ps
CPU time 0.68 seconds
Started Jul 14 05:19:05 PM PDT 24
Finished Jul 14 05:19:07 PM PDT 24
Peak memory 196000 kb
Host smart-1767efff-2a82-4146-b8d3-885a27669340
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012243190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.3012243190
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.1712382038
Short name T69
Test name
Test status
Simulation time 99410190 ps
CPU time 0.73 seconds
Started Jul 14 05:19:06 PM PDT 24
Finished Jul 14 05:19:07 PM PDT 24
Peak memory 194920 kb
Host smart-6518e53b-7a3b-4ba7-86d5-88bfe28b7b39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712382038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.1712382038
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1141032941
Short name T470
Test name
Test status
Simulation time 98293666 ps
CPU time 1.19 seconds
Started Jul 14 05:19:05 PM PDT 24
Finished Jul 14 05:19:06 PM PDT 24
Peak memory 197436 kb
Host smart-98b0bc27-77d7-478d-9c50-0550a4e80393
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141032941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.1141032941
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3148733544
Short name T157
Test name
Test status
Simulation time 165894541 ps
CPU time 2.53 seconds
Started Jul 14 05:19:03 PM PDT 24
Finished Jul 14 05:19:06 PM PDT 24
Peak memory 196456 kb
Host smart-bb49adac-4a84-4ffb-98f3-22ad20854958
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148733544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3148733544
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2350839051
Short name T124
Test name
Test status
Simulation time 59271889 ps
CPU time 1.26 seconds
Started Jul 14 05:19:03 PM PDT 24
Finished Jul 14 05:19:04 PM PDT 24
Peak memory 196508 kb
Host smart-8d0a0ade-de4e-4a7a-aec7-fdb59a49e7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350839051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2350839051
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.4252034306
Short name T168
Test name
Test status
Simulation time 171269598 ps
CPU time 1.26 seconds
Started Jul 14 05:19:04 PM PDT 24
Finished Jul 14 05:19:06 PM PDT 24
Peak memory 197528 kb
Host smart-488338bb-80d6-4514-92ae-09af4d027640
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252034306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.4252034306
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3341739253
Short name T177
Test name
Test status
Simulation time 76518577 ps
CPU time 1.13 seconds
Started Jul 14 05:19:05 PM PDT 24
Finished Jul 14 05:19:07 PM PDT 24
Peak memory 197404 kb
Host smart-09b61847-6d36-403a-996a-e92f8e25d59b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341739253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3341739253
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.3583031935
Short name T262
Test name
Test status
Simulation time 151784099 ps
CPU time 1.4 seconds
Started Jul 14 05:19:07 PM PDT 24
Finished Jul 14 05:19:09 PM PDT 24
Peak memory 198632 kb
Host smart-3e995fe9-2a56-4425-8d87-bd2f8692990a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583031935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3583031935
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1629311260
Short name T676
Test name
Test status
Simulation time 108160866 ps
CPU time 0.92 seconds
Started Jul 14 05:19:03 PM PDT 24
Finished Jul 14 05:19:05 PM PDT 24
Peak memory 197092 kb
Host smart-8cb2dfc1-ec4e-4e22-b0ae-b69589147c6c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629311260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1629311260
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2758913939
Short name T440
Test name
Test status
Simulation time 27517574576 ps
CPU time 188.93 seconds
Started Jul 14 05:19:06 PM PDT 24
Finished Jul 14 05:22:16 PM PDT 24
Peak memory 198616 kb
Host smart-b6e1984c-2acf-4997-92ba-b960e156f89b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758913939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2758913939
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3047323667
Short name T295
Test name
Test status
Simulation time 22411109 ps
CPU time 0.56 seconds
Started Jul 14 05:19:19 PM PDT 24
Finished Jul 14 05:19:21 PM PDT 24
Peak memory 195228 kb
Host smart-ff618f88-a538-4e46-a952-439ff0ddb218
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047323667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3047323667
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.3766363343
Short name T189
Test name
Test status
Simulation time 172784906 ps
CPU time 0.79 seconds
Started Jul 14 05:19:13 PM PDT 24
Finished Jul 14 05:19:15 PM PDT 24
Peak memory 196044 kb
Host smart-bacd9d1c-bdf0-4afa-b4c4-68df1871c033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766363343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.3766363343
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.4013317395
Short name T47
Test name
Test status
Simulation time 1686860717 ps
CPU time 22.99 seconds
Started Jul 14 05:19:13 PM PDT 24
Finished Jul 14 05:19:36 PM PDT 24
Peak memory 197076 kb
Host smart-ab5464d3-6aba-4856-b5fb-586b6261eaac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013317395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.4013317395
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1927455969
Short name T20
Test name
Test status
Simulation time 324233713 ps
CPU time 0.99 seconds
Started Jul 14 05:19:18 PM PDT 24
Finished Jul 14 05:19:20 PM PDT 24
Peak memory 197200 kb
Host smart-67ae6f18-835a-4c98-9d68-6f9b0204b53c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927455969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1927455969
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.576472328
Short name T65
Test name
Test status
Simulation time 50127245 ps
CPU time 1 seconds
Started Jul 14 05:19:11 PM PDT 24
Finished Jul 14 05:19:12 PM PDT 24
Peak memory 196676 kb
Host smart-f4c0a99d-f4ae-49fe-824d-ded806ea628f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576472328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.576472328
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.909966664
Short name T503
Test name
Test status
Simulation time 67172034 ps
CPU time 2.82 seconds
Started Jul 14 05:19:13 PM PDT 24
Finished Jul 14 05:19:17 PM PDT 24
Peak memory 198704 kb
Host smart-bf595a28-2297-4a9c-9f44-b79c3068bb8c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909966664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.gpio_intr_with_filter_rand_intr_event.909966664
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2752745127
Short name T165
Test name
Test status
Simulation time 99860272 ps
CPU time 1.98 seconds
Started Jul 14 05:19:11 PM PDT 24
Finished Jul 14 05:19:13 PM PDT 24
Peak memory 196784 kb
Host smart-89f8ba52-9a8c-4b0d-8379-be94ecb22efd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752745127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2752745127
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.2246124893
Short name T111
Test name
Test status
Simulation time 171236510 ps
CPU time 0.72 seconds
Started Jul 14 05:19:12 PM PDT 24
Finished Jul 14 05:19:13 PM PDT 24
Peak memory 194936 kb
Host smart-e6f41555-d7aa-414b-91b2-a5516afdbd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246124893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2246124893
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.2662692416
Short name T74
Test name
Test status
Simulation time 38931773 ps
CPU time 0.65 seconds
Started Jul 14 05:19:10 PM PDT 24
Finished Jul 14 05:19:11 PM PDT 24
Peak memory 194864 kb
Host smart-5183202e-ea51-49ad-821c-dc90faf50c61
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662692416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.2662692416
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.827098799
Short name T542
Test name
Test status
Simulation time 2391118046 ps
CPU time 6.52 seconds
Started Jul 14 05:19:19 PM PDT 24
Finished Jul 14 05:19:26 PM PDT 24
Peak memory 198652 kb
Host smart-b4a5da5a-499b-451e-97f8-3ea817225adc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827098799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.827098799
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3978736173
Short name T704
Test name
Test status
Simulation time 96083384 ps
CPU time 1.54 seconds
Started Jul 14 05:19:12 PM PDT 24
Finished Jul 14 05:19:14 PM PDT 24
Peak memory 197324 kb
Host smart-80bb4d99-0b1a-41de-8d4d-c3cfd31badeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978736173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3978736173
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.2166575798
Short name T207
Test name
Test status
Simulation time 137819767 ps
CPU time 1 seconds
Started Jul 14 05:19:14 PM PDT 24
Finished Jul 14 05:19:15 PM PDT 24
Peak memory 196344 kb
Host smart-9ee48a7e-df8b-442d-9ac2-03a571a28cee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166575798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2166575798
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.840399390
Short name T280
Test name
Test status
Simulation time 15998927319 ps
CPU time 92.79 seconds
Started Jul 14 05:19:17 PM PDT 24
Finished Jul 14 05:20:50 PM PDT 24
Peak memory 198664 kb
Host smart-46d84419-841c-4267-8b22-37daf540a05d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840399390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.g
pio_stress_all.840399390
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.3070763480
Short name T681
Test name
Test status
Simulation time 11846396 ps
CPU time 0.56 seconds
Started Jul 14 05:19:25 PM PDT 24
Finished Jul 14 05:19:26 PM PDT 24
Peak memory 194548 kb
Host smart-046daa9c-f492-44d2-9f29-54af8ceff054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070763480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.3070763480
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.1586009986
Short name T117
Test name
Test status
Simulation time 50693226 ps
CPU time 0.73 seconds
Started Jul 14 05:19:18 PM PDT 24
Finished Jul 14 05:19:19 PM PDT 24
Peak memory 195380 kb
Host smart-d627092a-88e8-478b-987a-5772603e9e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586009986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.1586009986
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3037052032
Short name T314
Test name
Test status
Simulation time 493033674 ps
CPU time 13.42 seconds
Started Jul 14 05:19:18 PM PDT 24
Finished Jul 14 05:19:32 PM PDT 24
Peak memory 197528 kb
Host smart-e8a575e0-df1e-4ba6-93b1-1c2d9212645c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037052032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3037052032
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.1858977660
Short name T476
Test name
Test status
Simulation time 104180237 ps
CPU time 0.66 seconds
Started Jul 14 05:19:24 PM PDT 24
Finished Jul 14 05:19:25 PM PDT 24
Peak memory 195088 kb
Host smart-c318acc8-a04f-4bd9-b914-4f9d4d1edf33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858977660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1858977660
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1248370294
Short name T277
Test name
Test status
Simulation time 20615111 ps
CPU time 0.76 seconds
Started Jul 14 05:19:17 PM PDT 24
Finished Jul 14 05:19:19 PM PDT 24
Peak memory 195872 kb
Host smart-d67b3c3f-f4a7-44bf-81f0-aa4646df9ca4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248370294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1248370294
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.324970346
Short name T620
Test name
Test status
Simulation time 43812476 ps
CPU time 1.99 seconds
Started Jul 14 05:19:19 PM PDT 24
Finished Jul 14 05:19:21 PM PDT 24
Peak memory 197288 kb
Host smart-ecf2d825-1bcc-4729-916d-0fd0d6cf2b34
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324970346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.gpio_intr_with_filter_rand_intr_event.324970346
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.833475148
Short name T63
Test name
Test status
Simulation time 137348188 ps
CPU time 1.36 seconds
Started Jul 14 05:19:19 PM PDT 24
Finished Jul 14 05:19:21 PM PDT 24
Peak memory 197548 kb
Host smart-c4b83bc3-8e92-4ad9-a169-c8c24d2ae494
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833475148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.
833475148
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2957189136
Short name T419
Test name
Test status
Simulation time 280652149 ps
CPU time 1.28 seconds
Started Jul 14 05:19:17 PM PDT 24
Finished Jul 14 05:19:19 PM PDT 24
Peak memory 197524 kb
Host smart-67a49a66-4f64-49bf-a1b8-037d54cad044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957189136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2957189136
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.997012424
Short name T184
Test name
Test status
Simulation time 49406676 ps
CPU time 1.1 seconds
Started Jul 14 05:19:17 PM PDT 24
Finished Jul 14 05:19:18 PM PDT 24
Peak memory 197076 kb
Host smart-4d9aefc5-7bbe-4214-aa65-343aea14b842
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997012424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.997012424
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_smoke.1437640287
Short name T322
Test name
Test status
Simulation time 324446484 ps
CPU time 1.57 seconds
Started Jul 14 05:19:17 PM PDT 24
Finished Jul 14 05:19:19 PM PDT 24
Peak memory 197284 kb
Host smart-7e6e9abf-f11a-4194-9e42-78d37ce1fa79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437640287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.1437640287
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3644545893
Short name T444
Test name
Test status
Simulation time 151500541 ps
CPU time 1.2 seconds
Started Jul 14 05:19:19 PM PDT 24
Finished Jul 14 05:19:21 PM PDT 24
Peak memory 196988 kb
Host smart-efc424cf-17d2-4c24-8e1c-3f0ddda24503
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644545893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3644545893
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1732340026
Short name T465
Test name
Test status
Simulation time 16010060558 ps
CPU time 57.32 seconds
Started Jul 14 05:19:26 PM PDT 24
Finished Jul 14 05:20:24 PM PDT 24
Peak memory 198716 kb
Host smart-3350d3f0-31d8-462f-baf7-74f67f61558c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732340026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1732340026
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.1019297381
Short name T669
Test name
Test status
Simulation time 51399214 ps
CPU time 0.59 seconds
Started Jul 14 05:19:32 PM PDT 24
Finished Jul 14 05:19:34 PM PDT 24
Peak memory 195428 kb
Host smart-8483352c-53aa-4af5-b57e-6e7df05a7ca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019297381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1019297381
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1099014871
Short name T415
Test name
Test status
Simulation time 22979976 ps
CPU time 0.8 seconds
Started Jul 14 05:19:22 PM PDT 24
Finished Jul 14 05:19:23 PM PDT 24
Peak memory 196680 kb
Host smart-51380686-526b-4baa-aa6c-9b0469aff382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099014871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1099014871
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.3566218100
Short name T441
Test name
Test status
Simulation time 1746120999 ps
CPU time 24.64 seconds
Started Jul 14 05:19:31 PM PDT 24
Finished Jul 14 05:19:57 PM PDT 24
Peak memory 197596 kb
Host smart-385095ad-c6fa-44cd-a065-cbc845538244
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566218100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.3566218100
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2623515795
Short name T75
Test name
Test status
Simulation time 367469340 ps
CPU time 1.07 seconds
Started Jul 14 05:19:31 PM PDT 24
Finished Jul 14 05:19:33 PM PDT 24
Peak memory 197144 kb
Host smart-71deaa34-5b94-4928-8212-386fde15eb6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623515795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2623515795
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1950979943
Short name T367
Test name
Test status
Simulation time 190153359 ps
CPU time 1.35 seconds
Started Jul 14 05:19:26 PM PDT 24
Finished Jul 14 05:19:28 PM PDT 24
Peak memory 196520 kb
Host smart-5356dd9e-bd56-43bd-8030-d0552d8a1467
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950979943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1950979943
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.14330933
Short name T333
Test name
Test status
Simulation time 653969003 ps
CPU time 3.42 seconds
Started Jul 14 05:19:31 PM PDT 24
Finished Jul 14 05:19:35 PM PDT 24
Peak memory 198488 kb
Host smart-7cc4ae36-3bff-480c-8835-0388c78057ec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14330933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.gpio_intr_with_filter_rand_intr_event.14330933
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.3848719584
Short name T122
Test name
Test status
Simulation time 262722153 ps
CPU time 3.43 seconds
Started Jul 14 05:19:24 PM PDT 24
Finished Jul 14 05:19:27 PM PDT 24
Peak memory 197216 kb
Host smart-368cb778-1301-4cfc-9136-2ceb2300732a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848719584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.3848719584
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.4127373818
Short name T587
Test name
Test status
Simulation time 47935847 ps
CPU time 1.02 seconds
Started Jul 14 05:19:25 PM PDT 24
Finished Jul 14 05:19:27 PM PDT 24
Peak memory 197220 kb
Host smart-fe624213-aa59-4bae-8c66-e91e33ea35f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127373818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.4127373818
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.2063034882
Short name T72
Test name
Test status
Simulation time 112249668 ps
CPU time 1.22 seconds
Started Jul 14 05:19:23 PM PDT 24
Finished Jul 14 05:19:24 PM PDT 24
Peak memory 197624 kb
Host smart-7a4f8b0b-889e-4769-b836-2fe2e2c9c284
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063034882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.2063034882
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3067347708
Short name T378
Test name
Test status
Simulation time 507594302 ps
CPU time 5.52 seconds
Started Jul 14 05:19:34 PM PDT 24
Finished Jul 14 05:19:40 PM PDT 24
Peak memory 198548 kb
Host smart-7a807968-0c19-41b3-ad0a-effee09394dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067347708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3067347708
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.586319261
Short name T14
Test name
Test status
Simulation time 663098934 ps
CPU time 1.3 seconds
Started Jul 14 05:19:24 PM PDT 24
Finished Jul 14 05:19:26 PM PDT 24
Peak memory 197684 kb
Host smart-a6178763-7b18-4379-8c43-dbc2f1f68ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586319261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.586319261
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2830247832
Short name T457
Test name
Test status
Simulation time 65616988 ps
CPU time 1.34 seconds
Started Jul 14 05:19:28 PM PDT 24
Finished Jul 14 05:19:30 PM PDT 24
Peak memory 197412 kb
Host smart-51c9b5b5-1968-462c-bd09-47a6b26ecf85
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830247832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2830247832
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3080151453
Short name T291
Test name
Test status
Simulation time 6462570716 ps
CPU time 189.19 seconds
Started Jul 14 05:19:31 PM PDT 24
Finished Jul 14 05:22:41 PM PDT 24
Peak memory 198656 kb
Host smart-abcbee9d-8fb0-4b4b-b9e7-2e1ae88fda3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080151453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3080151453
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.1824012522
Short name T613
Test name
Test status
Simulation time 276143020702 ps
CPU time 2025.56 seconds
Started Jul 14 05:19:32 PM PDT 24
Finished Jul 14 05:53:18 PM PDT 24
Peak memory 198920 kb
Host smart-bae55b0f-7f6a-453a-a985-26a91f826f4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1824012522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.1824012522
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.446935856
Short name T269
Test name
Test status
Simulation time 13478852 ps
CPU time 0.58 seconds
Started Jul 14 05:19:39 PM PDT 24
Finished Jul 14 05:19:40 PM PDT 24
Peak memory 194840 kb
Host smart-3c0fdb32-f93c-4d1c-b4ff-eaa0c2893b2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446935856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.446935856
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.1745243174
Short name T605
Test name
Test status
Simulation time 29985435 ps
CPU time 0.92 seconds
Started Jul 14 05:19:31 PM PDT 24
Finished Jul 14 05:19:32 PM PDT 24
Peak memory 196256 kb
Host smart-55f49de1-e20d-4855-a227-f42514bde046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745243174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.1745243174
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2333769853
Short name T549
Test name
Test status
Simulation time 181168344 ps
CPU time 9.67 seconds
Started Jul 14 05:19:40 PM PDT 24
Finished Jul 14 05:19:51 PM PDT 24
Peak memory 197452 kb
Host smart-52370314-a10d-4205-961e-4b296f95ec05
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333769853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2333769853
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3632564764
Short name T319
Test name
Test status
Simulation time 437304134 ps
CPU time 1.1 seconds
Started Jul 14 05:19:39 PM PDT 24
Finished Jul 14 05:19:41 PM PDT 24
Peak memory 197128 kb
Host smart-466d39df-6de6-487e-a142-7765e05531d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632564764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3632564764
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.818940585
Short name T272
Test name
Test status
Simulation time 204859188 ps
CPU time 1.08 seconds
Started Jul 14 05:19:34 PM PDT 24
Finished Jul 14 05:19:35 PM PDT 24
Peak memory 196400 kb
Host smart-e61f6006-1a92-4224-99bb-67d002950b07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818940585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.818940585
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.1640480864
Short name T366
Test name
Test status
Simulation time 37447539 ps
CPU time 1.6 seconds
Started Jul 14 05:19:38 PM PDT 24
Finished Jul 14 05:19:40 PM PDT 24
Peak memory 197432 kb
Host smart-f7d0b3db-df33-4b15-9e2f-c1bc58eb2623
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640480864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.1640480864
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3429952352
Short name T130
Test name
Test status
Simulation time 48077399 ps
CPU time 1.31 seconds
Started Jul 14 05:19:38 PM PDT 24
Finished Jul 14 05:19:40 PM PDT 24
Peak memory 196988 kb
Host smart-3733f2bd-d487-4edf-bce6-5ae2018fb804
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429952352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3429952352
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3264799145
Short name T46
Test name
Test status
Simulation time 16339809 ps
CPU time 0.68 seconds
Started Jul 14 05:19:30 PM PDT 24
Finished Jul 14 05:19:31 PM PDT 24
Peak memory 195520 kb
Host smart-269ae214-7f24-4bcf-b666-5677691eef40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264799145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3264799145
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.962889358
Short name T149
Test name
Test status
Simulation time 65176346 ps
CPU time 1.05 seconds
Started Jul 14 05:19:31 PM PDT 24
Finished Jul 14 05:19:33 PM PDT 24
Peak memory 196452 kb
Host smart-d49c378e-6fac-40e2-8907-19cbd6dc0e5f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962889358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup
_pulldown.962889358
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3062080495
Short name T477
Test name
Test status
Simulation time 756710521 ps
CPU time 2.44 seconds
Started Jul 14 05:19:40 PM PDT 24
Finished Jul 14 05:19:43 PM PDT 24
Peak memory 198372 kb
Host smart-49dca50d-9392-4d1a-b8e9-cab6ab36c1b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062080495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3062080495
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.3806619060
Short name T136
Test name
Test status
Simulation time 288934030 ps
CPU time 1.33 seconds
Started Jul 14 05:19:33 PM PDT 24
Finished Jul 14 05:19:35 PM PDT 24
Peak memory 197360 kb
Host smart-30ba9054-3689-4286-ba22-9aa53aafc0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806619060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.3806619060
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1040282759
Short name T474
Test name
Test status
Simulation time 244570244 ps
CPU time 1.38 seconds
Started Jul 14 05:19:32 PM PDT 24
Finished Jul 14 05:19:34 PM PDT 24
Peak memory 198528 kb
Host smart-8671ac99-360f-4cc0-a067-43a1435ff44b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040282759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1040282759
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.895514094
Short name T2
Test name
Test status
Simulation time 5758925501 ps
CPU time 43.42 seconds
Started Jul 14 05:19:39 PM PDT 24
Finished Jul 14 05:20:23 PM PDT 24
Peak memory 198668 kb
Host smart-1429274f-85d8-4d7e-8604-0721894a88a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895514094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.895514094
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3200087574
Short name T289
Test name
Test status
Simulation time 10881107 ps
CPU time 0.55 seconds
Started Jul 14 05:19:45 PM PDT 24
Finished Jul 14 05:19:46 PM PDT 24
Peak memory 194620 kb
Host smart-92fcea12-0a00-4456-9cc8-72eb1eff232a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200087574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3200087574
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.299535469
Short name T259
Test name
Test status
Simulation time 129671869 ps
CPU time 0.96 seconds
Started Jul 14 05:19:44 PM PDT 24
Finished Jul 14 05:19:45 PM PDT 24
Peak memory 196244 kb
Host smart-e3d129c7-4a22-482f-b725-b7642a30a462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299535469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.299535469
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.964893197
Short name T576
Test name
Test status
Simulation time 219755669 ps
CPU time 6.37 seconds
Started Jul 14 05:19:39 PM PDT 24
Finished Jul 14 05:19:46 PM PDT 24
Peak memory 198548 kb
Host smart-e9365688-fdca-4349-a64d-c98c19bf6aba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964893197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.964893197
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2420753696
Short name T42
Test name
Test status
Simulation time 273433913 ps
CPU time 0.98 seconds
Started Jul 14 05:19:49 PM PDT 24
Finished Jul 14 05:19:51 PM PDT 24
Peak memory 197076 kb
Host smart-bd8bd84b-af9d-4ab2-84e4-db67cedec2ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420753696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2420753696
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1698888379
Short name T396
Test name
Test status
Simulation time 41209492 ps
CPU time 0.84 seconds
Started Jul 14 05:19:38 PM PDT 24
Finished Jul 14 05:19:40 PM PDT 24
Peak memory 196120 kb
Host smart-4ab46fda-afd7-42d0-b10d-d089da6d4532
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698888379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1698888379
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.459316580
Short name T437
Test name
Test status
Simulation time 89814547 ps
CPU time 3.31 seconds
Started Jul 14 05:19:38 PM PDT 24
Finished Jul 14 05:19:42 PM PDT 24
Peak memory 198512 kb
Host smart-42b55fd8-a6f3-4c0e-a897-2d305c9533fe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459316580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.gpio_intr_with_filter_rand_intr_event.459316580
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1553644381
Short name T653
Test name
Test status
Simulation time 148154926 ps
CPU time 3.47 seconds
Started Jul 14 05:19:38 PM PDT 24
Finished Jul 14 05:19:42 PM PDT 24
Peak memory 198624 kb
Host smart-74881305-14dd-4e84-8419-987d8ba1d19c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553644381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1553644381
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.426453813
Short name T201
Test name
Test status
Simulation time 28573294 ps
CPU time 0.86 seconds
Started Jul 14 05:19:39 PM PDT 24
Finished Jul 14 05:19:41 PM PDT 24
Peak memory 196088 kb
Host smart-44567bfc-915d-463c-a1b3-97103e922c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426453813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.426453813
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3325894861
Short name T384
Test name
Test status
Simulation time 701095356 ps
CPU time 1.23 seconds
Started Jul 14 05:19:38 PM PDT 24
Finished Jul 14 05:19:40 PM PDT 24
Peak memory 197260 kb
Host smart-0ce0b623-6fd4-4b30-80e8-6b687db59a32
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325894861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3325894861
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.3076489368
Short name T371
Test name
Test status
Simulation time 225299246 ps
CPU time 5.34 seconds
Started Jul 14 05:19:47 PM PDT 24
Finished Jul 14 05:19:53 PM PDT 24
Peak memory 198624 kb
Host smart-38fd81f9-8b24-4be5-a65c-9e82c4bb2639
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076489368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.3076489368
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1975270794
Short name T190
Test name
Test status
Simulation time 55289989 ps
CPU time 1.21 seconds
Started Jul 14 05:19:40 PM PDT 24
Finished Jul 14 05:19:42 PM PDT 24
Peak memory 196244 kb
Host smart-9e5c313c-4c41-4f7c-ac66-cc7d2951fc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975270794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1975270794
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.49679025
Short name T657
Test name
Test status
Simulation time 82717685 ps
CPU time 0.86 seconds
Started Jul 14 05:19:40 PM PDT 24
Finished Jul 14 05:19:42 PM PDT 24
Peak memory 195956 kb
Host smart-1c748788-5cba-4ba1-bddd-8c41adf2c25c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49679025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.49679025
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.2323526624
Short name T73
Test name
Test status
Simulation time 15527705251 ps
CPU time 185.88 seconds
Started Jul 14 05:19:45 PM PDT 24
Finished Jul 14 05:22:51 PM PDT 24
Peak memory 198656 kb
Host smart-525ac29b-dacb-41fd-85d7-eb3cbaee8ab3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323526624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.2323526624
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.3461441814
Short name T700
Test name
Test status
Simulation time 96340824122 ps
CPU time 2006.81 seconds
Started Jul 14 05:19:47 PM PDT 24
Finished Jul 14 05:53:14 PM PDT 24
Peak memory 198792 kb
Host smart-bec06804-a009-43e7-baf6-f449603a15c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3461441814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.3461441814
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.1742971236
Short name T34
Test name
Test status
Simulation time 16138592 ps
CPU time 0.57 seconds
Started Jul 14 05:17:33 PM PDT 24
Finished Jul 14 05:17:33 PM PDT 24
Peak memory 195228 kb
Host smart-79205cd9-ecda-4ea4-9f73-361339e47e06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742971236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1742971236
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3369718941
Short name T173
Test name
Test status
Simulation time 55836590 ps
CPU time 0.78 seconds
Started Jul 14 05:17:18 PM PDT 24
Finished Jul 14 05:17:19 PM PDT 24
Peak memory 196344 kb
Host smart-f49bf2f9-f893-4dba-a99a-53551a30c600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369718941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3369718941
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.718817992
Short name T641
Test name
Test status
Simulation time 1092089854 ps
CPU time 19.28 seconds
Started Jul 14 05:17:26 PM PDT 24
Finished Jul 14 05:17:45 PM PDT 24
Peak memory 197436 kb
Host smart-2ca1d778-8cd7-4f17-9a77-888f371bf6a6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718817992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stress
.718817992
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.3422982441
Short name T375
Test name
Test status
Simulation time 87011412 ps
CPU time 1.07 seconds
Started Jul 14 05:17:24 PM PDT 24
Finished Jul 14 05:17:25 PM PDT 24
Peak memory 197848 kb
Host smart-76c79f27-9350-446c-b174-65ee30a76627
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422982441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.3422982441
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2940436446
Short name T515
Test name
Test status
Simulation time 112187046 ps
CPU time 0.98 seconds
Started Jul 14 05:17:19 PM PDT 24
Finished Jul 14 05:17:21 PM PDT 24
Peak memory 196648 kb
Host smart-e10e5251-c7ab-4a2b-b44f-b38a1cb65ad9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940436446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2940436446
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2970542593
Short name T686
Test name
Test status
Simulation time 41518597 ps
CPU time 1.8 seconds
Started Jul 14 05:17:24 PM PDT 24
Finished Jul 14 05:17:26 PM PDT 24
Peak memory 197416 kb
Host smart-0cacb66a-3a60-49c9-96b8-a27f3ef4358a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970542593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2970542593
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.35973222
Short name T607
Test name
Test status
Simulation time 164436687 ps
CPU time 2.09 seconds
Started Jul 14 05:17:26 PM PDT 24
Finished Jul 14 05:17:28 PM PDT 24
Peak memory 196396 kb
Host smart-74119605-e50f-4115-87d6-b425585fb29e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35973222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.35973222
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.985159537
Short name T48
Test name
Test status
Simulation time 79146638 ps
CPU time 1.55 seconds
Started Jul 14 05:17:19 PM PDT 24
Finished Jul 14 05:17:21 PM PDT 24
Peak memory 197504 kb
Host smart-e6fc94e2-fd37-4361-b2f0-41c841ded61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985159537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.985159537
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.410171096
Short name T185
Test name
Test status
Simulation time 75382929 ps
CPU time 0.91 seconds
Started Jul 14 05:17:18 PM PDT 24
Finished Jul 14 05:17:20 PM PDT 24
Peak memory 196564 kb
Host smart-6655f77c-03ea-4ca1-906d-ab32ff8c6211
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410171096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_
pulldown.410171096
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3673023955
Short name T464
Test name
Test status
Simulation time 243802469 ps
CPU time 3.93 seconds
Started Jul 14 05:17:23 PM PDT 24
Finished Jul 14 05:17:27 PM PDT 24
Peak memory 198432 kb
Host smart-46c33993-6083-4c8c-a15a-233f286cc772
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673023955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3673023955
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.2094130108
Short name T43
Test name
Test status
Simulation time 154146167 ps
CPU time 0.78 seconds
Started Jul 14 05:17:23 PM PDT 24
Finished Jul 14 05:17:25 PM PDT 24
Peak memory 214168 kb
Host smart-3e8fa6ed-8d17-438f-ac5b-f9791b7014d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094130108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.2094130108
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.3143737444
Short name T232
Test name
Test status
Simulation time 77582401 ps
CPU time 1.02 seconds
Started Jul 14 05:17:18 PM PDT 24
Finished Jul 14 05:17:19 PM PDT 24
Peak memory 197036 kb
Host smart-69581c60-4978-4158-86ae-a642a4762b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143737444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3143737444
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3886090359
Short name T128
Test name
Test status
Simulation time 84257492 ps
CPU time 1.04 seconds
Started Jul 14 05:17:18 PM PDT 24
Finished Jul 14 05:17:19 PM PDT 24
Peak memory 196828 kb
Host smart-4f1236ce-6308-4152-b946-a8dd398f22d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886090359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3886090359
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.4141692580
Short name T132
Test name
Test status
Simulation time 9119538848 ps
CPU time 131.97 seconds
Started Jul 14 05:17:24 PM PDT 24
Finished Jul 14 05:19:36 PM PDT 24
Peak memory 198776 kb
Host smart-02047930-dc7a-48cd-bf08-cda2f7627bc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141692580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.4141692580
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.534635278
Short name T25
Test name
Test status
Simulation time 32747950353 ps
CPU time 580.83 seconds
Started Jul 14 05:17:24 PM PDT 24
Finished Jul 14 05:27:06 PM PDT 24
Peak memory 198792 kb
Host smart-65fc49cb-f9ab-469f-9d77-2fbd6db79602
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=534635278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.534635278
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1474842979
Short name T630
Test name
Test status
Simulation time 45581853 ps
CPU time 0.57 seconds
Started Jul 14 05:19:52 PM PDT 24
Finished Jul 14 05:19:53 PM PDT 24
Peak memory 194736 kb
Host smart-14e5e0f9-ed18-4ed1-b29a-7385b555fa3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474842979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1474842979
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.634364260
Short name T284
Test name
Test status
Simulation time 22052973 ps
CPU time 0.79 seconds
Started Jul 14 05:19:46 PM PDT 24
Finished Jul 14 05:19:48 PM PDT 24
Peak memory 195848 kb
Host smart-ad772c0b-01a4-40a6-bb61-e2759b9ba7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634364260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.634364260
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1758348820
Short name T596
Test name
Test status
Simulation time 267119618 ps
CPU time 13.52 seconds
Started Jul 14 05:19:49 PM PDT 24
Finished Jul 14 05:20:03 PM PDT 24
Peak memory 196776 kb
Host smart-c8e475ca-afe3-4b49-8746-5ab5dc49687e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758348820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1758348820
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2173915945
Short name T422
Test name
Test status
Simulation time 97364275 ps
CPU time 1.02 seconds
Started Jul 14 05:19:51 PM PDT 24
Finished Jul 14 05:19:52 PM PDT 24
Peak memory 196980 kb
Host smart-2d13acab-317a-472e-94cd-1ff2bb8609d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173915945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2173915945
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2515273439
Short name T316
Test name
Test status
Simulation time 174242920 ps
CPU time 0.94 seconds
Started Jul 14 05:19:47 PM PDT 24
Finished Jul 14 05:19:48 PM PDT 24
Peak memory 197420 kb
Host smart-e456a305-14a0-4b12-b4ec-08793c2b1c75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515273439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2515273439
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3264878197
Short name T158
Test name
Test status
Simulation time 93733061 ps
CPU time 4.02 seconds
Started Jul 14 05:19:46 PM PDT 24
Finished Jul 14 05:19:50 PM PDT 24
Peak memory 198572 kb
Host smart-cbd98328-0123-412c-867e-ca20a0536a30
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264878197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3264878197
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.630910724
Short name T614
Test name
Test status
Simulation time 451597356 ps
CPU time 3.44 seconds
Started Jul 14 05:19:44 PM PDT 24
Finished Jul 14 05:19:48 PM PDT 24
Peak memory 197128 kb
Host smart-ca5f06d7-3061-426c-88e8-076037bb1deb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630910724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger.
630910724
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1097780323
Short name T664
Test name
Test status
Simulation time 34824550 ps
CPU time 0.86 seconds
Started Jul 14 05:19:46 PM PDT 24
Finished Jul 14 05:19:47 PM PDT 24
Peak memory 197656 kb
Host smart-5583c25b-1dd6-4d30-87b7-bafacb7bfa6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097780323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1097780323
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.698407160
Short name T609
Test name
Test status
Simulation time 35435199 ps
CPU time 0.92 seconds
Started Jul 14 05:19:52 PM PDT 24
Finished Jul 14 05:19:53 PM PDT 24
Peak memory 197316 kb
Host smart-fc91aa70-816c-4c1d-922b-071780884447
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698407160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullup
_pulldown.698407160
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.184545172
Short name T51
Test name
Test status
Simulation time 1053797053 ps
CPU time 4.87 seconds
Started Jul 14 05:19:48 PM PDT 24
Finished Jul 14 05:19:54 PM PDT 24
Peak memory 198604 kb
Host smart-0dbe791b-ff1c-4b35-8a0b-a7431859fba7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184545172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.184545172
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1802873101
Short name T318
Test name
Test status
Simulation time 59952901 ps
CPU time 1.11 seconds
Started Jul 14 05:19:52 PM PDT 24
Finished Jul 14 05:19:54 PM PDT 24
Peak memory 196352 kb
Host smart-9772a4ad-89e9-4e54-b34a-17097985df66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802873101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1802873101
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.288227516
Short name T317
Test name
Test status
Simulation time 269323464 ps
CPU time 1.25 seconds
Started Jul 14 05:19:49 PM PDT 24
Finished Jul 14 05:19:51 PM PDT 24
Peak memory 197316 kb
Host smart-8fce2486-87da-44b5-b860-b44481f5c10a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288227516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.288227516
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.4245467371
Short name T4
Test name
Test status
Simulation time 40514019408 ps
CPU time 245.51 seconds
Started Jul 14 05:19:48 PM PDT 24
Finished Jul 14 05:23:54 PM PDT 24
Peak memory 198720 kb
Host smart-3ae4182c-b71d-4f07-921c-db577df78a88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245467371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.4245467371
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.3981263622
Short name T286
Test name
Test status
Simulation time 17160753 ps
CPU time 0.55 seconds
Started Jul 14 05:19:58 PM PDT 24
Finished Jul 14 05:19:59 PM PDT 24
Peak memory 194604 kb
Host smart-74e1e4d8-c1b8-410a-876d-ab8f8054f774
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981263622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.3981263622
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2936425996
Short name T498
Test name
Test status
Simulation time 35787713 ps
CPU time 0.95 seconds
Started Jul 14 05:19:52 PM PDT 24
Finished Jul 14 05:19:54 PM PDT 24
Peak memory 196820 kb
Host smart-97b4000b-d34d-47d3-853a-2059ef3ab716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936425996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2936425996
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2454105186
Short name T423
Test name
Test status
Simulation time 162278320 ps
CPU time 6.32 seconds
Started Jul 14 05:19:54 PM PDT 24
Finished Jul 14 05:20:01 PM PDT 24
Peak memory 197492 kb
Host smart-3d93e254-315d-4619-b695-48f1be15c422
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454105186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2454105186
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.4082055926
Short name T121
Test name
Test status
Simulation time 233461397 ps
CPU time 1.05 seconds
Started Jul 14 05:20:00 PM PDT 24
Finished Jul 14 05:20:02 PM PDT 24
Peak memory 198392 kb
Host smart-718cecee-15ea-4701-a77d-ee304256de39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082055926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.4082055926
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.1478629535
Short name T467
Test name
Test status
Simulation time 153436556 ps
CPU time 1.21 seconds
Started Jul 14 05:19:53 PM PDT 24
Finished Jul 14 05:19:55 PM PDT 24
Peak memory 196500 kb
Host smart-de3e39f5-e8ad-4549-b136-e2e16b16e783
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478629535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.1478629535
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.3499549267
Short name T519
Test name
Test status
Simulation time 403953810 ps
CPU time 3.71 seconds
Started Jul 14 05:19:56 PM PDT 24
Finished Jul 14 05:20:00 PM PDT 24
Peak memory 198600 kb
Host smart-d07baae3-49e3-4a42-a996-7dd21f9fcbfe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499549267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.3499549267
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1933486799
Short name T126
Test name
Test status
Simulation time 106672560 ps
CPU time 2.58 seconds
Started Jul 14 05:19:53 PM PDT 24
Finished Jul 14 05:19:56 PM PDT 24
Peak memory 196760 kb
Host smart-b39311a9-4d6c-4283-a30c-780bc11f542f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933486799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1933486799
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1311873907
Short name T254
Test name
Test status
Simulation time 19586384 ps
CPU time 0.68 seconds
Started Jul 14 05:19:56 PM PDT 24
Finished Jul 14 05:19:57 PM PDT 24
Peak memory 195484 kb
Host smart-b48576bf-1821-4ba5-bb47-b0127b90e42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311873907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1311873907
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2053152608
Short name T311
Test name
Test status
Simulation time 21266715 ps
CPU time 0.87 seconds
Started Jul 14 05:19:54 PM PDT 24
Finished Jul 14 05:19:55 PM PDT 24
Peak memory 196340 kb
Host smart-43c807d2-fad4-4ea5-9c0d-1951ed5104e0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053152608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2053152608
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1638749531
Short name T137
Test name
Test status
Simulation time 170695917 ps
CPU time 4.73 seconds
Started Jul 14 05:19:55 PM PDT 24
Finished Jul 14 05:20:00 PM PDT 24
Peak memory 198528 kb
Host smart-61ce5691-f58d-423c-a45a-aae59b4cc181
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638749531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1638749531
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.1054625925
Short name T178
Test name
Test status
Simulation time 34892219 ps
CPU time 1.21 seconds
Started Jul 14 05:19:54 PM PDT 24
Finished Jul 14 05:19:56 PM PDT 24
Peak memory 197040 kb
Host smart-74207fb8-d659-4cba-9fd6-b147c1583099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054625925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1054625925
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.238605259
Short name T413
Test name
Test status
Simulation time 84855423 ps
CPU time 0.74 seconds
Started Jul 14 05:19:55 PM PDT 24
Finished Jul 14 05:19:56 PM PDT 24
Peak memory 195876 kb
Host smart-79d70d6f-d633-4477-8858-2ba1ff4185ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238605259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.238605259
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.29861113
Short name T517
Test name
Test status
Simulation time 12415689627 ps
CPU time 135.93 seconds
Started Jul 14 05:20:00 PM PDT 24
Finished Jul 14 05:22:16 PM PDT 24
Peak memory 198632 kb
Host smart-66298a7b-48f4-4476-b3d5-44b598f02f05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29861113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gp
io_stress_all.29861113
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.1846707328
Short name T475
Test name
Test status
Simulation time 307247071886 ps
CPU time 1320.77 seconds
Started Jul 14 05:19:59 PM PDT 24
Finished Jul 14 05:42:00 PM PDT 24
Peak memory 198828 kb
Host smart-f741e9d9-6992-4f49-9008-ca1e2c3029ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1846707328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.1846707328
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3362242450
Short name T709
Test name
Test status
Simulation time 118922137 ps
CPU time 0.56 seconds
Started Jul 14 05:20:11 PM PDT 24
Finished Jul 14 05:20:12 PM PDT 24
Peak memory 194808 kb
Host smart-555ffb2e-e198-4817-ae88-d4f6fb4b322b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362242450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3362242450
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.3698831686
Short name T682
Test name
Test status
Simulation time 37813350 ps
CPU time 0.78 seconds
Started Jul 14 05:20:00 PM PDT 24
Finished Jul 14 05:20:01 PM PDT 24
Peak memory 195752 kb
Host smart-bb77e33f-7f04-4e56-b4ac-347de3eef168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698831686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.3698831686
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3504716056
Short name T533
Test name
Test status
Simulation time 335813296 ps
CPU time 18.01 seconds
Started Jul 14 05:20:00 PM PDT 24
Finished Jul 14 05:20:19 PM PDT 24
Peak memory 196808 kb
Host smart-63bee11d-7ac9-40a3-8c3e-c23847a1bb8f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504716056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3504716056
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3058669350
Short name T339
Test name
Test status
Simulation time 78558141 ps
CPU time 0.71 seconds
Started Jul 14 05:20:08 PM PDT 24
Finished Jul 14 05:20:10 PM PDT 24
Peak memory 195252 kb
Host smart-4c2f9119-af45-4594-87b9-d6af63153504
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058669350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3058669350
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3515913178
Short name T260
Test name
Test status
Simulation time 23858285 ps
CPU time 0.91 seconds
Started Jul 14 05:20:01 PM PDT 24
Finished Jul 14 05:20:02 PM PDT 24
Peak memory 196052 kb
Host smart-047aa715-98e8-4337-9a1f-209edaaa167c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515913178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3515913178
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3795142751
Short name T303
Test name
Test status
Simulation time 228001685 ps
CPU time 1.71 seconds
Started Jul 14 05:19:59 PM PDT 24
Finished Jul 14 05:20:02 PM PDT 24
Peak memory 198596 kb
Host smart-3d016d1c-f1de-4899-b80e-ce86fda64745
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795142751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3795142751
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.829257584
Short name T360
Test name
Test status
Simulation time 87925701 ps
CPU time 1.03 seconds
Started Jul 14 05:19:59 PM PDT 24
Finished Jul 14 05:20:01 PM PDT 24
Peak memory 196024 kb
Host smart-76598f7d-ccac-46c8-8e70-143771fffa31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829257584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
829257584
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.1394399502
Short name T304
Test name
Test status
Simulation time 140097227 ps
CPU time 1.22 seconds
Started Jul 14 05:19:59 PM PDT 24
Finished Jul 14 05:20:01 PM PDT 24
Peak memory 196456 kb
Host smart-3bcc4f84-64b5-41f1-a8f4-cae1e79451eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394399502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1394399502
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3879648265
Short name T380
Test name
Test status
Simulation time 64263817 ps
CPU time 1.24 seconds
Started Jul 14 05:20:00 PM PDT 24
Finished Jul 14 05:20:02 PM PDT 24
Peak memory 197692 kb
Host smart-5f8146e1-7c1d-44c6-8d4a-3451db8126d2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879648265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3879648265
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.332086022
Short name T138
Test name
Test status
Simulation time 80266704 ps
CPU time 3.51 seconds
Started Jul 14 05:20:12 PM PDT 24
Finished Jul 14 05:20:16 PM PDT 24
Peak memory 198600 kb
Host smart-f0e648a1-30b8-41d0-afe9-f8203866006c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332086022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.332086022
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.2389850878
Short name T459
Test name
Test status
Simulation time 267462001 ps
CPU time 1.2 seconds
Started Jul 14 05:20:03 PM PDT 24
Finished Jul 14 05:20:05 PM PDT 24
Peak memory 196464 kb
Host smart-650f3e35-cdc6-4106-aadc-220b71534bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389850878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.2389850878
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.563310561
Short name T599
Test name
Test status
Simulation time 138597230 ps
CPU time 1.06 seconds
Started Jul 14 05:19:58 PM PDT 24
Finished Jul 14 05:20:00 PM PDT 24
Peak memory 196472 kb
Host smart-9d9c4291-035a-4bab-9a37-5459c8ca11b8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563310561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.563310561
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.653339743
Short name T294
Test name
Test status
Simulation time 43516118843 ps
CPU time 92.33 seconds
Started Jul 14 05:20:10 PM PDT 24
Finished Jul 14 05:21:43 PM PDT 24
Peak memory 198800 kb
Host smart-af7bce26-4f2c-449c-a96a-c360f141b772
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653339743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.653339743
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.3501817723
Short name T482
Test name
Test status
Simulation time 12994058 ps
CPU time 0.58 seconds
Started Jul 14 05:20:14 PM PDT 24
Finished Jul 14 05:20:15 PM PDT 24
Peak memory 194516 kb
Host smart-febd54dc-af0c-46d5-b9b3-b0effcdb79c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501817723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3501817723
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.289481542
Short name T263
Test name
Test status
Simulation time 22336887 ps
CPU time 0.67 seconds
Started Jul 14 05:20:10 PM PDT 24
Finished Jul 14 05:20:12 PM PDT 24
Peak memory 194736 kb
Host smart-ef7794cb-d7c4-4f82-8d37-76c83f0362fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289481542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.289481542
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.65511768
Short name T273
Test name
Test status
Simulation time 518348783 ps
CPU time 26.69 seconds
Started Jul 14 05:20:09 PM PDT 24
Finished Jul 14 05:20:36 PM PDT 24
Peak memory 197180 kb
Host smart-eddcaa51-4a3e-4b6a-80b4-4c692d8c369d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65511768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stress
.65511768
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3465724924
Short name T326
Test name
Test status
Simulation time 323258884 ps
CPU time 0.97 seconds
Started Jul 14 05:20:10 PM PDT 24
Finished Jul 14 05:20:12 PM PDT 24
Peak memory 198388 kb
Host smart-b309bd89-932d-4580-9edf-dddbabd42d7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465724924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3465724924
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.4118698619
Short name T581
Test name
Test status
Simulation time 98507256 ps
CPU time 1.39 seconds
Started Jul 14 05:20:10 PM PDT 24
Finished Jul 14 05:20:11 PM PDT 24
Peak memory 197904 kb
Host smart-a1c5317b-7df3-469c-8ae3-5ca1e1ea9bd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118698619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.4118698619
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3548800246
Short name T501
Test name
Test status
Simulation time 352624598 ps
CPU time 3.71 seconds
Started Jul 14 05:20:09 PM PDT 24
Finished Jul 14 05:20:13 PM PDT 24
Peak memory 198580 kb
Host smart-2d240edc-f2d0-4670-8c30-2ca731e183dc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548800246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3548800246
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.619259422
Short name T362
Test name
Test status
Simulation time 68602857 ps
CPU time 1.29 seconds
Started Jul 14 05:20:08 PM PDT 24
Finished Jul 14 05:20:10 PM PDT 24
Peak memory 197180 kb
Host smart-f41177ce-494c-4524-8144-beaf0cd5062e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619259422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
619259422
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2197961279
Short name T556
Test name
Test status
Simulation time 86512421 ps
CPU time 0.77 seconds
Started Jul 14 05:20:10 PM PDT 24
Finished Jul 14 05:20:11 PM PDT 24
Peak memory 196668 kb
Host smart-4517c9b5-e780-4205-b91e-b64fe8141e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197961279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2197961279
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3083708153
Short name T708
Test name
Test status
Simulation time 86268000 ps
CPU time 1.03 seconds
Started Jul 14 05:20:08 PM PDT 24
Finished Jul 14 05:20:10 PM PDT 24
Peak memory 197304 kb
Host smart-eb09d920-4b13-45d2-8e5c-99efab97f945
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083708153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3083708153
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1237459192
Short name T275
Test name
Test status
Simulation time 288318772 ps
CPU time 2.55 seconds
Started Jul 14 05:20:12 PM PDT 24
Finished Jul 14 05:20:15 PM PDT 24
Peak memory 198496 kb
Host smart-5067a36b-a360-41f3-baba-18d6876ceaa4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237459192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1237459192
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.878351978
Short name T67
Test name
Test status
Simulation time 86988989 ps
CPU time 0.88 seconds
Started Jul 14 05:20:07 PM PDT 24
Finished Jul 14 05:20:08 PM PDT 24
Peak memory 196944 kb
Host smart-62a181d0-01b2-4f57-a37d-b09d818c4e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878351978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.878351978
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3977425127
Short name T658
Test name
Test status
Simulation time 73726234 ps
CPU time 0.78 seconds
Started Jul 14 05:20:08 PM PDT 24
Finished Jul 14 05:20:09 PM PDT 24
Peak memory 195780 kb
Host smart-4488dab0-aedb-45d3-9ebb-47dc16abb224
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977425127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3977425127
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.1194360400
Short name T242
Test name
Test status
Simulation time 47137172820 ps
CPU time 220.41 seconds
Started Jul 14 05:20:11 PM PDT 24
Finished Jul 14 05:23:52 PM PDT 24
Peak memory 198588 kb
Host smart-440f1e62-66c3-4a1e-b1d3-5b6b4dc8ed79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194360400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.1194360400
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2832713426
Short name T404
Test name
Test status
Simulation time 24367099 ps
CPU time 0.57 seconds
Started Jul 14 05:20:16 PM PDT 24
Finished Jul 14 05:20:17 PM PDT 24
Peak memory 194648 kb
Host smart-48bde9b8-9d75-48d5-a79e-75d31e1be691
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832713426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2832713426
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.2988155768
Short name T712
Test name
Test status
Simulation time 14800789 ps
CPU time 0.68 seconds
Started Jul 14 05:20:18 PM PDT 24
Finished Jul 14 05:20:19 PM PDT 24
Peak memory 194672 kb
Host smart-a6d26053-0bbe-4bdf-9aad-18b2e13c1025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988155768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.2988155768
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3070549289
Short name T182
Test name
Test status
Simulation time 1262572160 ps
CPU time 8.29 seconds
Started Jul 14 05:20:16 PM PDT 24
Finished Jul 14 05:20:24 PM PDT 24
Peak memory 197452 kb
Host smart-c977cb0a-96ab-4e18-ab0f-528a6479d474
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070549289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3070549289
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1839827212
Short name T429
Test name
Test status
Simulation time 62530549 ps
CPU time 1.15 seconds
Started Jul 14 05:20:16 PM PDT 24
Finished Jul 14 05:20:17 PM PDT 24
Peak memory 198696 kb
Host smart-509df9c6-ae58-421f-83b6-1d7b308590bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839827212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1839827212
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.4122845622
Short name T702
Test name
Test status
Simulation time 71802154 ps
CPU time 1.19 seconds
Started Jul 14 05:20:15 PM PDT 24
Finished Jul 14 05:20:17 PM PDT 24
Peak memory 197060 kb
Host smart-f4800d21-e2bd-40f6-a3a0-d605667b52c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122845622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.4122845622
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1577377645
Short name T486
Test name
Test status
Simulation time 67631508 ps
CPU time 0.98 seconds
Started Jul 14 05:20:21 PM PDT 24
Finished Jul 14 05:20:23 PM PDT 24
Peak memory 196692 kb
Host smart-61d81bd4-1050-44e3-babd-daeadd29328d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577377645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1577377645
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.2814839461
Short name T535
Test name
Test status
Simulation time 145974362 ps
CPU time 2.8 seconds
Started Jul 14 05:20:14 PM PDT 24
Finished Jul 14 05:20:18 PM PDT 24
Peak memory 198580 kb
Host smart-48ad3ace-5822-45a0-a2ad-722a7264f988
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814839461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.2814839461
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.246811054
Short name T146
Test name
Test status
Simulation time 43209616 ps
CPU time 0.7 seconds
Started Jul 14 05:20:16 PM PDT 24
Finished Jul 14 05:20:18 PM PDT 24
Peak memory 195980 kb
Host smart-8f20a250-14e5-4499-8582-272dd4c2ffe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246811054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.246811054
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.848430596
Short name T160
Test name
Test status
Simulation time 32098332 ps
CPU time 0.64 seconds
Started Jul 14 05:20:19 PM PDT 24
Finished Jul 14 05:20:20 PM PDT 24
Peak memory 194848 kb
Host smart-94788ad2-bd6d-4e23-9c2b-b3dbb8c5feef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848430596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.848430596
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.603879944
Short name T610
Test name
Test status
Simulation time 617797837 ps
CPU time 2.46 seconds
Started Jul 14 05:20:19 PM PDT 24
Finished Jul 14 05:20:22 PM PDT 24
Peak memory 198632 kb
Host smart-95b6079d-a6c5-43cc-b7ac-80980e2bb266
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603879944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.603879944
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2828800952
Short name T550
Test name
Test status
Simulation time 38728539 ps
CPU time 1.25 seconds
Started Jul 14 05:20:15 PM PDT 24
Finished Jul 14 05:20:17 PM PDT 24
Peak memory 197168 kb
Host smart-4a1d1066-c1d1-437e-a18d-62ed55d1b339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828800952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2828800952
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3204696568
Short name T534
Test name
Test status
Simulation time 323065185 ps
CPU time 1.5 seconds
Started Jul 14 05:20:16 PM PDT 24
Finished Jul 14 05:20:19 PM PDT 24
Peak memory 198516 kb
Host smart-24a7206b-c774-44f9-93af-610590540ac6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204696568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3204696568
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.1985975936
Short name T358
Test name
Test status
Simulation time 75778416244 ps
CPU time 237.3 seconds
Started Jul 14 05:20:16 PM PDT 24
Finished Jul 14 05:24:14 PM PDT 24
Peak memory 198668 kb
Host smart-90eb5cbc-9532-4104-a745-7514711e7552
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985975936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.1985975936
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.3276842807
Short name T55
Test name
Test status
Simulation time 466759946385 ps
CPU time 1401.15 seconds
Started Jul 14 05:20:18 PM PDT 24
Finished Jul 14 05:43:40 PM PDT 24
Peak memory 198868 kb
Host smart-b7f54b89-4258-404d-8a9e-0f32e4aa9202
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3276842807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.3276842807
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3934435495
Short name T335
Test name
Test status
Simulation time 47473489 ps
CPU time 0.58 seconds
Started Jul 14 05:20:26 PM PDT 24
Finished Jul 14 05:20:27 PM PDT 24
Peak memory 194792 kb
Host smart-6bce4854-8bad-4d13-8496-1cb0ac7a4084
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934435495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3934435495
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.533149466
Short name T257
Test name
Test status
Simulation time 42828385 ps
CPU time 0.82 seconds
Started Jul 14 05:20:17 PM PDT 24
Finished Jul 14 05:20:18 PM PDT 24
Peak memory 195752 kb
Host smart-eb8ef0f8-cf74-475e-bd77-fa31f76bde31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533149466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.533149466
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3119982486
Short name T400
Test name
Test status
Simulation time 829815514 ps
CPU time 24.81 seconds
Started Jul 14 05:20:36 PM PDT 24
Finished Jul 14 05:21:01 PM PDT 24
Peak memory 198556 kb
Host smart-9a284325-e825-4029-8aad-6e00537b1c0a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119982486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3119982486
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.4270869018
Short name T271
Test name
Test status
Simulation time 53338893 ps
CPU time 0.95 seconds
Started Jul 14 05:20:26 PM PDT 24
Finished Jul 14 05:20:27 PM PDT 24
Peak memory 197788 kb
Host smart-4e16bef1-b24b-44c0-939b-65aef7f8feb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270869018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.4270869018
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3007342664
Short name T407
Test name
Test status
Simulation time 24970983 ps
CPU time 0.85 seconds
Started Jul 14 05:20:17 PM PDT 24
Finished Jul 14 05:20:18 PM PDT 24
Peak memory 196928 kb
Host smart-00b05f75-8723-4c0b-9f8c-9c2aede4502b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007342664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3007342664
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.951185295
Short name T107
Test name
Test status
Simulation time 200125281 ps
CPU time 2.15 seconds
Started Jul 14 05:20:19 PM PDT 24
Finished Jul 14 05:20:21 PM PDT 24
Peak memory 198612 kb
Host smart-74aa86e0-7559-47ec-a56b-c732ef053ed2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951185295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.951185295
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.2359291457
Short name T246
Test name
Test status
Simulation time 243617140 ps
CPU time 4.17 seconds
Started Jul 14 05:20:16 PM PDT 24
Finished Jul 14 05:20:21 PM PDT 24
Peak memory 197452 kb
Host smart-8d83128a-ceb4-4e76-8694-f8d28c4b281e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359291457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.2359291457
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.2267779311
Short name T391
Test name
Test status
Simulation time 52870946 ps
CPU time 1 seconds
Started Jul 14 05:20:19 PM PDT 24
Finished Jul 14 05:20:20 PM PDT 24
Peak memory 196580 kb
Host smart-cda8c6e8-8b5b-4e9e-a5dc-996629f251f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267779311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.2267779311
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.1109315208
Short name T125
Test name
Test status
Simulation time 33302750 ps
CPU time 0.76 seconds
Started Jul 14 05:20:17 PM PDT 24
Finished Jul 14 05:20:18 PM PDT 24
Peak memory 195916 kb
Host smart-b67688e7-8455-4d30-87a9-142dcb438674
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109315208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.1109315208
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1342782600
Short name T394
Test name
Test status
Simulation time 110066568 ps
CPU time 5.4 seconds
Started Jul 14 05:20:24 PM PDT 24
Finished Jul 14 05:20:30 PM PDT 24
Peak memory 198460 kb
Host smart-5ff4b5bb-0274-45b7-a73b-24dd2604712d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342782600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1342782600
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.499255769
Short name T662
Test name
Test status
Simulation time 60457672 ps
CPU time 1.12 seconds
Started Jul 14 05:20:17 PM PDT 24
Finished Jul 14 05:20:19 PM PDT 24
Peak memory 196328 kb
Host smart-757dbb3f-1514-4ca8-88a7-fdf87c9ebe02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499255769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.499255769
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3472311034
Short name T252
Test name
Test status
Simulation time 980862331 ps
CPU time 1.32 seconds
Started Jul 14 05:20:17 PM PDT 24
Finished Jul 14 05:20:19 PM PDT 24
Peak memory 197088 kb
Host smart-0c63f61c-c608-41ac-a7f2-4d03a67299ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472311034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3472311034
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2585440717
Short name T7
Test name
Test status
Simulation time 82367107361 ps
CPU time 160.57 seconds
Started Jul 14 05:20:29 PM PDT 24
Finished Jul 14 05:23:10 PM PDT 24
Peak memory 198744 kb
Host smart-314ede6e-abea-41c6-80f3-eef019cb768d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585440717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2585440717
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.821516549
Short name T58
Test name
Test status
Simulation time 144985267211 ps
CPU time 922.89 seconds
Started Jul 14 05:20:25 PM PDT 24
Finished Jul 14 05:35:48 PM PDT 24
Peak memory 198876 kb
Host smart-ee0e78e6-6cdb-44c1-9023-d5c90f860ed8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=821516549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.821516549
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2248690566
Short name T320
Test name
Test status
Simulation time 18404498 ps
CPU time 0.58 seconds
Started Jul 14 05:20:36 PM PDT 24
Finished Jul 14 05:20:37 PM PDT 24
Peak memory 195348 kb
Host smart-f5532757-2e48-43c9-9128-7a49e7980813
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248690566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2248690566
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.463506133
Short name T684
Test name
Test status
Simulation time 149311037 ps
CPU time 0.68 seconds
Started Jul 14 05:20:28 PM PDT 24
Finished Jul 14 05:20:29 PM PDT 24
Peak memory 194648 kb
Host smart-b8844611-4aa1-4567-a06f-4a55ebd3fadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463506133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.463506133
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2786634715
Short name T214
Test name
Test status
Simulation time 2471441758 ps
CPU time 20.32 seconds
Started Jul 14 05:20:24 PM PDT 24
Finished Jul 14 05:20:45 PM PDT 24
Peak memory 197468 kb
Host smart-778d12fc-2115-462b-83e5-70a631d05a53
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786634715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2786634715
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.3609435151
Short name T338
Test name
Test status
Simulation time 62757689 ps
CPU time 0.99 seconds
Started Jul 14 05:20:26 PM PDT 24
Finished Jul 14 05:20:27 PM PDT 24
Peak memory 197144 kb
Host smart-cd7ffba4-9af7-4d67-961a-12c2b400ce64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609435151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.3609435151
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3460880844
Short name T344
Test name
Test status
Simulation time 65464812 ps
CPU time 1.36 seconds
Started Jul 14 05:20:36 PM PDT 24
Finished Jul 14 05:20:38 PM PDT 24
Peak memory 196596 kb
Host smart-697a0dc0-b617-422c-be16-47537161b3e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460880844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3460880844
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3687286101
Short name T348
Test name
Test status
Simulation time 69631872 ps
CPU time 2.66 seconds
Started Jul 14 05:20:24 PM PDT 24
Finished Jul 14 05:20:28 PM PDT 24
Peak memory 197104 kb
Host smart-80616150-a5c7-4379-a380-21c4a52b90e2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687286101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3687286101
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.4203518103
Short name T571
Test name
Test status
Simulation time 160760721 ps
CPU time 3.08 seconds
Started Jul 14 05:20:27 PM PDT 24
Finished Jul 14 05:20:30 PM PDT 24
Peak memory 197844 kb
Host smart-b912203a-6377-4743-8725-936c892e9a0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203518103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.4203518103
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.4180099673
Short name T495
Test name
Test status
Simulation time 125144005 ps
CPU time 1.15 seconds
Started Jul 14 05:20:26 PM PDT 24
Finished Jul 14 05:20:28 PM PDT 24
Peak memory 196360 kb
Host smart-aa0b3842-8484-4993-9f0e-547f51cea46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180099673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.4180099673
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.832510386
Short name T211
Test name
Test status
Simulation time 136088236 ps
CPU time 0.76 seconds
Started Jul 14 05:20:25 PM PDT 24
Finished Jul 14 05:20:26 PM PDT 24
Peak memory 195844 kb
Host smart-f96af68e-ff0f-42fd-b98e-1508273c0a53
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832510386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.832510386
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.551938049
Short name T418
Test name
Test status
Simulation time 544343867 ps
CPU time 6.57 seconds
Started Jul 14 05:20:26 PM PDT 24
Finished Jul 14 05:20:33 PM PDT 24
Peak memory 198556 kb
Host smart-466668d4-0ac2-487d-9c07-d58726c4b169
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551938049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ran
dom_long_reg_writes_reg_reads.551938049
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.3934242074
Short name T598
Test name
Test status
Simulation time 58251856 ps
CPU time 1.28 seconds
Started Jul 14 05:20:23 PM PDT 24
Finished Jul 14 05:20:25 PM PDT 24
Peak memory 196328 kb
Host smart-dd6dea54-365e-48b7-bf82-686032796a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934242074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.3934242074
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2075412068
Short name T532
Test name
Test status
Simulation time 49984291 ps
CPU time 0.89 seconds
Started Jul 14 05:20:29 PM PDT 24
Finished Jul 14 05:20:30 PM PDT 24
Peak memory 195828 kb
Host smart-317e32b7-2804-4c20-8239-288917cbb9c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075412068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2075412068
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.4256704177
Short name T152
Test name
Test status
Simulation time 6651397161 ps
CPU time 93.01 seconds
Started Jul 14 05:20:37 PM PDT 24
Finished Jul 14 05:22:10 PM PDT 24
Peak memory 198796 kb
Host smart-8f4648e1-046f-4d6f-8d9f-6763ae70d2ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256704177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.4256704177
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.2553341938
Short name T711
Test name
Test status
Simulation time 26161770 ps
CPU time 0.59 seconds
Started Jul 14 05:20:36 PM PDT 24
Finished Jul 14 05:20:37 PM PDT 24
Peak memory 194728 kb
Host smart-4822671b-e9c9-4a72-956e-37c870c4041b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553341938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.2553341938
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1865715468
Short name T251
Test name
Test status
Simulation time 29079792 ps
CPU time 0.78 seconds
Started Jul 14 05:20:34 PM PDT 24
Finished Jul 14 05:20:35 PM PDT 24
Peak memory 195880 kb
Host smart-cf787b8f-73ce-4c02-a94c-a47a8d6c8dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865715468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1865715468
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.288606591
Short name T399
Test name
Test status
Simulation time 1609128527 ps
CPU time 18.47 seconds
Started Jul 14 05:20:41 PM PDT 24
Finished Jul 14 05:21:00 PM PDT 24
Peak memory 198628 kb
Host smart-4ecd4ea3-dd6c-49ce-9853-5c8ea67d1153
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288606591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stres
s.288606591
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1731260499
Short name T368
Test name
Test status
Simulation time 20459511 ps
CPU time 0.66 seconds
Started Jul 14 05:20:35 PM PDT 24
Finished Jul 14 05:20:36 PM PDT 24
Peak memory 195092 kb
Host smart-5e01d9f7-e3fe-4cc4-9aa8-acd7cc412995
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731260499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1731260499
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1242827742
Short name T590
Test name
Test status
Simulation time 171896619 ps
CPU time 0.97 seconds
Started Jul 14 05:20:39 PM PDT 24
Finished Jul 14 05:20:40 PM PDT 24
Peak memory 197384 kb
Host smart-288e3b82-2a47-44e1-ab61-17fcba0e48eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242827742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1242827742
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.4240517834
Short name T183
Test name
Test status
Simulation time 89404924 ps
CPU time 1.99 seconds
Started Jul 14 05:20:36 PM PDT 24
Finished Jul 14 05:20:39 PM PDT 24
Peak memory 198632 kb
Host smart-77801035-f47c-4879-89f2-5ae3e6d4bf43
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240517834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.4240517834
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2242952126
Short name T171
Test name
Test status
Simulation time 97842207 ps
CPU time 3.32 seconds
Started Jul 14 05:20:34 PM PDT 24
Finished Jul 14 05:20:37 PM PDT 24
Peak memory 198080 kb
Host smart-b25a1bcc-6776-43e0-8c7b-0d9ba6cd9089
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242952126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2242952126
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.500596531
Short name T483
Test name
Test status
Simulation time 76897839 ps
CPU time 0.94 seconds
Started Jul 14 05:20:41 PM PDT 24
Finished Jul 14 05:20:43 PM PDT 24
Peak memory 196496 kb
Host smart-d0959c05-34af-4fb2-9a8f-ef448891772f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500596531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.500596531
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3890384873
Short name T425
Test name
Test status
Simulation time 55749872 ps
CPU time 1.19 seconds
Started Jul 14 05:20:36 PM PDT 24
Finished Jul 14 05:20:38 PM PDT 24
Peak memory 196384 kb
Host smart-93319875-75da-4885-a289-ea52e2bf95f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890384873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3890384873
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1475536808
Short name T164
Test name
Test status
Simulation time 81055774 ps
CPU time 3.81 seconds
Started Jul 14 05:20:36 PM PDT 24
Finished Jul 14 05:20:40 PM PDT 24
Peak memory 198432 kb
Host smart-44197253-350d-4ef9-ab62-bef2066edf64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475536808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1475536808
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.3373850541
Short name T345
Test name
Test status
Simulation time 36319733 ps
CPU time 1.1 seconds
Started Jul 14 05:20:42 PM PDT 24
Finished Jul 14 05:20:44 PM PDT 24
Peak memory 196192 kb
Host smart-64be48fa-15dd-4516-a57a-0503062533b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373850541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.3373850541
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3054301606
Short name T216
Test name
Test status
Simulation time 148317759 ps
CPU time 1.22 seconds
Started Jul 14 05:20:41 PM PDT 24
Finished Jul 14 05:20:43 PM PDT 24
Peak memory 196416 kb
Host smart-148438aa-e21c-450f-9621-abe8f6c1ceb5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054301606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.3054301606
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3746626510
Short name T458
Test name
Test status
Simulation time 127206699157 ps
CPU time 191.09 seconds
Started Jul 14 05:20:35 PM PDT 24
Finished Jul 14 05:23:47 PM PDT 24
Peak memory 198624 kb
Host smart-3d1c0299-9e99-4768-aa18-e1eeb2dd7294
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746626510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3746626510
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.3403351626
Short name T507
Test name
Test status
Simulation time 105914162355 ps
CPU time 511.62 seconds
Started Jul 14 05:20:36 PM PDT 24
Finished Jul 14 05:29:09 PM PDT 24
Peak memory 198888 kb
Host smart-dd54101f-fbc6-46c7-8946-ca87b0c4cf6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3403351626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.3403351626
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1437942833
Short name T156
Test name
Test status
Simulation time 39048069 ps
CPU time 0.58 seconds
Started Jul 14 05:20:45 PM PDT 24
Finished Jul 14 05:20:46 PM PDT 24
Peak memory 194496 kb
Host smart-dd4605ac-26e0-47f2-ae53-9f552cd63410
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437942833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1437942833
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3914528957
Short name T11
Test name
Test status
Simulation time 32481737 ps
CPU time 0.66 seconds
Started Jul 14 05:20:43 PM PDT 24
Finished Jul 14 05:20:44 PM PDT 24
Peak memory 195252 kb
Host smart-35f58c1f-75dd-4ff1-ad82-659be0ae6258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914528957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3914528957
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1192853779
Short name T432
Test name
Test status
Simulation time 1136502219 ps
CPU time 15.22 seconds
Started Jul 14 05:20:45 PM PDT 24
Finished Jul 14 05:21:01 PM PDT 24
Peak memory 197340 kb
Host smart-72865c37-0dad-472b-aef7-9920391d3f39
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192853779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1192853779
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.1330761083
Short name T544
Test name
Test status
Simulation time 60599061 ps
CPU time 0.9 seconds
Started Jul 14 05:20:42 PM PDT 24
Finished Jul 14 05:20:43 PM PDT 24
Peak memory 196636 kb
Host smart-6aab91f3-85e1-43d9-b2ce-541526e5fb5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330761083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.1330761083
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.4053037794
Short name T21
Test name
Test status
Simulation time 123349607 ps
CPU time 1.36 seconds
Started Jul 14 05:20:42 PM PDT 24
Finished Jul 14 05:20:44 PM PDT 24
Peak memory 197288 kb
Host smart-f45a588b-0e20-4303-8eca-e36d0ecab6d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053037794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.4053037794
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1759927648
Short name T582
Test name
Test status
Simulation time 142995032 ps
CPU time 3.11 seconds
Started Jul 14 05:20:40 PM PDT 24
Finished Jul 14 05:20:44 PM PDT 24
Peak memory 198600 kb
Host smart-dd6ae9ee-45c7-412b-be2f-95522cc84d1d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759927648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1759927648
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.810572263
Short name T565
Test name
Test status
Simulation time 46286330 ps
CPU time 1.31 seconds
Started Jul 14 05:20:42 PM PDT 24
Finished Jul 14 05:20:44 PM PDT 24
Peak memory 196348 kb
Host smart-0ba54f44-f9e3-48d8-99d6-473a521fd54d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810572263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
810572263
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3786438277
Short name T646
Test name
Test status
Simulation time 38226322 ps
CPU time 1.2 seconds
Started Jul 14 05:20:35 PM PDT 24
Finished Jul 14 05:20:37 PM PDT 24
Peak memory 196704 kb
Host smart-6ad9f30d-6486-4d47-abcb-882f58c48a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786438277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3786438277
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.726109633
Short name T261
Test name
Test status
Simulation time 36667063 ps
CPU time 1.25 seconds
Started Jul 14 05:20:42 PM PDT 24
Finished Jul 14 05:20:44 PM PDT 24
Peak memory 196484 kb
Host smart-c28764dd-ef9b-49d2-9da4-e317c4a083bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726109633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.726109633
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.1975216509
Short name T395
Test name
Test status
Simulation time 26393973 ps
CPU time 1.13 seconds
Started Jul 14 05:20:46 PM PDT 24
Finished Jul 14 05:20:47 PM PDT 24
Peak memory 198472 kb
Host smart-0c504a99-dbef-4d90-b0d1-6eab05f7e773
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975216509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.1975216509
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.1645545596
Short name T701
Test name
Test status
Simulation time 123450735 ps
CPU time 1.04 seconds
Started Jul 14 05:20:35 PM PDT 24
Finished Jul 14 05:20:37 PM PDT 24
Peak memory 196124 kb
Host smart-73740f80-9cd3-400d-a6b2-cfaa7145ccf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645545596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.1645545596
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.1851210410
Short name T331
Test name
Test status
Simulation time 152682056 ps
CPU time 1.37 seconds
Started Jul 14 05:20:37 PM PDT 24
Finished Jul 14 05:20:39 PM PDT 24
Peak memory 197568 kb
Host smart-5ef3546b-802c-48d2-b793-e3fd61369b80
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851210410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.1851210410
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2400339893
Short name T588
Test name
Test status
Simulation time 5550264720 ps
CPU time 144 seconds
Started Jul 14 05:20:40 PM PDT 24
Finished Jul 14 05:23:05 PM PDT 24
Peak memory 198640 kb
Host smart-be69827b-8b7a-4abf-ab25-607e75712d64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400339893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2400339893
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.1441403516
Short name T54
Test name
Test status
Simulation time 18211758491 ps
CPU time 260.52 seconds
Started Jul 14 05:20:53 PM PDT 24
Finished Jul 14 05:25:15 PM PDT 24
Peak memory 198840 kb
Host smart-f0d006c3-12e4-4e3a-855a-038015dd1369
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1441403516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.1441403516
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.4012727318
Short name T479
Test name
Test status
Simulation time 13145042 ps
CPU time 0.59 seconds
Started Jul 14 05:20:51 PM PDT 24
Finished Jul 14 05:20:52 PM PDT 24
Peak memory 194644 kb
Host smart-6706b17b-27fd-4d8a-bd28-d32ed52d10c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012727318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.4012727318
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.4216988522
Short name T649
Test name
Test status
Simulation time 75675113 ps
CPU time 0.83 seconds
Started Jul 14 05:20:43 PM PDT 24
Finished Jul 14 05:20:44 PM PDT 24
Peak memory 195948 kb
Host smart-aeab2f40-366c-45eb-a538-c4c7d5ed14c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216988522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.4216988522
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.2488841972
Short name T675
Test name
Test status
Simulation time 2808846934 ps
CPU time 24.96 seconds
Started Jul 14 05:20:49 PM PDT 24
Finished Jul 14 05:21:15 PM PDT 24
Peak memory 198708 kb
Host smart-913866f8-2b65-4496-a07c-be8cae8340b3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488841972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2488841972
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.799999298
Short name T583
Test name
Test status
Simulation time 163994166 ps
CPU time 1.02 seconds
Started Jul 14 05:20:48 PM PDT 24
Finished Jul 14 05:20:49 PM PDT 24
Peak memory 197048 kb
Host smart-6d82647c-07b7-4e6b-83ec-bc9332b33c29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799999298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.799999298
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.4266188448
Short name T690
Test name
Test status
Simulation time 84201431 ps
CPU time 1.17 seconds
Started Jul 14 05:20:54 PM PDT 24
Finished Jul 14 05:20:55 PM PDT 24
Peak memory 196384 kb
Host smart-810ff66b-2115-47cf-97a1-5da96b80978e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266188448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.4266188448
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.167850419
Short name T446
Test name
Test status
Simulation time 81236374 ps
CPU time 3.11 seconds
Started Jul 14 05:20:46 PM PDT 24
Finished Jul 14 05:20:49 PM PDT 24
Peak memory 198424 kb
Host smart-bedca0ec-657b-4d5b-b4c2-04e0d39d4ddc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167850419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.gpio_intr_with_filter_rand_intr_event.167850419
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.2066092234
Short name T115
Test name
Test status
Simulation time 1295772050 ps
CPU time 2.47 seconds
Started Jul 14 05:20:54 PM PDT 24
Finished Jul 14 05:20:57 PM PDT 24
Peak memory 198512 kb
Host smart-49bcfe8a-65e4-489d-861a-b1a3e48fb539
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066092234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.2066092234
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.2247462221
Short name T226
Test name
Test status
Simulation time 54679262 ps
CPU time 1.24 seconds
Started Jul 14 05:20:42 PM PDT 24
Finished Jul 14 05:20:43 PM PDT 24
Peak memory 198660 kb
Host smart-a92f9a30-e4bb-4f65-9c56-32f9b5d60057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247462221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.2247462221
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.2015415231
Short name T175
Test name
Test status
Simulation time 134961211 ps
CPU time 0.83 seconds
Started Jul 14 05:20:54 PM PDT 24
Finished Jul 14 05:20:55 PM PDT 24
Peak memory 196768 kb
Host smart-c1dac75a-8370-416b-8e07-1777fd69cadf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015415231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.2015415231
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2361467779
Short name T106
Test name
Test status
Simulation time 317715481 ps
CPU time 5.36 seconds
Started Jul 14 05:20:49 PM PDT 24
Finished Jul 14 05:20:55 PM PDT 24
Peak memory 198468 kb
Host smart-bf4033b6-5a48-47f8-b2d6-99299fff41c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361467779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2361467779
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.2733723674
Short name T564
Test name
Test status
Simulation time 67259603 ps
CPU time 0.79 seconds
Started Jul 14 05:20:46 PM PDT 24
Finished Jul 14 05:20:47 PM PDT 24
Peak memory 196392 kb
Host smart-cd5a18d1-5b4b-4869-9326-8ac36888ea00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733723674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2733723674
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.3566773530
Short name T49
Test name
Test status
Simulation time 221593633 ps
CPU time 1.17 seconds
Started Jul 14 05:20:54 PM PDT 24
Finished Jul 14 05:20:55 PM PDT 24
Peak memory 195912 kb
Host smart-b8cf3862-d81b-4c1c-814c-e66070f0f742
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566773530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.3566773530
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.1764550427
Short name T19
Test name
Test status
Simulation time 3329619506 ps
CPU time 47.45 seconds
Started Jul 14 05:20:47 PM PDT 24
Finished Jul 14 05:21:35 PM PDT 24
Peak memory 198680 kb
Host smart-376ab301-6ef3-4b5e-b403-d0c2285208af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764550427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.1764550427
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.2421191499
Short name T485
Test name
Test status
Simulation time 48382567568 ps
CPU time 1343.19 seconds
Started Jul 14 05:20:50 PM PDT 24
Finished Jul 14 05:43:14 PM PDT 24
Peak memory 198924 kb
Host smart-f9323ef7-166e-41b6-a922-9cdc545f1bda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2421191499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.2421191499
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.3200871403
Short name T527
Test name
Test status
Simulation time 23657536 ps
CPU time 0.58 seconds
Started Jul 14 05:17:39 PM PDT 24
Finished Jul 14 05:17:40 PM PDT 24
Peak memory 194516 kb
Host smart-b06cd23b-e302-4829-96aa-ff13c7331b15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200871403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3200871403
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.4179944739
Short name T147
Test name
Test status
Simulation time 131690588 ps
CPU time 0.83 seconds
Started Jul 14 05:17:32 PM PDT 24
Finished Jul 14 05:17:33 PM PDT 24
Peak memory 196660 kb
Host smart-aa30b7ae-64b7-4bda-8db7-08a9c0a9f61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179944739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.4179944739
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3993747589
Short name T509
Test name
Test status
Simulation time 1303092083 ps
CPU time 9.29 seconds
Started Jul 14 05:17:38 PM PDT 24
Finished Jul 14 05:17:48 PM PDT 24
Peak memory 196888 kb
Host smart-922c43fa-efb1-4f38-a094-a66ef03d9b1c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993747589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3993747589
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3362792608
Short name T354
Test name
Test status
Simulation time 77302224 ps
CPU time 0.6 seconds
Started Jul 14 05:17:36 PM PDT 24
Finished Jul 14 05:17:37 PM PDT 24
Peak memory 194964 kb
Host smart-3b5b96c8-01f5-4c38-92df-e08054b9755d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362792608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3362792608
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3045057875
Short name T363
Test name
Test status
Simulation time 235133318 ps
CPU time 1.07 seconds
Started Jul 14 05:17:28 PM PDT 24
Finished Jul 14 05:17:29 PM PDT 24
Peak memory 196628 kb
Host smart-239fb88a-4fac-41c4-90ba-f550d4965a42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045057875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3045057875
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1505996944
Short name T153
Test name
Test status
Simulation time 132194487 ps
CPU time 3.38 seconds
Started Jul 14 05:17:31 PM PDT 24
Finished Jul 14 05:17:35 PM PDT 24
Peak memory 198604 kb
Host smart-8f7f1580-9066-44f0-8261-cae539cbbe5c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505996944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1505996944
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.999790386
Short name T298
Test name
Test status
Simulation time 88943305 ps
CPU time 0.98 seconds
Started Jul 14 05:17:31 PM PDT 24
Finished Jul 14 05:17:32 PM PDT 24
Peak memory 196124 kb
Host smart-72471e47-b3e4-46b8-93ed-e54b76ff9f0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999790386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.999790386
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1164144955
Short name T142
Test name
Test status
Simulation time 408363774 ps
CPU time 1.12 seconds
Started Jul 14 05:17:30 PM PDT 24
Finished Jul 14 05:17:32 PM PDT 24
Peak memory 196356 kb
Host smart-f0113fd0-54d8-45a7-a174-25063c18bd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164144955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1164144955
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.395349191
Short name T703
Test name
Test status
Simulation time 170303355 ps
CPU time 1.53 seconds
Started Jul 14 05:17:32 PM PDT 24
Finished Jul 14 05:17:34 PM PDT 24
Peak memory 196384 kb
Host smart-0329489b-2a7b-4f52-b83d-2d39f108601a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395349191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup_
pulldown.395349191
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.4095440992
Short name T600
Test name
Test status
Simulation time 99831198 ps
CPU time 4.69 seconds
Started Jul 14 05:17:39 PM PDT 24
Finished Jul 14 05:17:44 PM PDT 24
Peak memory 198496 kb
Host smart-19440cfb-a935-4743-a6fe-dd00d6ebbe61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095440992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.4095440992
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.563769484
Short name T30
Test name
Test status
Simulation time 61083791 ps
CPU time 0.87 seconds
Started Jul 14 05:17:37 PM PDT 24
Finished Jul 14 05:17:39 PM PDT 24
Peak memory 214332 kb
Host smart-fbf53e1a-2bfb-45db-b849-6467b80ba368
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563769484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.563769484
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.76940669
Short name T621
Test name
Test status
Simulation time 240101716 ps
CPU time 1.15 seconds
Started Jul 14 05:17:32 PM PDT 24
Finished Jul 14 05:17:34 PM PDT 24
Peak memory 196324 kb
Host smart-6239454b-ef91-445a-923c-daa02725d973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76940669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.76940669
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.442988860
Short name T127
Test name
Test status
Simulation time 197249422 ps
CPU time 1.05 seconds
Started Jul 14 05:17:30 PM PDT 24
Finished Jul 14 05:17:31 PM PDT 24
Peak memory 197004 kb
Host smart-4ac24cdb-e620-4bbd-a900-93a58e211ded
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442988860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.442988860
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.3203944022
Short name T518
Test name
Test status
Simulation time 11617849172 ps
CPU time 180.64 seconds
Started Jul 14 05:17:38 PM PDT 24
Finished Jul 14 05:20:39 PM PDT 24
Peak memory 198648 kb
Host smart-b983eff9-1833-4b2d-ab2a-acc1ee2873db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203944022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.3203944022
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.930934704
Short name T223
Test name
Test status
Simulation time 14576794 ps
CPU time 0.57 seconds
Started Jul 14 05:20:55 PM PDT 24
Finished Jul 14 05:20:56 PM PDT 24
Peak memory 194516 kb
Host smart-e37f406e-a168-43ea-a60f-f5f2eb3931d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930934704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.930934704
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1904227924
Short name T492
Test name
Test status
Simulation time 36476326 ps
CPU time 0.83 seconds
Started Jul 14 05:20:48 PM PDT 24
Finished Jul 14 05:20:49 PM PDT 24
Peak memory 196040 kb
Host smart-730720f4-5638-42ad-89ad-78c1e253998f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904227924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1904227924
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.1863476495
Short name T265
Test name
Test status
Simulation time 387755073 ps
CPU time 20.55 seconds
Started Jul 14 05:20:58 PM PDT 24
Finished Jul 14 05:21:19 PM PDT 24
Peak memory 196100 kb
Host smart-50fd0272-baa7-45b5-aad3-65438e79f259
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863476495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.1863476495
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3644832102
Short name T627
Test name
Test status
Simulation time 319058228 ps
CPU time 0.96 seconds
Started Jul 14 05:20:57 PM PDT 24
Finished Jul 14 05:20:58 PM PDT 24
Peak memory 198412 kb
Host smart-55711d7c-8111-4e82-8604-4dbb68728d3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644832102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3644832102
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3439361520
Short name T151
Test name
Test status
Simulation time 175781112 ps
CPU time 1.27 seconds
Started Jul 14 05:20:48 PM PDT 24
Finished Jul 14 05:20:49 PM PDT 24
Peak memory 196728 kb
Host smart-284fb019-21aa-44af-9302-4b427610d707
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439361520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3439361520
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.818661417
Short name T430
Test name
Test status
Simulation time 189610490 ps
CPU time 2.94 seconds
Started Jul 14 05:20:56 PM PDT 24
Finished Jul 14 05:21:00 PM PDT 24
Peak memory 196848 kb
Host smart-93043cfd-0e39-43a8-9b22-2557d5563470
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818661417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.gpio_intr_with_filter_rand_intr_event.818661417
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.678767078
Short name T385
Test name
Test status
Simulation time 106491987 ps
CPU time 2.3 seconds
Started Jul 14 05:20:56 PM PDT 24
Finished Jul 14 05:20:59 PM PDT 24
Peak memory 196524 kb
Host smart-eb500759-f7f4-4aba-aa7b-cb6e73f5aa1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678767078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger.
678767078
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.302298262
Short name T497
Test name
Test status
Simulation time 50229593 ps
CPU time 1.06 seconds
Started Jul 14 05:20:47 PM PDT 24
Finished Jul 14 05:20:49 PM PDT 24
Peak memory 196372 kb
Host smart-08e66fcf-1f6b-49c6-8537-ed142225d791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302298262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.302298262
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.1744209511
Short name T466
Test name
Test status
Simulation time 283517386 ps
CPU time 0.96 seconds
Started Jul 14 05:20:48 PM PDT 24
Finished Jul 14 05:20:49 PM PDT 24
Peak memory 196492 kb
Host smart-290499a6-c70a-43ea-993d-6217e995ac41
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744209511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.1744209511
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.175816552
Short name T374
Test name
Test status
Simulation time 144076224 ps
CPU time 1.97 seconds
Started Jul 14 05:20:58 PM PDT 24
Finished Jul 14 05:21:00 PM PDT 24
Peak memory 198464 kb
Host smart-eb63ad56-eaaa-400c-9d64-762ed30bf8d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175816552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ran
dom_long_reg_writes_reg_reads.175816552
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3923186306
Short name T388
Test name
Test status
Simulation time 362167949 ps
CPU time 1.56 seconds
Started Jul 14 05:20:51 PM PDT 24
Finished Jul 14 05:20:53 PM PDT 24
Peak memory 197396 kb
Host smart-2d1914f4-e1bb-45ee-a9cb-1cf6ceffe91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923186306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3923186306
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1412195775
Short name T616
Test name
Test status
Simulation time 57869095 ps
CPU time 1.17 seconds
Started Jul 14 05:20:49 PM PDT 24
Finished Jul 14 05:20:51 PM PDT 24
Peak memory 196224 kb
Host smart-6d93e638-f073-4a38-8bcb-518fb9211b54
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412195775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1412195775
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1098099826
Short name T491
Test name
Test status
Simulation time 41439798732 ps
CPU time 155.67 seconds
Started Jul 14 05:20:55 PM PDT 24
Finished Jul 14 05:23:31 PM PDT 24
Peak memory 198628 kb
Host smart-4e399107-4432-48c9-a0bf-d53389e8e662
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098099826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1098099826
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3250078882
Short name T680
Test name
Test status
Simulation time 13390172 ps
CPU time 0.58 seconds
Started Jul 14 05:20:58 PM PDT 24
Finished Jul 14 05:20:59 PM PDT 24
Peak memory 194628 kb
Host smart-62feff6f-196f-4914-957f-9d4fbaae8772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250078882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3250078882
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1407284754
Short name T644
Test name
Test status
Simulation time 94626731 ps
CPU time 0.69 seconds
Started Jul 14 05:20:55 PM PDT 24
Finished Jul 14 05:20:56 PM PDT 24
Peak memory 194648 kb
Host smart-1657c1b1-a6e9-4cba-8fe5-5435326fe3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407284754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1407284754
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.2819976159
Short name T537
Test name
Test status
Simulation time 1517888832 ps
CPU time 10.7 seconds
Started Jul 14 05:20:54 PM PDT 24
Finished Jul 14 05:21:05 PM PDT 24
Peak memory 196076 kb
Host smart-921c027d-7467-4446-9352-2c4499beae11
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819976159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.2819976159
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3730071010
Short name T548
Test name
Test status
Simulation time 155835848 ps
CPU time 0.8 seconds
Started Jul 14 05:20:55 PM PDT 24
Finished Jul 14 05:20:57 PM PDT 24
Peak memory 196608 kb
Host smart-76c172f3-b37a-4718-a36b-330a49a2899d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730071010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3730071010
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.4027197034
Short name T530
Test name
Test status
Simulation time 125790652 ps
CPU time 1.55 seconds
Started Jul 14 05:20:54 PM PDT 24
Finished Jul 14 05:20:57 PM PDT 24
Peak memory 196372 kb
Host smart-f587364b-faca-43db-b74d-17a024516e61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027197034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.4027197034
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1328316020
Short name T324
Test name
Test status
Simulation time 319979505 ps
CPU time 3.16 seconds
Started Jul 14 05:20:59 PM PDT 24
Finished Jul 14 05:21:03 PM PDT 24
Peak memory 197012 kb
Host smart-a77b0969-905e-472d-ae42-bc33f19d1654
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328316020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1328316020
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1669087203
Short name T575
Test name
Test status
Simulation time 155860184 ps
CPU time 3.09 seconds
Started Jul 14 05:20:58 PM PDT 24
Finished Jul 14 05:21:01 PM PDT 24
Peak memory 197812 kb
Host smart-0787fffe-2c1a-4494-91eb-ac79122712e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669087203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1669087203
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.324556794
Short name T622
Test name
Test status
Simulation time 59743524 ps
CPU time 1.25 seconds
Started Jul 14 05:20:56 PM PDT 24
Finished Jul 14 05:20:58 PM PDT 24
Peak memory 196648 kb
Host smart-856b1154-9ce8-4ff1-a8b9-3a2965c2b408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324556794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.324556794
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.1899473790
Short name T206
Test name
Test status
Simulation time 186265140 ps
CPU time 1.34 seconds
Started Jul 14 05:20:54 PM PDT 24
Finished Jul 14 05:20:56 PM PDT 24
Peak memory 197624 kb
Host smart-3dbd3555-d580-4379-bdba-cb7eb645e0a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899473790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.1899473790
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.70371202
Short name T119
Test name
Test status
Simulation time 602870249 ps
CPU time 2.58 seconds
Started Jul 14 05:20:57 PM PDT 24
Finished Jul 14 05:21:00 PM PDT 24
Peak memory 198632 kb
Host smart-9ad426fb-17f3-4c66-ba93-a6e409c7b4b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70371202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand
om_long_reg_writes_reg_reads.70371202
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2648380294
Short name T579
Test name
Test status
Simulation time 70797850 ps
CPU time 1.47 seconds
Started Jul 14 05:20:59 PM PDT 24
Finished Jul 14 05:21:01 PM PDT 24
Peak memory 197292 kb
Host smart-02fb80db-eb45-441a-905f-857bfca67d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648380294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2648380294
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.1442710769
Short name T455
Test name
Test status
Simulation time 100119922 ps
CPU time 1.19 seconds
Started Jul 14 05:20:58 PM PDT 24
Finished Jul 14 05:21:00 PM PDT 24
Peak memory 196992 kb
Host smart-e8cee4af-679f-4d4f-8638-ab1b52817a52
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442710769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.1442710769
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.259229343
Short name T469
Test name
Test status
Simulation time 18732901597 ps
CPU time 57.5 seconds
Started Jul 14 05:20:57 PM PDT 24
Finished Jul 14 05:21:55 PM PDT 24
Peak memory 198676 kb
Host smart-ea48bef6-07d9-4da3-8e81-98998d9dff51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259229343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.g
pio_stress_all.259229343
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.2532011243
Short name T410
Test name
Test status
Simulation time 44838201 ps
CPU time 0.6 seconds
Started Jul 14 05:21:09 PM PDT 24
Finished Jul 14 05:21:10 PM PDT 24
Peak memory 194552 kb
Host smart-6add0569-6eff-471d-9b9c-f1d51af3b01c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532011243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.2532011243
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3539365976
Short name T353
Test name
Test status
Simulation time 119457132 ps
CPU time 0.9 seconds
Started Jul 14 05:21:05 PM PDT 24
Finished Jul 14 05:21:06 PM PDT 24
Peak memory 197772 kb
Host smart-6b16e022-34d0-430f-9f2e-22aa10ff1ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539365976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3539365976
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.247342519
Short name T68
Test name
Test status
Simulation time 1856660601 ps
CPU time 14.11 seconds
Started Jul 14 05:21:03 PM PDT 24
Finished Jul 14 05:21:18 PM PDT 24
Peak memory 196084 kb
Host smart-8e34788a-b1d6-4992-aee8-c00c04a1f970
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247342519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stres
s.247342519
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3460677548
Short name T15
Test name
Test status
Simulation time 55917153 ps
CPU time 0.63 seconds
Started Jul 14 05:21:03 PM PDT 24
Finished Jul 14 05:21:04 PM PDT 24
Peak memory 194812 kb
Host smart-0a5cfca2-cce5-4423-8f47-effe615c308a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460677548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3460677548
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.1382852665
Short name T463
Test name
Test status
Simulation time 80908713 ps
CPU time 1.29 seconds
Started Jul 14 05:21:04 PM PDT 24
Finished Jul 14 05:21:06 PM PDT 24
Peak memory 196724 kb
Host smart-241b3bd2-8413-4388-80de-4537c0d0f8b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382852665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1382852665
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.889489257
Short name T445
Test name
Test status
Simulation time 107488391 ps
CPU time 2.13 seconds
Started Jul 14 05:21:06 PM PDT 24
Finished Jul 14 05:21:08 PM PDT 24
Peak memory 198616 kb
Host smart-8654c37b-febb-45d5-afa8-583ef2b675c4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889489257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.gpio_intr_with_filter_rand_intr_event.889489257
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1895475947
Short name T105
Test name
Test status
Simulation time 103436400 ps
CPU time 2.7 seconds
Started Jul 14 05:21:04 PM PDT 24
Finished Jul 14 05:21:07 PM PDT 24
Peak memory 197492 kb
Host smart-ecb3aef8-5fd0-43a3-bc37-6eef7037ee38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895475947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1895475947
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2362458360
Short name T656
Test name
Test status
Simulation time 35361977 ps
CPU time 0.92 seconds
Started Jul 14 05:21:05 PM PDT 24
Finished Jul 14 05:21:06 PM PDT 24
Peak memory 197844 kb
Host smart-cb5342c0-ddae-46be-afd4-cf2094beda0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362458360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2362458360
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1645952036
Short name T451
Test name
Test status
Simulation time 92933062 ps
CPU time 1.09 seconds
Started Jul 14 05:21:03 PM PDT 24
Finished Jul 14 05:21:05 PM PDT 24
Peak memory 196516 kb
Host smart-937a494e-a899-4cd7-82b0-e3f8a89a42e7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645952036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1645952036
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2101044693
Short name T13
Test name
Test status
Simulation time 222776599 ps
CPU time 1.13 seconds
Started Jul 14 05:21:04 PM PDT 24
Finished Jul 14 05:21:06 PM PDT 24
Peak memory 197060 kb
Host smart-36beb9e9-878c-4af8-870b-3f50691a322d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101044693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2101044693
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.4166190949
Short name T244
Test name
Test status
Simulation time 45130866 ps
CPU time 1.15 seconds
Started Jul 14 05:20:57 PM PDT 24
Finished Jul 14 05:20:59 PM PDT 24
Peak memory 196528 kb
Host smart-bc2f397c-8cf2-4093-8c97-d4de72c3813e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166190949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.4166190949
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3503858021
Short name T197
Test name
Test status
Simulation time 54226177 ps
CPU time 1 seconds
Started Jul 14 05:21:02 PM PDT 24
Finished Jul 14 05:21:03 PM PDT 24
Peak memory 197752 kb
Host smart-869b7bae-f838-4dc0-b822-d971da968d88
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503858021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3503858021
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3793789322
Short name T670
Test name
Test status
Simulation time 20637773943 ps
CPU time 98.04 seconds
Started Jul 14 05:21:03 PM PDT 24
Finished Jul 14 05:22:41 PM PDT 24
Peak memory 198684 kb
Host smart-6a71ac82-dd5b-4b04-b29d-5da5c4fdfa38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793789322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3793789322
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.2414078408
Short name T511
Test name
Test status
Simulation time 26962097 ps
CPU time 0.6 seconds
Started Jul 14 05:21:11 PM PDT 24
Finished Jul 14 05:21:12 PM PDT 24
Peak memory 194828 kb
Host smart-ed57da70-d3be-4940-923d-24ff631dfcbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414078408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.2414078408
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.626704948
Short name T283
Test name
Test status
Simulation time 22308625 ps
CPU time 0.72 seconds
Started Jul 14 05:21:10 PM PDT 24
Finished Jul 14 05:21:11 PM PDT 24
Peak memory 195392 kb
Host smart-30aaaf06-0db3-44b7-819d-2894a84b9e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626704948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.626704948
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.361151424
Short name T628
Test name
Test status
Simulation time 1632613294 ps
CPU time 11.74 seconds
Started Jul 14 05:21:09 PM PDT 24
Finished Jul 14 05:21:21 PM PDT 24
Peak memory 196860 kb
Host smart-75b65dc1-a72a-4442-bfc4-f326a784fda5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361151424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stres
s.361151424
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1819457374
Short name T329
Test name
Test status
Simulation time 63385732 ps
CPU time 0.89 seconds
Started Jul 14 05:21:09 PM PDT 24
Finished Jul 14 05:21:11 PM PDT 24
Peak memory 197688 kb
Host smart-f53781fe-b791-4cdd-b426-6b38a0b59302
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819457374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1819457374
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.641432078
Short name T500
Test name
Test status
Simulation time 228160904 ps
CPU time 1.07 seconds
Started Jul 14 05:21:11 PM PDT 24
Finished Jul 14 05:21:12 PM PDT 24
Peak memory 197316 kb
Host smart-6853355b-80c9-4ffd-8d2c-90e883f03ab8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641432078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.641432078
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.870098574
Short name T390
Test name
Test status
Simulation time 38365435 ps
CPU time 1.78 seconds
Started Jul 14 05:21:12 PM PDT 24
Finished Jul 14 05:21:15 PM PDT 24
Peak memory 197204 kb
Host smart-27241cd2-9f6a-4eac-b1c6-bbf823d86444
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870098574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.gpio_intr_with_filter_rand_intr_event.870098574
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.2355367042
Short name T468
Test name
Test status
Simulation time 1788567509 ps
CPU time 3.68 seconds
Started Jul 14 05:21:13 PM PDT 24
Finished Jul 14 05:21:17 PM PDT 24
Peak memory 197768 kb
Host smart-012f646f-bd14-4a4c-b2f9-7f3fa3e79093
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355367042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.2355367042
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1500647302
Short name T484
Test name
Test status
Simulation time 22720887 ps
CPU time 0.76 seconds
Started Jul 14 05:21:05 PM PDT 24
Finished Jul 14 05:21:06 PM PDT 24
Peak memory 195980 kb
Host smart-1781e10f-5bec-4c86-9e2b-49eb153c92e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500647302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1500647302
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1105492103
Short name T585
Test name
Test status
Simulation time 129739348 ps
CPU time 0.89 seconds
Started Jul 14 05:21:10 PM PDT 24
Finished Jul 14 05:21:11 PM PDT 24
Peak memory 196952 kb
Host smart-d6a26ef5-9c86-4180-9f7f-e1afa8297c77
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105492103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1105492103
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.362706048
Short name T427
Test name
Test status
Simulation time 286426214 ps
CPU time 2.89 seconds
Started Jul 14 05:21:12 PM PDT 24
Finished Jul 14 05:21:16 PM PDT 24
Peak memory 198532 kb
Host smart-ea45ad1c-195e-4736-ba46-b2be3a81fd69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362706048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.362706048
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3180891723
Short name T203
Test name
Test status
Simulation time 116593600 ps
CPU time 1.06 seconds
Started Jul 14 05:21:05 PM PDT 24
Finished Jul 14 05:21:06 PM PDT 24
Peak memory 196288 kb
Host smart-3e6da822-99d4-4ec1-bbe2-0ebba53a4bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180891723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3180891723
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1981112207
Short name T525
Test name
Test status
Simulation time 47008537 ps
CPU time 1.32 seconds
Started Jul 14 05:21:05 PM PDT 24
Finished Jul 14 05:21:07 PM PDT 24
Peak memory 196568 kb
Host smart-2e6e2370-9ba8-4abd-b65a-ee5690d1b153
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981112207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1981112207
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3356699799
Short name T439
Test name
Test status
Simulation time 4481587979 ps
CPU time 62.76 seconds
Started Jul 14 05:21:08 PM PDT 24
Finished Jul 14 05:22:11 PM PDT 24
Peak memory 198668 kb
Host smart-aa84d65c-4900-4b42-9a4a-69f2b640ee02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356699799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3356699799
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.1022266931
Short name T170
Test name
Test status
Simulation time 13190152 ps
CPU time 0.59 seconds
Started Jul 14 05:21:19 PM PDT 24
Finished Jul 14 05:21:20 PM PDT 24
Peak memory 194728 kb
Host smart-15441a74-e52d-489c-a4b8-0cb45caf83c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022266931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.1022266931
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2437621758
Short name T612
Test name
Test status
Simulation time 40297801 ps
CPU time 0.79 seconds
Started Jul 14 05:21:21 PM PDT 24
Finished Jul 14 05:21:22 PM PDT 24
Peak memory 195888 kb
Host smart-12d1ea6f-4cd2-4601-b925-92630dddf1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437621758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2437621758
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.400285199
Short name T161
Test name
Test status
Simulation time 662458026 ps
CPU time 17.58 seconds
Started Jul 14 05:21:22 PM PDT 24
Finished Jul 14 05:21:41 PM PDT 24
Peak memory 197628 kb
Host smart-e8740ce7-ca86-4a5e-bb55-1d7f405ff5bc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400285199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stres
s.400285199
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3665865942
Short name T159
Test name
Test status
Simulation time 1173766026 ps
CPU time 0.97 seconds
Started Jul 14 05:21:19 PM PDT 24
Finished Jul 14 05:21:21 PM PDT 24
Peak memory 197696 kb
Host smart-300d35af-2ea5-49cd-87f5-e83e0a3e79b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665865942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3665865942
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.2626808727
Short name T334
Test name
Test status
Simulation time 33485744 ps
CPU time 0.99 seconds
Started Jul 14 05:21:17 PM PDT 24
Finished Jul 14 05:21:19 PM PDT 24
Peak memory 197064 kb
Host smart-07770f47-95f0-4bda-bdae-ca3a9b02d368
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626808727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.2626808727
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3593263745
Short name T351
Test name
Test status
Simulation time 255281165 ps
CPU time 2.25 seconds
Started Jul 14 05:21:19 PM PDT 24
Finished Jul 14 05:21:22 PM PDT 24
Peak memory 198668 kb
Host smart-ebd2418d-2f9e-4ccb-96b6-0288df273972
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593263745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3593263745
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.4021478770
Short name T172
Test name
Test status
Simulation time 41774414 ps
CPU time 1.2 seconds
Started Jul 14 05:21:15 PM PDT 24
Finished Jul 14 05:21:17 PM PDT 24
Peak memory 196088 kb
Host smart-e4b66afc-30f1-439f-b155-0b178da7abe7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021478770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.4021478770
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.4252448516
Short name T552
Test name
Test status
Simulation time 27353766 ps
CPU time 1.1 seconds
Started Jul 14 05:21:17 PM PDT 24
Finished Jul 14 05:21:18 PM PDT 24
Peak memory 197264 kb
Host smart-dfca67c3-cc78-465d-aec6-00999758d63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252448516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.4252448516
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.3871429113
Short name T632
Test name
Test status
Simulation time 39138802 ps
CPU time 0.99 seconds
Started Jul 14 05:21:14 PM PDT 24
Finished Jul 14 05:21:15 PM PDT 24
Peak memory 196736 kb
Host smart-6dbd53a1-23d4-4ea8-b641-80d429c4be33
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871429113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.3871429113
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1826093565
Short name T342
Test name
Test status
Simulation time 1751253168 ps
CPU time 6.03 seconds
Started Jul 14 05:21:22 PM PDT 24
Finished Jul 14 05:21:29 PM PDT 24
Peak memory 198580 kb
Host smart-ea48987c-c2c0-48ff-ae46-0a880cef8680
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826093565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1826093565
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.2920852982
Short name T376
Test name
Test status
Simulation time 172529754 ps
CPU time 1.38 seconds
Started Jul 14 05:21:16 PM PDT 24
Finished Jul 14 05:21:18 PM PDT 24
Peak memory 196348 kb
Host smart-d42458a6-a5fc-4f01-95aa-df9dd9f519a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920852982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2920852982
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2233758345
Short name T442
Test name
Test status
Simulation time 314688066 ps
CPU time 1.56 seconds
Started Jul 14 05:21:17 PM PDT 24
Finished Jul 14 05:21:19 PM PDT 24
Peak memory 198676 kb
Host smart-ae32a9d3-794e-468d-a48c-c0ec9b2b022d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233758345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2233758345
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.119103911
Short name T361
Test name
Test status
Simulation time 13933268292 ps
CPU time 36.86 seconds
Started Jul 14 05:21:15 PM PDT 24
Finished Jul 14 05:21:52 PM PDT 24
Peak memory 198676 kb
Host smart-e7d649dc-d959-4308-ae0d-e1122c2d738a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119103911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.119103911
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2948597210
Short name T584
Test name
Test status
Simulation time 14626426 ps
CPU time 0.65 seconds
Started Jul 14 05:21:24 PM PDT 24
Finished Jul 14 05:21:26 PM PDT 24
Peak memory 194704 kb
Host smart-829284b9-2ed6-4c3b-b059-1e22fef0b711
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948597210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2948597210
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.612244243
Short name T651
Test name
Test status
Simulation time 39053417 ps
CPU time 0.86 seconds
Started Jul 14 05:21:21 PM PDT 24
Finished Jul 14 05:21:22 PM PDT 24
Peak memory 196608 kb
Host smart-b022b295-f561-4cc3-aa76-9fa54adff410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612244243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.612244243
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1977755717
Short name T169
Test name
Test status
Simulation time 398074501 ps
CPU time 19.35 seconds
Started Jul 14 05:21:26 PM PDT 24
Finished Jul 14 05:21:46 PM PDT 24
Peak memory 197412 kb
Host smart-ef57374e-1900-4a6c-b503-48f2c1492dd4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977755717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1977755717
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3683987851
Short name T524
Test name
Test status
Simulation time 612038816 ps
CPU time 0.84 seconds
Started Jul 14 05:21:21 PM PDT 24
Finished Jul 14 05:21:23 PM PDT 24
Peak memory 196568 kb
Host smart-0319ef9c-258e-472a-8bd6-f9d2eed02d6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683987851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3683987851
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3108601234
Short name T699
Test name
Test status
Simulation time 16057787 ps
CPU time 0.67 seconds
Started Jul 14 05:21:26 PM PDT 24
Finished Jul 14 05:21:28 PM PDT 24
Peak memory 194764 kb
Host smart-d0af2cf9-5fc5-4d6d-b1ad-eaf63685f09c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108601234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3108601234
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3672481414
Short name T692
Test name
Test status
Simulation time 154043231 ps
CPU time 1.35 seconds
Started Jul 14 05:21:22 PM PDT 24
Finished Jul 14 05:21:24 PM PDT 24
Peak memory 196976 kb
Host smart-0438be09-e5c9-4c6b-9d9e-59b4ef2957eb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672481414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3672481414
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.3728920324
Short name T594
Test name
Test status
Simulation time 121552160 ps
CPU time 3.72 seconds
Started Jul 14 05:21:22 PM PDT 24
Finished Jul 14 05:21:27 PM PDT 24
Peak memory 198668 kb
Host smart-b4c45f38-68af-4013-aa0a-309af3ecc1b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728920324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.3728920324
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3405911269
Short name T255
Test name
Test status
Simulation time 18409882 ps
CPU time 0.67 seconds
Started Jul 14 05:21:16 PM PDT 24
Finished Jul 14 05:21:17 PM PDT 24
Peak memory 195684 kb
Host smart-3c278695-306b-40b2-bfe2-bec5d1fa61e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405911269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3405911269
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.593059507
Short name T299
Test name
Test status
Simulation time 109523542 ps
CPU time 0.73 seconds
Started Jul 14 05:21:22 PM PDT 24
Finished Jul 14 05:21:24 PM PDT 24
Peak memory 195972 kb
Host smart-d6fdb192-30dd-4c23-839a-2f25457a9652
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593059507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup
_pulldown.593059507
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3273081133
Short name T341
Test name
Test status
Simulation time 79019569 ps
CPU time 1.27 seconds
Started Jul 14 05:21:25 PM PDT 24
Finished Jul 14 05:21:28 PM PDT 24
Peak memory 198504 kb
Host smart-35233593-1dc7-4b65-9c90-1bee6551ee38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273081133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3273081133
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.482294982
Short name T663
Test name
Test status
Simulation time 81817607 ps
CPU time 1.3 seconds
Started Jul 14 05:21:16 PM PDT 24
Finished Jul 14 05:21:18 PM PDT 24
Peak memory 196488 kb
Host smart-9332aab8-d698-4e0d-aabe-3b986fcb2e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482294982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.482294982
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2793619891
Short name T70
Test name
Test status
Simulation time 75173817 ps
CPU time 1.36 seconds
Started Jul 14 05:21:17 PM PDT 24
Finished Jul 14 05:21:19 PM PDT 24
Peak memory 196560 kb
Host smart-80bceb30-d488-4b1e-b0b3-7f2a3b5f5b92
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793619891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2793619891
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2374707177
Short name T313
Test name
Test status
Simulation time 6052641676 ps
CPU time 66.02 seconds
Started Jul 14 05:21:23 PM PDT 24
Finished Jul 14 05:22:30 PM PDT 24
Peak memory 198764 kb
Host smart-4c9abd4c-db23-40c9-a05c-5103120aef26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374707177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2374707177
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.69511280
Short name T24
Test name
Test status
Simulation time 30215999970 ps
CPU time 797.13 seconds
Started Jul 14 05:21:26 PM PDT 24
Finished Jul 14 05:34:44 PM PDT 24
Peak memory 198820 kb
Host smart-0d00129a-0243-40ee-8d38-1ee7b4939a69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=69511280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.69511280
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.158506616
Short name T416
Test name
Test status
Simulation time 11353683 ps
CPU time 0.55 seconds
Started Jul 14 05:21:29 PM PDT 24
Finished Jul 14 05:21:30 PM PDT 24
Peak memory 194500 kb
Host smart-4cbe9ec7-be49-439b-aab7-ff34ca8138a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158506616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.158506616
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3354783459
Short name T629
Test name
Test status
Simulation time 15806831 ps
CPU time 0.67 seconds
Started Jul 14 05:21:24 PM PDT 24
Finished Jul 14 05:21:25 PM PDT 24
Peak memory 194524 kb
Host smart-c350cf89-f6b5-469d-849f-0c173270e232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354783459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3354783459
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.1445598963
Short name T282
Test name
Test status
Simulation time 634789191 ps
CPU time 16.94 seconds
Started Jul 14 05:21:32 PM PDT 24
Finished Jul 14 05:21:49 PM PDT 24
Peak memory 198508 kb
Host smart-afc23d0c-6f05-40db-acf2-8e69caeaa2e8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445598963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.1445598963
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3072575153
Short name T698
Test name
Test status
Simulation time 53914698 ps
CPU time 0.89 seconds
Started Jul 14 05:21:29 PM PDT 24
Finished Jul 14 05:21:30 PM PDT 24
Peak memory 197364 kb
Host smart-de5c5d1e-67b2-4577-b8f9-120a26ec95a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072575153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3072575153
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.2568775611
Short name T268
Test name
Test status
Simulation time 100831412 ps
CPU time 0.7 seconds
Started Jul 14 05:21:30 PM PDT 24
Finished Jul 14 05:21:32 PM PDT 24
Peak memory 195708 kb
Host smart-02acfb4d-c96d-49bc-ae70-05d95233d0af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568775611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.2568775611
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3186219573
Short name T635
Test name
Test status
Simulation time 1234165400 ps
CPU time 2.82 seconds
Started Jul 14 05:21:30 PM PDT 24
Finished Jul 14 05:21:34 PM PDT 24
Peak memory 198540 kb
Host smart-5d236eb9-17b0-42b4-bed2-b69385e97399
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186219573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3186219573
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.802446502
Short name T372
Test name
Test status
Simulation time 128168048 ps
CPU time 3.67 seconds
Started Jul 14 05:21:35 PM PDT 24
Finished Jul 14 05:21:39 PM PDT 24
Peak memory 196480 kb
Host smart-7d33acc6-4d88-435b-a2f3-be6f01ed7134
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802446502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
802446502
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1202576436
Short name T381
Test name
Test status
Simulation time 52967197 ps
CPU time 1.12 seconds
Started Jul 14 05:21:24 PM PDT 24
Finished Jul 14 05:21:26 PM PDT 24
Peak memory 196388 kb
Host smart-5df0e4d5-7940-407e-8015-10dbb5566d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202576436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1202576436
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2495610407
Short name T671
Test name
Test status
Simulation time 30436928 ps
CPU time 0.8 seconds
Started Jul 14 05:21:23 PM PDT 24
Finished Jul 14 05:21:25 PM PDT 24
Peak memory 196148 kb
Host smart-fa43f921-34bb-412c-a54a-0f9dd09da339
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495610407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2495610407
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.882541264
Short name T307
Test name
Test status
Simulation time 320327486 ps
CPU time 3.88 seconds
Started Jul 14 05:21:30 PM PDT 24
Finished Jul 14 05:21:35 PM PDT 24
Peak memory 198660 kb
Host smart-5d245c65-0d14-4cf4-950d-f05e3c8acc29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882541264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.882541264
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3105403527
Short name T241
Test name
Test status
Simulation time 49350033 ps
CPU time 1 seconds
Started Jul 14 05:21:25 PM PDT 24
Finished Jul 14 05:21:27 PM PDT 24
Peak memory 196260 kb
Host smart-1ec0eb83-3dee-4866-bc7b-6d9cc1aa40ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105403527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3105403527
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1796327098
Short name T431
Test name
Test status
Simulation time 36175243 ps
CPU time 0.79 seconds
Started Jul 14 05:21:25 PM PDT 24
Finished Jul 14 05:21:26 PM PDT 24
Peak memory 196568 kb
Host smart-dbb4dd91-01c5-415f-97c3-66e9401b6be5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796327098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1796327098
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.4011483420
Short name T365
Test name
Test status
Simulation time 17986446036 ps
CPU time 66.11 seconds
Started Jul 14 05:21:33 PM PDT 24
Finished Jul 14 05:22:39 PM PDT 24
Peak memory 198644 kb
Host smart-9c8958da-d97f-4f1b-ac3e-47b8cad7ee0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011483420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.4011483420
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.627859183
Short name T558
Test name
Test status
Simulation time 21294139 ps
CPU time 0.6 seconds
Started Jul 14 05:21:39 PM PDT 24
Finished Jul 14 05:21:40 PM PDT 24
Peak memory 194696 kb
Host smart-ab8261ca-6abb-4890-8852-1bc0a096b08a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627859183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.627859183
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2297169066
Short name T424
Test name
Test status
Simulation time 105528668 ps
CPU time 0.88 seconds
Started Jul 14 05:21:31 PM PDT 24
Finished Jul 14 05:21:32 PM PDT 24
Peak memory 197244 kb
Host smart-9dacf62f-99a1-44fc-89be-b53be70a5272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297169066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2297169066
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.1926696350
Short name T239
Test name
Test status
Simulation time 495458083 ps
CPU time 14.98 seconds
Started Jul 14 05:21:34 PM PDT 24
Finished Jul 14 05:21:49 PM PDT 24
Peak memory 197312 kb
Host smart-cbde8f73-39bb-4f69-a310-ed63a9616095
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926696350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.1926696350
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.4112936801
Short name T602
Test name
Test status
Simulation time 105900545 ps
CPU time 0.75 seconds
Started Jul 14 05:21:45 PM PDT 24
Finished Jul 14 05:21:46 PM PDT 24
Peak memory 196000 kb
Host smart-3588bf0b-8525-4525-b715-1bb57694cb87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112936801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.4112936801
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1202393240
Short name T199
Test name
Test status
Simulation time 157214932 ps
CPU time 0.82 seconds
Started Jul 14 05:21:30 PM PDT 24
Finished Jul 14 05:21:31 PM PDT 24
Peak memory 196628 kb
Host smart-d268ed18-0a83-449d-b9e0-ed157981e647
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202393240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1202393240
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.3407312760
Short name T108
Test name
Test status
Simulation time 260265348 ps
CPU time 1.25 seconds
Started Jul 14 05:21:31 PM PDT 24
Finished Jul 14 05:21:33 PM PDT 24
Peak memory 198268 kb
Host smart-6007c9c9-2473-49d3-95d7-9bed83d33181
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407312760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.3407312760
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.4185632367
Short name T570
Test name
Test status
Simulation time 343478193 ps
CPU time 2.29 seconds
Started Jul 14 05:21:30 PM PDT 24
Finished Jul 14 05:21:33 PM PDT 24
Peak memory 196544 kb
Host smart-e9f0e625-f9ec-4c70-8d58-d549b6111969
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185632367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.4185632367
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3665423227
Short name T355
Test name
Test status
Simulation time 83023431 ps
CPU time 1.29 seconds
Started Jul 14 05:21:30 PM PDT 24
Finished Jul 14 05:21:32 PM PDT 24
Peak memory 197124 kb
Host smart-1a7d6427-d751-4fcf-ae7f-1681426db53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665423227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3665423227
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1882222201
Short name T546
Test name
Test status
Simulation time 46984126 ps
CPU time 1 seconds
Started Jul 14 05:21:33 PM PDT 24
Finished Jul 14 05:21:34 PM PDT 24
Peak memory 197304 kb
Host smart-31a914e6-a3ce-438b-8a77-01ccfb26cafb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882222201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1882222201
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3777938067
Short name T187
Test name
Test status
Simulation time 90277277 ps
CPU time 1.22 seconds
Started Jul 14 05:21:38 PM PDT 24
Finished Jul 14 05:21:40 PM PDT 24
Peak memory 198232 kb
Host smart-0528c990-c68b-4766-bb4c-a75d6398ee7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777938067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3777938067
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1657699158
Short name T129
Test name
Test status
Simulation time 1127501865 ps
CPU time 1.4 seconds
Started Jul 14 05:21:35 PM PDT 24
Finished Jul 14 05:21:37 PM PDT 24
Peak memory 197412 kb
Host smart-155226f5-0df4-40ec-9278-aa165c0ab271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657699158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1657699158
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1974684073
Short name T688
Test name
Test status
Simulation time 34195934 ps
CPU time 0.96 seconds
Started Jul 14 05:21:30 PM PDT 24
Finished Jul 14 05:21:31 PM PDT 24
Peak memory 195740 kb
Host smart-65c09dc0-0a1e-4a47-8268-3a586adc2ab0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974684073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1974684073
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3716658979
Short name T116
Test name
Test status
Simulation time 11994421167 ps
CPU time 77.48 seconds
Started Jul 14 05:21:37 PM PDT 24
Finished Jul 14 05:22:55 PM PDT 24
Peak memory 198784 kb
Host smart-a7a7b4a8-2327-4f67-9ee4-40992a1d5c9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716658979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3716658979
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.117742928
Short name T557
Test name
Test status
Simulation time 190423575252 ps
CPU time 1050.46 seconds
Started Jul 14 05:21:42 PM PDT 24
Finished Jul 14 05:39:14 PM PDT 24
Peak memory 198872 kb
Host smart-68bf7a2e-2c19-434a-ae59-641a8c9ec2aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=117742928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.117742928
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.3229636617
Short name T577
Test name
Test status
Simulation time 23812188 ps
CPU time 0.6 seconds
Started Jul 14 05:21:37 PM PDT 24
Finished Jul 14 05:21:38 PM PDT 24
Peak memory 195232 kb
Host smart-f8eceb6b-bc59-482b-b018-70ff8f1871e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229636617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.3229636617
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.3743618440
Short name T193
Test name
Test status
Simulation time 56950958 ps
CPU time 0.62 seconds
Started Jul 14 05:21:36 PM PDT 24
Finished Jul 14 05:21:37 PM PDT 24
Peak memory 195128 kb
Host smart-69a42ca4-af52-42c4-bc7d-4f8665664313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743618440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.3743618440
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.4174195862
Short name T204
Test name
Test status
Simulation time 1765109770 ps
CPU time 23.41 seconds
Started Jul 14 05:21:42 PM PDT 24
Finished Jul 14 05:22:06 PM PDT 24
Peak memory 198652 kb
Host smart-69bf75e4-b0a1-4822-b6e8-53c92bb7020a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174195862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.4174195862
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.703164644
Short name T450
Test name
Test status
Simulation time 82246478 ps
CPU time 0.69 seconds
Started Jul 14 05:21:37 PM PDT 24
Finished Jul 14 05:21:39 PM PDT 24
Peak memory 195964 kb
Host smart-8927b266-d410-48c7-be1d-919b42e2e32b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703164644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.703164644
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2718856373
Short name T180
Test name
Test status
Simulation time 105258343 ps
CPU time 0.97 seconds
Started Jul 14 05:21:37 PM PDT 24
Finished Jul 14 05:21:39 PM PDT 24
Peak memory 197140 kb
Host smart-06c596a2-3996-4f24-8ecb-3f2b51c3993d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718856373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2718856373
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.642594586
Short name T449
Test name
Test status
Simulation time 59467542 ps
CPU time 2.53 seconds
Started Jul 14 05:21:38 PM PDT 24
Finished Jul 14 05:21:41 PM PDT 24
Peak memory 198484 kb
Host smart-82bebfee-effd-4bf8-85b0-30e1a013b9be
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642594586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.642594586
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2518229760
Short name T369
Test name
Test status
Simulation time 216843789 ps
CPU time 1.8 seconds
Started Jul 14 05:21:45 PM PDT 24
Finished Jul 14 05:21:47 PM PDT 24
Peak memory 196664 kb
Host smart-c40b5d3e-8cf8-4236-aed9-c8f55b3e6c1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518229760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2518229760
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3450660165
Short name T547
Test name
Test status
Simulation time 15464831 ps
CPU time 0.68 seconds
Started Jul 14 05:21:34 PM PDT 24
Finished Jul 14 05:21:35 PM PDT 24
Peak memory 194864 kb
Host smart-05695316-4f8e-451c-8380-f387567405df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450660165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3450660165
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3526844695
Short name T572
Test name
Test status
Simulation time 67891037 ps
CPU time 0.86 seconds
Started Jul 14 05:21:36 PM PDT 24
Finished Jul 14 05:21:37 PM PDT 24
Peak memory 197104 kb
Host smart-5ef63051-fdd9-4610-943c-14c6234e9592
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526844695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3526844695
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.629054452
Short name T245
Test name
Test status
Simulation time 1208269873 ps
CPU time 7.33 seconds
Started Jul 14 05:21:37 PM PDT 24
Finished Jul 14 05:21:45 PM PDT 24
Peak memory 198556 kb
Host smart-085a239e-be92-4c6b-be2b-eaec6ec801aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629054452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ran
dom_long_reg_writes_reg_reads.629054452
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.761388606
Short name T408
Test name
Test status
Simulation time 287944144 ps
CPU time 1.15 seconds
Started Jul 14 05:21:36 PM PDT 24
Finished Jul 14 05:21:38 PM PDT 24
Peak memory 196096 kb
Host smart-e901f106-bda5-49e2-8d8e-056a0237dc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761388606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.761388606
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.2617935294
Short name T144
Test name
Test status
Simulation time 88765782 ps
CPU time 0.75 seconds
Started Jul 14 05:21:36 PM PDT 24
Finished Jul 14 05:21:37 PM PDT 24
Peak memory 194720 kb
Host smart-ac52735a-645b-42e4-b869-7ca416f42724
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617935294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.2617935294
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.382226923
Short name T276
Test name
Test status
Simulation time 130770465611 ps
CPU time 179.51 seconds
Started Jul 14 05:21:42 PM PDT 24
Finished Jul 14 05:24:42 PM PDT 24
Peak memory 198724 kb
Host smart-14092909-5620-4143-9143-23461a3ea0ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382226923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.382226923
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2001227674
Short name T624
Test name
Test status
Simulation time 18106623 ps
CPU time 0.59 seconds
Started Jul 14 05:21:43 PM PDT 24
Finished Jul 14 05:21:44 PM PDT 24
Peak memory 194528 kb
Host smart-1b46b82a-59da-4f1d-8998-830eb641f522
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001227674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2001227674
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1092822019
Short name T578
Test name
Test status
Simulation time 31685315 ps
CPU time 0.82 seconds
Started Jul 14 05:21:42 PM PDT 24
Finished Jul 14 05:21:44 PM PDT 24
Peak memory 196012 kb
Host smart-38cf6b44-2331-4d91-bd77-4f5095c2c139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092822019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1092822019
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1291248967
Short name T551
Test name
Test status
Simulation time 521692363 ps
CPU time 7.3 seconds
Started Jul 14 05:21:48 PM PDT 24
Finished Jul 14 05:21:56 PM PDT 24
Peak memory 196900 kb
Host smart-d6642da0-558e-45d0-a1ed-4c0381f433b9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291248967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1291248967
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.4156159018
Short name T710
Test name
Test status
Simulation time 271872275 ps
CPU time 0.88 seconds
Started Jul 14 05:21:45 PM PDT 24
Finished Jul 14 05:21:46 PM PDT 24
Peak memory 197576 kb
Host smart-303df8f1-f643-48f2-b573-bfe3bd74ce42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156159018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.4156159018
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.4213153544
Short name T250
Test name
Test status
Simulation time 68844963 ps
CPU time 1.11 seconds
Started Jul 14 05:21:38 PM PDT 24
Finished Jul 14 05:21:40 PM PDT 24
Peak memory 196416 kb
Host smart-b13550a6-8885-4fed-9b49-586167f3b98d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213153544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.4213153544
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3233193148
Short name T205
Test name
Test status
Simulation time 45546673 ps
CPU time 1.91 seconds
Started Jul 14 05:21:46 PM PDT 24
Finished Jul 14 05:21:49 PM PDT 24
Peak memory 198648 kb
Host smart-76e873b4-bbe6-4391-b602-6202905276fc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233193148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3233193148
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.2301209694
Short name T302
Test name
Test status
Simulation time 694305412 ps
CPU time 2.49 seconds
Started Jul 14 05:21:45 PM PDT 24
Finished Jul 14 05:21:48 PM PDT 24
Peak memory 196424 kb
Host smart-85b070e4-3a0b-4dfc-afc4-102398de7bad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301209694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.2301209694
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.4003123776
Short name T323
Test name
Test status
Simulation time 53063364 ps
CPU time 1.29 seconds
Started Jul 14 05:21:37 PM PDT 24
Finished Jul 14 05:21:39 PM PDT 24
Peak memory 197240 kb
Host smart-9ab2128d-78b7-4a24-8978-c87099621c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003123776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.4003123776
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1388261869
Short name T297
Test name
Test status
Simulation time 94759211 ps
CPU time 1.06 seconds
Started Jul 14 05:21:37 PM PDT 24
Finished Jul 14 05:21:38 PM PDT 24
Peak memory 197200 kb
Host smart-c7f0d8b0-c09e-4284-a825-d8ac0d004ed7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388261869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.1388261869
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2523348306
Short name T218
Test name
Test status
Simulation time 146097590 ps
CPU time 5.99 seconds
Started Jul 14 05:21:43 PM PDT 24
Finished Jul 14 05:21:50 PM PDT 24
Peak memory 198496 kb
Host smart-2003e6d5-344b-4340-918a-709c161d2588
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523348306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2523348306
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1065747857
Short name T163
Test name
Test status
Simulation time 125654162 ps
CPU time 0.88 seconds
Started Jul 14 05:21:41 PM PDT 24
Finished Jul 14 05:21:43 PM PDT 24
Peak memory 197052 kb
Host smart-2d78a1f7-846d-4ffe-80af-8defca4daf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065747857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1065747857
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1296722463
Short name T414
Test name
Test status
Simulation time 120364638 ps
CPU time 0.84 seconds
Started Jul 14 05:21:36 PM PDT 24
Finished Jul 14 05:21:38 PM PDT 24
Peak memory 195688 kb
Host smart-cbd5dc11-2447-4b69-8e57-2e45fb495d93
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296722463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1296722463
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.1400489066
Short name T10
Test name
Test status
Simulation time 12685529530 ps
CPU time 134.29 seconds
Started Jul 14 05:21:45 PM PDT 24
Finished Jul 14 05:24:00 PM PDT 24
Peak memory 198672 kb
Host smart-1d0bb791-0c73-4238-9de9-4dc0e1219ce2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400489066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.1400489066
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.3131366232
Short name T559
Test name
Test status
Simulation time 15093024 ps
CPU time 0.6 seconds
Started Jul 14 05:17:50 PM PDT 24
Finished Jul 14 05:17:50 PM PDT 24
Peak memory 195532 kb
Host smart-fe68095e-7de4-45d3-8257-2adc0a923d39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131366232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3131366232
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1146707053
Short name T296
Test name
Test status
Simulation time 28687532 ps
CPU time 0.87 seconds
Started Jul 14 05:17:43 PM PDT 24
Finished Jul 14 05:17:44 PM PDT 24
Peak memory 197056 kb
Host smart-8ad72217-1fff-4208-9276-830596b2f1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146707053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1146707053
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.2305275799
Short name T420
Test name
Test status
Simulation time 782826828 ps
CPU time 21.05 seconds
Started Jul 14 05:17:44 PM PDT 24
Finished Jul 14 05:18:05 PM PDT 24
Peak memory 197388 kb
Host smart-51c5808a-dc10-4637-ba56-989f31f5c460
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305275799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.2305275799
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2066756956
Short name T634
Test name
Test status
Simulation time 78673968 ps
CPU time 0.73 seconds
Started Jul 14 05:17:50 PM PDT 24
Finished Jul 14 05:17:51 PM PDT 24
Peak memory 195432 kb
Host smart-bbdee4d3-2dcf-485a-be1c-f0a13e33c7b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066756956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2066756956
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3263817979
Short name T461
Test name
Test status
Simulation time 18488096 ps
CPU time 0.66 seconds
Started Jul 14 05:17:42 PM PDT 24
Finished Jul 14 05:17:43 PM PDT 24
Peak memory 194748 kb
Host smart-7edd48d1-ce42-4de7-943f-215257f1955d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263817979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3263817979
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3746494371
Short name T472
Test name
Test status
Simulation time 97268567 ps
CPU time 3.56 seconds
Started Jul 14 05:17:44 PM PDT 24
Finished Jul 14 05:17:48 PM PDT 24
Peak memory 198668 kb
Host smart-11ee2854-a9ea-4038-b045-156c58109082
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746494371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3746494371
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.1175659437
Short name T279
Test name
Test status
Simulation time 79033179 ps
CPU time 1.6 seconds
Started Jul 14 05:17:45 PM PDT 24
Finished Jul 14 05:17:47 PM PDT 24
Peak memory 196584 kb
Host smart-ad833945-807f-49c5-99d7-56b60a770386
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175659437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
1175659437
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.1064919518
Short name T221
Test name
Test status
Simulation time 33397222 ps
CPU time 1.27 seconds
Started Jul 14 05:17:45 PM PDT 24
Finished Jul 14 05:17:47 PM PDT 24
Peak memory 198664 kb
Host smart-0446043e-ab91-44a1-9327-5634cc6e9256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064919518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1064919518
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.3033080665
Short name T665
Test name
Test status
Simulation time 77858877 ps
CPU time 1.11 seconds
Started Jul 14 05:17:45 PM PDT 24
Finished Jul 14 05:17:46 PM PDT 24
Peak memory 196460 kb
Host smart-2ce19250-0550-4e72-8625-92277c0606e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033080665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.3033080665
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.4096947546
Short name T179
Test name
Test status
Simulation time 65895090 ps
CPU time 1.46 seconds
Started Jul 14 05:17:51 PM PDT 24
Finished Jul 14 05:17:53 PM PDT 24
Peak memory 198520 kb
Host smart-af597bd5-ca6b-4972-bb0d-7d6c2f385815
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096947546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.4096947546
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2837687155
Short name T31
Test name
Test status
Simulation time 38385582 ps
CPU time 0.78 seconds
Started Jul 14 05:17:51 PM PDT 24
Finished Jul 14 05:17:52 PM PDT 24
Peak memory 214060 kb
Host smart-939bf340-be42-4b74-8137-2987a25cac47
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837687155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2837687155
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.3866172973
Short name T536
Test name
Test status
Simulation time 56525771 ps
CPU time 0.98 seconds
Started Jul 14 05:17:42 PM PDT 24
Finished Jul 14 05:17:44 PM PDT 24
Peak memory 196940 kb
Host smart-9cc8ad7e-d9ad-421a-af4c-8a0f52e8eb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866172973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3866172973
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2937734203
Short name T222
Test name
Test status
Simulation time 27426421 ps
CPU time 0.8 seconds
Started Jul 14 05:17:44 PM PDT 24
Finished Jul 14 05:17:45 PM PDT 24
Peak memory 196392 kb
Host smart-6963806e-c61b-4931-83f5-c2866bcde0fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937734203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2937734203
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.410813431
Short name T9
Test name
Test status
Simulation time 26350049128 ps
CPU time 168.02 seconds
Started Jul 14 05:17:50 PM PDT 24
Finished Jul 14 05:20:39 PM PDT 24
Peak memory 198656 kb
Host smart-9ec14656-4774-488a-9bf0-bf4cdf24b6bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410813431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gp
io_stress_all.410813431
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.1746248070
Short name T327
Test name
Test status
Simulation time 37403187 ps
CPU time 0.57 seconds
Started Jul 14 05:21:48 PM PDT 24
Finished Jul 14 05:21:49 PM PDT 24
Peak memory 194544 kb
Host smart-06db8a0b-ac06-437b-bcf9-dfb48bb144fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746248070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.1746248070
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.2031830868
Short name T707
Test name
Test status
Simulation time 21982778 ps
CPU time 0.62 seconds
Started Jul 14 05:21:44 PM PDT 24
Finished Jul 14 05:21:45 PM PDT 24
Peak memory 195276 kb
Host smart-49eec589-cf85-47f1-bc7d-bcfd7bd06891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031830868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.2031830868
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2058993028
Short name T292
Test name
Test status
Simulation time 3959333691 ps
CPU time 27.73 seconds
Started Jul 14 05:21:51 PM PDT 24
Finished Jul 14 05:22:19 PM PDT 24
Peak memory 198700 kb
Host smart-57b21461-ca43-4882-b299-ba6f1bb09df9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058993028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2058993028
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.2649519498
Short name T332
Test name
Test status
Simulation time 135227831 ps
CPU time 1.08 seconds
Started Jul 14 05:21:49 PM PDT 24
Finished Jul 14 05:21:51 PM PDT 24
Peak memory 197248 kb
Host smart-a8e65123-6763-4a55-b030-f0086dd9c990
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649519498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.2649519498
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3828609323
Short name T623
Test name
Test status
Simulation time 44119936 ps
CPU time 1.24 seconds
Started Jul 14 05:21:46 PM PDT 24
Finished Jul 14 05:21:48 PM PDT 24
Peak memory 196752 kb
Host smart-d28adc77-2e28-4f72-8800-84f907c26915
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828609323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3828609323
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.380674761
Short name T192
Test name
Test status
Simulation time 52844642 ps
CPU time 1.93 seconds
Started Jul 14 05:21:51 PM PDT 24
Finished Jul 14 05:21:53 PM PDT 24
Peak memory 198704 kb
Host smart-9b7e65c4-15b8-47ac-b588-30b530e6f6eb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380674761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.380674761
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.4015692572
Short name T555
Test name
Test status
Simulation time 102915676 ps
CPU time 0.99 seconds
Started Jul 14 05:21:41 PM PDT 24
Finished Jul 14 05:21:43 PM PDT 24
Peak memory 196276 kb
Host smart-f33a871a-81dc-46f7-b65e-855027372057
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015692572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.4015692572
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1695269266
Short name T403
Test name
Test status
Simulation time 60091648 ps
CPU time 1.19 seconds
Started Jul 14 05:21:45 PM PDT 24
Finished Jul 14 05:21:47 PM PDT 24
Peak memory 196532 kb
Host smart-77aa4684-3bad-49d7-a9ec-6c67723c6ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695269266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1695269266
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.4033032245
Short name T233
Test name
Test status
Simulation time 24447232 ps
CPU time 1.01 seconds
Started Jul 14 05:21:45 PM PDT 24
Finished Jul 14 05:21:47 PM PDT 24
Peak memory 196408 kb
Host smart-e48aa0b1-7d57-48e3-8d48-9ace7a20ee95
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033032245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.4033032245
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3982675156
Short name T356
Test name
Test status
Simulation time 1213607427 ps
CPU time 6.54 seconds
Started Jul 14 05:21:50 PM PDT 24
Finished Jul 14 05:21:57 PM PDT 24
Peak memory 198616 kb
Host smart-761d89f2-8554-49c5-8388-eb7133f4fd50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982675156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.3982675156
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.1816775182
Short name T17
Test name
Test status
Simulation time 36376322 ps
CPU time 1.22 seconds
Started Jul 14 05:21:46 PM PDT 24
Finished Jul 14 05:21:48 PM PDT 24
Peak memory 197112 kb
Host smart-e4e70352-216b-490f-b446-8b119ca869ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816775182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.1816775182
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.277638008
Short name T352
Test name
Test status
Simulation time 144105749 ps
CPU time 1.25 seconds
Started Jul 14 05:21:44 PM PDT 24
Finished Jul 14 05:21:45 PM PDT 24
Peak memory 198640 kb
Host smart-0509e614-d24c-492d-b97c-e8ee353d2add
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277638008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.277638008
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.514568778
Short name T494
Test name
Test status
Simulation time 3455437498 ps
CPU time 35.86 seconds
Started Jul 14 05:21:50 PM PDT 24
Finished Jul 14 05:22:27 PM PDT 24
Peak memory 198680 kb
Host smart-a8f53652-4996-4313-864f-a2e0accce3cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514568778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.514568778
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3204394436
Short name T508
Test name
Test status
Simulation time 12298998 ps
CPU time 0.57 seconds
Started Jul 14 05:21:54 PM PDT 24
Finished Jul 14 05:21:55 PM PDT 24
Peak memory 194628 kb
Host smart-3f2b5ba0-0405-4224-a035-36db320c23b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204394436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3204394436
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.4087159912
Short name T71
Test name
Test status
Simulation time 24524183 ps
CPU time 0.66 seconds
Started Jul 14 05:21:55 PM PDT 24
Finished Jul 14 05:21:56 PM PDT 24
Peak memory 195504 kb
Host smart-38bc4900-e2e1-427c-aef7-1c06ae6259b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087159912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.4087159912
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.831180903
Short name T652
Test name
Test status
Simulation time 1075379706 ps
CPU time 8 seconds
Started Jul 14 05:21:56 PM PDT 24
Finished Jul 14 05:22:04 PM PDT 24
Peak memory 197496 kb
Host smart-b729d4b6-7193-4da2-a093-6ef1058e0ab4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831180903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stres
s.831180903
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.155828716
Short name T306
Test name
Test status
Simulation time 69109645 ps
CPU time 1.08 seconds
Started Jul 14 05:21:54 PM PDT 24
Finished Jul 14 05:21:56 PM PDT 24
Peak memory 196988 kb
Host smart-cc748c8b-4c30-449f-8cae-af59e7eab7ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155828716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.155828716
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3240013658
Short name T123
Test name
Test status
Simulation time 85479717 ps
CPU time 0.9 seconds
Started Jul 14 05:21:54 PM PDT 24
Finished Jul 14 05:21:55 PM PDT 24
Peak memory 196172 kb
Host smart-f23d6d75-871a-4c55-ad2d-bd5996192ee7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240013658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3240013658
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.2824306282
Short name T267
Test name
Test status
Simulation time 89332098 ps
CPU time 3.83 seconds
Started Jul 14 05:21:56 PM PDT 24
Finished Jul 14 05:22:01 PM PDT 24
Peak memory 198740 kb
Host smart-066cbea0-8b35-4b49-8b09-6b41093612e1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824306282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.2824306282
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2838260049
Short name T566
Test name
Test status
Simulation time 147250022 ps
CPU time 2.6 seconds
Started Jul 14 05:21:52 PM PDT 24
Finished Jul 14 05:21:55 PM PDT 24
Peak memory 198076 kb
Host smart-71b031aa-8819-4042-af96-a54019bfdfee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838260049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2838260049
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.882884654
Short name T453
Test name
Test status
Simulation time 77531977 ps
CPU time 1.29 seconds
Started Jul 14 05:21:48 PM PDT 24
Finished Jul 14 05:21:50 PM PDT 24
Peak memory 196392 kb
Host smart-99ad2a6e-9692-4882-ae2e-7d25550f53f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882884654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.882884654
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.1715631418
Short name T134
Test name
Test status
Simulation time 43747827 ps
CPU time 0.97 seconds
Started Jul 14 05:21:50 PM PDT 24
Finished Jul 14 05:21:51 PM PDT 24
Peak memory 196568 kb
Host smart-a9e78952-cb2b-4e29-b6e2-a6fdb00e5c99
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715631418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.1715631418
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.874047059
Short name T8
Test name
Test status
Simulation time 910658074 ps
CPU time 5.39 seconds
Started Jul 14 05:21:51 PM PDT 24
Finished Jul 14 05:21:57 PM PDT 24
Peak memory 198536 kb
Host smart-b71f6312-a087-4a38-bb1f-1407fa629e19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874047059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.874047059
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.2027515704
Short name T406
Test name
Test status
Simulation time 208382524 ps
CPU time 1.04 seconds
Started Jul 14 05:21:49 PM PDT 24
Finished Jul 14 05:21:51 PM PDT 24
Peak memory 196120 kb
Host smart-5483b019-12ab-421c-bc97-5d3b6fd31486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027515704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.2027515704
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.828045843
Short name T386
Test name
Test status
Simulation time 171809127 ps
CPU time 1.44 seconds
Started Jul 14 05:21:52 PM PDT 24
Finished Jul 14 05:21:54 PM PDT 24
Peak memory 196908 kb
Host smart-6f800240-af39-456c-b334-a806be49d22a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828045843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.828045843
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2273855818
Short name T3
Test name
Test status
Simulation time 19024881069 ps
CPU time 207.23 seconds
Started Jul 14 05:22:00 PM PDT 24
Finished Jul 14 05:25:28 PM PDT 24
Peak memory 198688 kb
Host smart-d4b9fb55-4740-4b15-b322-b7591ebc6804
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273855818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2273855818
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.721132357
Short name T480
Test name
Test status
Simulation time 94564701991 ps
CPU time 341.05 seconds
Started Jul 14 05:21:52 PM PDT 24
Finished Jul 14 05:27:34 PM PDT 24
Peak memory 198888 kb
Host smart-4ac0f1ef-3a18-4ff1-832a-97cebf548588
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=721132357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.721132357
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.4029500773
Short name T212
Test name
Test status
Simulation time 34577905 ps
CPU time 0.58 seconds
Started Jul 14 05:21:59 PM PDT 24
Finished Jul 14 05:22:00 PM PDT 24
Peak memory 195352 kb
Host smart-1d437fd2-9f17-482e-bb66-c1107b69c655
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029500773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.4029500773
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.403109720
Short name T490
Test name
Test status
Simulation time 58263016 ps
CPU time 0.7 seconds
Started Jul 14 05:21:57 PM PDT 24
Finished Jul 14 05:21:58 PM PDT 24
Peak memory 194708 kb
Host smart-54cd0ebb-ce54-435c-9f56-dae80e3ccb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403109720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.403109720
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.238078571
Short name T694
Test name
Test status
Simulation time 177202795 ps
CPU time 8.85 seconds
Started Jul 14 05:22:00 PM PDT 24
Finished Jul 14 05:22:10 PM PDT 24
Peak memory 196080 kb
Host smart-7f63d365-224f-474d-9e15-b89164c42f6f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238078571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stres
s.238078571
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.515764133
Short name T428
Test name
Test status
Simulation time 215382802 ps
CPU time 0.86 seconds
Started Jul 14 05:22:00 PM PDT 24
Finished Jul 14 05:22:02 PM PDT 24
Peak memory 196716 kb
Host smart-1973b29e-5eb3-4d65-8c06-77a9ac91e023
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515764133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.515764133
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1956053934
Short name T392
Test name
Test status
Simulation time 54927836 ps
CPU time 0.94 seconds
Started Jul 14 05:21:55 PM PDT 24
Finished Jul 14 05:21:56 PM PDT 24
Peak memory 197312 kb
Host smart-3300f135-4432-45df-8317-c289bed318df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956053934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1956053934
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.2017633659
Short name T516
Test name
Test status
Simulation time 873119773 ps
CPU time 3.17 seconds
Started Jul 14 05:21:57 PM PDT 24
Finished Jul 14 05:22:01 PM PDT 24
Peak memory 196988 kb
Host smart-45a02276-bb1b-4b29-976e-e160c78b7ab4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017633659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.2017633659
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2872489981
Short name T619
Test name
Test status
Simulation time 73542231 ps
CPU time 2.55 seconds
Started Jul 14 05:21:57 PM PDT 24
Finished Jul 14 05:22:00 PM PDT 24
Peak memory 197864 kb
Host smart-21a9a128-a237-4e81-a73b-e2185ee3d7db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872489981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2872489981
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3592141499
Short name T705
Test name
Test status
Simulation time 101275980 ps
CPU time 0.78 seconds
Started Jul 14 05:21:52 PM PDT 24
Finished Jul 14 05:21:53 PM PDT 24
Peak memory 196096 kb
Host smart-b40385a2-7308-4574-adde-4a26e58e83eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592141499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3592141499
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3542490892
Short name T196
Test name
Test status
Simulation time 63013158 ps
CPU time 0.85 seconds
Started Jul 14 05:22:00 PM PDT 24
Finished Jul 14 05:22:02 PM PDT 24
Peak memory 197104 kb
Host smart-0da35c4b-1398-4ead-a891-d3e3e92094e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542490892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3542490892
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3422223454
Short name T454
Test name
Test status
Simulation time 1195992099 ps
CPU time 1.59 seconds
Started Jul 14 05:21:59 PM PDT 24
Finished Jul 14 05:22:02 PM PDT 24
Peak memory 197796 kb
Host smart-8676562f-8005-4dc5-ba4f-0c46f2759fee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422223454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3422223454
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3397219564
Short name T62
Test name
Test status
Simulation time 182211336 ps
CPU time 0.96 seconds
Started Jul 14 05:21:53 PM PDT 24
Finished Jul 14 05:21:55 PM PDT 24
Peak memory 197124 kb
Host smart-6d61a8cd-7089-4d1f-a965-781b6c57e75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397219564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3397219564
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1773090712
Short name T637
Test name
Test status
Simulation time 97085803 ps
CPU time 1.39 seconds
Started Jul 14 05:21:56 PM PDT 24
Finished Jul 14 05:21:58 PM PDT 24
Peak memory 197468 kb
Host smart-c632109f-1f39-47c9-9908-1c14aa68af5e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773090712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1773090712
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1516184150
Short name T114
Test name
Test status
Simulation time 92337749299 ps
CPU time 165.06 seconds
Started Jul 14 05:22:00 PM PDT 24
Finished Jul 14 05:24:46 PM PDT 24
Peak memory 198664 kb
Host smart-5aec6ac8-edf2-45ff-9563-fb2112e2d20e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516184150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1516184150
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1059123555
Short name T240
Test name
Test status
Simulation time 11781444 ps
CPU time 0.59 seconds
Started Jul 14 05:22:05 PM PDT 24
Finished Jul 14 05:22:07 PM PDT 24
Peak memory 194520 kb
Host smart-e54d877b-d860-43a7-9949-fd2243e416f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059123555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1059123555
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1074296232
Short name T139
Test name
Test status
Simulation time 27165721 ps
CPU time 0.68 seconds
Started Jul 14 05:22:02 PM PDT 24
Finished Jul 14 05:22:04 PM PDT 24
Peak memory 195208 kb
Host smart-5d04ef36-a9e7-4f9e-9910-883a030a0e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074296232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1074296232
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.4105200361
Short name T506
Test name
Test status
Simulation time 843473961 ps
CPU time 30.32 seconds
Started Jul 14 05:21:59 PM PDT 24
Finished Jul 14 05:22:30 PM PDT 24
Peak memory 196080 kb
Host smart-713f1600-225f-4b01-9f19-fa7276a601bf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105200361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.4105200361
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3860014927
Short name T636
Test name
Test status
Simulation time 128110178 ps
CPU time 0.98 seconds
Started Jul 14 05:21:59 PM PDT 24
Finished Jul 14 05:22:01 PM PDT 24
Peak memory 197220 kb
Host smart-af8e04eb-b066-4bb7-bdd6-08d72caa2182
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860014927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3860014927
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.4185028450
Short name T604
Test name
Test status
Simulation time 48071569 ps
CPU time 1.33 seconds
Started Jul 14 05:21:58 PM PDT 24
Finished Jul 14 05:22:00 PM PDT 24
Peak memory 197716 kb
Host smart-098fc6ed-6408-4a3a-a507-6a9fd8b32cd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185028450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.4185028450
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.1585689316
Short name T520
Test name
Test status
Simulation time 449106614 ps
CPU time 2.58 seconds
Started Jul 14 05:21:59 PM PDT 24
Finished Jul 14 05:22:03 PM PDT 24
Peak memory 198660 kb
Host smart-6c8f485e-3c91-46ce-8da5-897d3ed2b41f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585689316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.1585689316
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.1553453401
Short name T592
Test name
Test status
Simulation time 534720208 ps
CPU time 3.9 seconds
Started Jul 14 05:22:00 PM PDT 24
Finished Jul 14 05:22:05 PM PDT 24
Peak memory 197596 kb
Host smart-cae92fe9-ef48-44ff-9766-1c2d3f143b79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553453401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.1553453401
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2895507580
Short name T148
Test name
Test status
Simulation time 14642690 ps
CPU time 0.64 seconds
Started Jul 14 05:22:00 PM PDT 24
Finished Jul 14 05:22:01 PM PDT 24
Peak memory 194868 kb
Host smart-838ec58f-c872-401c-b85b-985556eede36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895507580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2895507580
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3359412960
Short name T502
Test name
Test status
Simulation time 69199188 ps
CPU time 0.83 seconds
Started Jul 14 05:21:58 PM PDT 24
Finished Jul 14 05:21:59 PM PDT 24
Peak memory 196972 kb
Host smart-e3891835-a001-40b6-b54a-10d61c1e6631
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359412960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3359412960
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3851687472
Short name T248
Test name
Test status
Simulation time 1031130375 ps
CPU time 5.9 seconds
Started Jul 14 05:21:59 PM PDT 24
Finished Jul 14 05:22:06 PM PDT 24
Peak memory 198500 kb
Host smart-6148a1e1-0797-4995-9752-6c9da58a7e3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851687472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3851687472
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.633154344
Short name T219
Test name
Test status
Simulation time 379201277 ps
CPU time 0.82 seconds
Started Jul 14 05:29:12 PM PDT 24
Finished Jul 14 05:29:14 PM PDT 24
Peak memory 195852 kb
Host smart-18b71e19-b1dc-47c2-a2a5-462a1de5887b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633154344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.633154344
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.2451292531
Short name T504
Test name
Test status
Simulation time 28282782 ps
CPU time 1.06 seconds
Started Jul 14 05:21:58 PM PDT 24
Finished Jul 14 05:21:59 PM PDT 24
Peak memory 196872 kb
Host smart-db083d69-bfc9-434b-ba8d-5d1d0a9acc6e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451292531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.2451292531
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.3401538118
Short name T112
Test name
Test status
Simulation time 63669829876 ps
CPU time 76.45 seconds
Started Jul 14 05:22:06 PM PDT 24
Finished Jul 14 05:23:23 PM PDT 24
Peak memory 198628 kb
Host smart-212e592e-63cf-41f6-a9f8-9dc7a77a1a33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401538118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.3401538118
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.3629279003
Short name T57
Test name
Test status
Simulation time 78995921403 ps
CPU time 469.69 seconds
Started Jul 14 05:22:04 PM PDT 24
Finished Jul 14 05:29:55 PM PDT 24
Peak memory 198884 kb
Host smart-0eda5e4d-4d3c-41de-893c-e17a698b9498
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3629279003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.3629279003
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1030402241
Short name T606
Test name
Test status
Simulation time 49775486 ps
CPU time 0.59 seconds
Started Jul 14 05:22:09 PM PDT 24
Finished Jul 14 05:22:10 PM PDT 24
Peak memory 194780 kb
Host smart-79221215-3698-41d8-8229-dd2e6edec714
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030402241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1030402241
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.4106883273
Short name T141
Test name
Test status
Simulation time 109741932 ps
CPU time 1.01 seconds
Started Jul 14 05:22:08 PM PDT 24
Finished Jul 14 05:22:09 PM PDT 24
Peak memory 197060 kb
Host smart-7c4e5291-ad5d-4d54-99d6-44a911426056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106883273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.4106883273
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.143558692
Short name T510
Test name
Test status
Simulation time 2056869744 ps
CPU time 19.27 seconds
Started Jul 14 05:22:09 PM PDT 24
Finished Jul 14 05:22:28 PM PDT 24
Peak memory 197392 kb
Host smart-d984266b-6430-4c46-b210-4904624c9b15
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143558692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stres
s.143558692
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.774005191
Short name T436
Test name
Test status
Simulation time 43693384 ps
CPU time 0.7 seconds
Started Jul 14 05:22:16 PM PDT 24
Finished Jul 14 05:22:18 PM PDT 24
Peak memory 195364 kb
Host smart-9ce598c2-97a0-48d8-be30-dc82912a45b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774005191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.774005191
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.3291530770
Short name T50
Test name
Test status
Simulation time 199953789 ps
CPU time 1.02 seconds
Started Jul 14 05:22:05 PM PDT 24
Finished Jul 14 05:22:06 PM PDT 24
Peak memory 197076 kb
Host smart-d17d99de-940b-47df-b31c-5d2a352bc921
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291530770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.3291530770
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2103229558
Short name T325
Test name
Test status
Simulation time 183881581 ps
CPU time 2.03 seconds
Started Jul 14 05:22:06 PM PDT 24
Finished Jul 14 05:22:08 PM PDT 24
Peak memory 198600 kb
Host smart-ec0b3a2c-649b-44f1-80fc-94d852cb843f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103229558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2103229558
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.2683652378
Short name T499
Test name
Test status
Simulation time 199605122 ps
CPU time 1.26 seconds
Started Jul 14 05:22:03 PM PDT 24
Finished Jul 14 05:22:05 PM PDT 24
Peak memory 197216 kb
Host smart-3a362843-1653-4b5a-805c-83caefa4ce45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683652378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.2683652378
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.440107793
Short name T340
Test name
Test status
Simulation time 513695292 ps
CPU time 1.19 seconds
Started Jul 14 05:22:05 PM PDT 24
Finished Jul 14 05:22:07 PM PDT 24
Peak memory 197736 kb
Host smart-5f08ea85-5dc6-4da2-a683-b773ff89fa79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440107793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.440107793
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3772947868
Short name T118
Test name
Test status
Simulation time 110626995 ps
CPU time 1.04 seconds
Started Jul 14 05:22:04 PM PDT 24
Finished Jul 14 05:22:06 PM PDT 24
Peak memory 196484 kb
Host smart-10325e02-9b07-44e3-a1bb-ac0082a377b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772947868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3772947868
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1309994472
Short name T487
Test name
Test status
Simulation time 278507803 ps
CPU time 2.4 seconds
Started Jul 14 05:22:19 PM PDT 24
Finished Jul 14 05:22:23 PM PDT 24
Peak memory 198528 kb
Host smart-4818df2e-4753-40c4-a216-81c905cf82b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309994472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1309994472
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1124890194
Short name T601
Test name
Test status
Simulation time 37776496 ps
CPU time 1.12 seconds
Started Jul 14 05:22:04 PM PDT 24
Finished Jul 14 05:22:05 PM PDT 24
Peak memory 196068 kb
Host smart-f90705f7-b863-47b4-8852-7caa255f72b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124890194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1124890194
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.382653810
Short name T258
Test name
Test status
Simulation time 156900383 ps
CPU time 1.34 seconds
Started Jul 14 05:22:04 PM PDT 24
Finished Jul 14 05:22:06 PM PDT 24
Peak memory 198664 kb
Host smart-2b721cb9-9888-4fd7-8062-fc2ed599f8a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382653810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.382653810
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.537386096
Short name T293
Test name
Test status
Simulation time 29398079013 ps
CPU time 199.65 seconds
Started Jul 14 05:22:16 PM PDT 24
Finished Jul 14 05:25:36 PM PDT 24
Peak memory 198672 kb
Host smart-80e6268a-fabe-4059-936f-1b361972634e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537386096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.537386096
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3517794531
Short name T478
Test name
Test status
Simulation time 22322984 ps
CPU time 0.56 seconds
Started Jul 14 05:22:12 PM PDT 24
Finished Jul 14 05:22:13 PM PDT 24
Peak memory 194552 kb
Host smart-316a1cf8-124b-4da4-a2aa-19f2ec6c8cad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517794531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3517794531
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.529450843
Short name T167
Test name
Test status
Simulation time 83204002 ps
CPU time 0.72 seconds
Started Jul 14 05:22:12 PM PDT 24
Finished Jul 14 05:22:13 PM PDT 24
Peak memory 196396 kb
Host smart-ab810c36-d3fd-4fb4-af7f-e612fa51f908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529450843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.529450843
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.1968066388
Short name T693
Test name
Test status
Simulation time 480049058 ps
CPU time 17.04 seconds
Started Jul 14 05:22:24 PM PDT 24
Finished Jul 14 05:22:42 PM PDT 24
Peak memory 196068 kb
Host smart-2f405fa4-171c-41f6-be9c-69b1e79a1857
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968066388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.1968066388
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3208462172
Short name T695
Test name
Test status
Simulation time 73366488 ps
CPU time 0.87 seconds
Started Jul 14 05:22:18 PM PDT 24
Finished Jul 14 05:22:20 PM PDT 24
Peak memory 196536 kb
Host smart-53ccb275-1e8c-47af-a9a7-ac170c85f025
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208462172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3208462172
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2262166730
Short name T523
Test name
Test status
Simulation time 104551309 ps
CPU time 0.8 seconds
Started Jul 14 05:22:16 PM PDT 24
Finished Jul 14 05:22:17 PM PDT 24
Peak memory 195924 kb
Host smart-2070db5c-f248-4f7e-b44f-ba81c32995f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262166730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2262166730
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1283493710
Short name T597
Test name
Test status
Simulation time 77259889 ps
CPU time 1.59 seconds
Started Jul 14 05:22:11 PM PDT 24
Finished Jul 14 05:22:13 PM PDT 24
Peak memory 196956 kb
Host smart-9032516d-981c-4860-9e13-a8181d1e8b44
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283493710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1283493710
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2610224451
Short name T456
Test name
Test status
Simulation time 141769182 ps
CPU time 1.38 seconds
Started Jul 14 05:22:22 PM PDT 24
Finished Jul 14 05:22:24 PM PDT 24
Peak memory 196664 kb
Host smart-99634da9-61c4-43c1-8b19-7e2304f97212
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610224451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2610224451
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1391217565
Short name T359
Test name
Test status
Simulation time 28829268 ps
CPU time 0.82 seconds
Started Jul 14 05:22:10 PM PDT 24
Finished Jul 14 05:22:12 PM PDT 24
Peak memory 195972 kb
Host smart-3f8dd193-18f2-4edf-a87d-f55d38e91666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391217565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1391217565
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3580564787
Short name T305
Test name
Test status
Simulation time 78061572 ps
CPU time 0.97 seconds
Started Jul 14 05:22:17 PM PDT 24
Finished Jul 14 05:22:18 PM PDT 24
Peak memory 197300 kb
Host smart-0a50fb68-c3ce-4124-a872-7cf126719356
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580564787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.3580564787
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.120208283
Short name T315
Test name
Test status
Simulation time 401916034 ps
CPU time 3.38 seconds
Started Jul 14 05:22:16 PM PDT 24
Finished Jul 14 05:22:20 PM PDT 24
Peak memory 198532 kb
Host smart-ad93e6d6-54cd-41fe-860f-12e69091c1da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120208283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ran
dom_long_reg_writes_reg_reads.120208283
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.757205086
Short name T401
Test name
Test status
Simulation time 43899707 ps
CPU time 0.81 seconds
Started Jul 14 05:22:12 PM PDT 24
Finished Jul 14 05:22:13 PM PDT 24
Peak memory 195792 kb
Host smart-94843cc7-b518-42a5-9a78-24f996eaf6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757205086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.757205086
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.304499772
Short name T18
Test name
Test status
Simulation time 38755054 ps
CPU time 1.14 seconds
Started Jul 14 05:22:18 PM PDT 24
Finished Jul 14 05:22:20 PM PDT 24
Peak memory 196352 kb
Host smart-7555c1a0-f073-4cb0-8d7b-ff30537420c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304499772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.304499772
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.239357803
Short name T6
Test name
Test status
Simulation time 34242057293 ps
CPU time 111.39 seconds
Started Jul 14 05:22:12 PM PDT 24
Finished Jul 14 05:24:04 PM PDT 24
Peak memory 198784 kb
Host smart-ca25b87e-7099-4516-b5d3-802399222399
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239357803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.g
pio_stress_all.239357803
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1301501780
Short name T357
Test name
Test status
Simulation time 33027316 ps
CPU time 0.58 seconds
Started Jul 14 05:22:20 PM PDT 24
Finished Jul 14 05:22:21 PM PDT 24
Peak memory 194540 kb
Host smart-6aa64015-9a1a-4119-a351-35c1666f0e29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301501780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1301501780
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.455198076
Short name T691
Test name
Test status
Simulation time 68090409 ps
CPU time 0.77 seconds
Started Jul 14 05:22:21 PM PDT 24
Finished Jul 14 05:22:22 PM PDT 24
Peak memory 195804 kb
Host smart-9fcc060c-4935-43f3-8377-8f3928f3b8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455198076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.455198076
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.4270352845
Short name T617
Test name
Test status
Simulation time 1150944506 ps
CPU time 13.41 seconds
Started Jul 14 05:22:19 PM PDT 24
Finished Jul 14 05:22:33 PM PDT 24
Peak memory 197472 kb
Host smart-434ae155-912a-4221-a0b2-907b0fcb9a19
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270352845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.4270352845
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.1093481790
Short name T350
Test name
Test status
Simulation time 156254883 ps
CPU time 1.06 seconds
Started Jul 14 05:22:20 PM PDT 24
Finished Jul 14 05:22:21 PM PDT 24
Peak memory 198648 kb
Host smart-684b2d9c-ada5-4929-87fb-8dc6cc2adb33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093481790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.1093481790
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2552063896
Short name T143
Test name
Test status
Simulation time 1149157697 ps
CPU time 1.22 seconds
Started Jul 14 05:22:17 PM PDT 24
Finished Jul 14 05:22:19 PM PDT 24
Peak memory 196344 kb
Host smart-9c3f9432-2ee8-43b4-8e48-3f2f15093ed3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552063896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2552063896
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2759100282
Short name T521
Test name
Test status
Simulation time 278609897 ps
CPU time 2.67 seconds
Started Jul 14 05:22:17 PM PDT 24
Finished Jul 14 05:22:20 PM PDT 24
Peak memory 197016 kb
Host smart-680bb7d9-0b4a-4fa1-b957-0a4e2573f93b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759100282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2759100282
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1035896548
Short name T433
Test name
Test status
Simulation time 1255137549 ps
CPU time 3.83 seconds
Started Jul 14 05:22:20 PM PDT 24
Finished Jul 14 05:22:24 PM PDT 24
Peak memory 197624 kb
Host smart-b552153d-46d5-4791-840a-05cf8d0f40ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035896548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1035896548
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3553233874
Short name T661
Test name
Test status
Simulation time 45959035 ps
CPU time 0.76 seconds
Started Jul 14 05:22:17 PM PDT 24
Finished Jul 14 05:22:18 PM PDT 24
Peak memory 195916 kb
Host smart-217e5f60-b420-428a-ac4c-002ca51dd3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553233874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3553233874
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.365295541
Short name T109
Test name
Test status
Simulation time 24933432 ps
CPU time 0.99 seconds
Started Jul 14 05:22:18 PM PDT 24
Finished Jul 14 05:22:20 PM PDT 24
Peak memory 196536 kb
Host smart-f0ba923a-dc7f-48cd-ad0e-f0bad66af7b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365295541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullup
_pulldown.365295541
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.4063419789
Short name T514
Test name
Test status
Simulation time 155662667 ps
CPU time 2.92 seconds
Started Jul 14 05:22:17 PM PDT 24
Finished Jul 14 05:22:21 PM PDT 24
Peak memory 198540 kb
Host smart-30e30beb-b956-4bf0-9c1c-ffc2acb09d6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063419789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.4063419789
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3863189731
Short name T188
Test name
Test status
Simulation time 142944992 ps
CPU time 1.04 seconds
Started Jul 14 05:22:18 PM PDT 24
Finished Jul 14 05:22:20 PM PDT 24
Peak memory 196088 kb
Host smart-88dd3746-6c13-4427-9300-d46692817cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863189731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3863189731
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.3754970433
Short name T405
Test name
Test status
Simulation time 20691829 ps
CPU time 0.94 seconds
Started Jul 14 05:22:21 PM PDT 24
Finished Jul 14 05:22:22 PM PDT 24
Peak memory 195884 kb
Host smart-f752af67-f1ef-4bb1-aeb8-647ffb8708b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754970433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.3754970433
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2612413226
Short name T5
Test name
Test status
Simulation time 11753392045 ps
CPU time 126.53 seconds
Started Jul 14 05:22:18 PM PDT 24
Finished Jul 14 05:24:25 PM PDT 24
Peak memory 198688 kb
Host smart-28e22177-5956-4e69-a2e1-b2d49d076385
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612413226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2612413226
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.49052804
Short name T677
Test name
Test status
Simulation time 12946015 ps
CPU time 0.57 seconds
Started Jul 14 05:22:24 PM PDT 24
Finished Jul 14 05:22:26 PM PDT 24
Peak memory 195224 kb
Host smart-a1c4b3da-e6b3-4803-bb60-2c0075b4f973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49052804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.49052804
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3757519449
Short name T543
Test name
Test status
Simulation time 15903012 ps
CPU time 0.67 seconds
Started Jul 14 05:22:24 PM PDT 24
Finished Jul 14 05:22:26 PM PDT 24
Peak memory 195292 kb
Host smart-20f2ae14-f41e-44b5-aa23-3ed7e201b247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757519449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3757519449
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2393352383
Short name T162
Test name
Test status
Simulation time 80328532 ps
CPU time 4.09 seconds
Started Jul 14 05:22:24 PM PDT 24
Finished Jul 14 05:22:29 PM PDT 24
Peak memory 197076 kb
Host smart-de797402-a5d1-4c2c-bc9c-2c94fb7d3625
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393352383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2393352383
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.1855151082
Short name T608
Test name
Test status
Simulation time 50444993 ps
CPU time 0.8 seconds
Started Jul 14 05:22:21 PM PDT 24
Finished Jul 14 05:22:22 PM PDT 24
Peak memory 197120 kb
Host smart-a65709b3-efb8-4e43-a65f-b41433a659e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855151082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1855151082
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2528293457
Short name T631
Test name
Test status
Simulation time 35041689 ps
CPU time 0.83 seconds
Started Jul 14 05:22:24 PM PDT 24
Finished Jul 14 05:22:26 PM PDT 24
Peak memory 196104 kb
Host smart-0aa60b49-e261-42cd-9e02-1b24e29cfc6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528293457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2528293457
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.168432913
Short name T438
Test name
Test status
Simulation time 52588353 ps
CPU time 1.98 seconds
Started Jul 14 05:22:22 PM PDT 24
Finished Jul 14 05:22:24 PM PDT 24
Peak memory 198888 kb
Host smart-88a010c8-599b-4ead-aa0c-46ca8be53a4a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168432913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.168432913
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3826505639
Short name T364
Test name
Test status
Simulation time 441172356 ps
CPU time 3.4 seconds
Started Jul 14 05:22:22 PM PDT 24
Finished Jul 14 05:22:26 PM PDT 24
Peak memory 198740 kb
Host smart-e6a0d983-4027-479b-a903-84587c419736
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826505639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3826505639
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2797568323
Short name T567
Test name
Test status
Simulation time 213137395 ps
CPU time 1.05 seconds
Started Jul 14 05:22:20 PM PDT 24
Finished Jul 14 05:22:21 PM PDT 24
Peak memory 196496 kb
Host smart-886f86fa-cd3d-4907-a16b-7d5fa4346730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797568323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2797568323
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.596533185
Short name T220
Test name
Test status
Simulation time 24839765 ps
CPU time 0.75 seconds
Started Jul 14 05:22:18 PM PDT 24
Finished Jul 14 05:22:19 PM PDT 24
Peak memory 195832 kb
Host smart-f1cca3b2-0a8f-41fb-b0f3-c0772bfe0b48
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596533185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.596533185
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2123730756
Short name T176
Test name
Test status
Simulation time 121343916 ps
CPU time 4.64 seconds
Started Jul 14 05:22:23 PM PDT 24
Finished Jul 14 05:22:28 PM PDT 24
Peak memory 198188 kb
Host smart-df0ae16d-b6da-4045-bf4a-c146903bdd98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123730756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2123730756
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.3861601123
Short name T679
Test name
Test status
Simulation time 57185810 ps
CPU time 1.07 seconds
Started Jul 14 05:22:18 PM PDT 24
Finished Jul 14 05:22:20 PM PDT 24
Peak memory 197036 kb
Host smart-6c59546e-3866-4579-8a14-fc957ee8cd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861601123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.3861601123
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1764354117
Short name T346
Test name
Test status
Simulation time 71222094 ps
CPU time 1.05 seconds
Started Jul 14 05:22:17 PM PDT 24
Finished Jul 14 05:22:18 PM PDT 24
Peak memory 196324 kb
Host smart-8d5d4c60-b52f-4841-aa7c-a6b232726165
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764354117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1764354117
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.430193344
Short name T434
Test name
Test status
Simulation time 10233962982 ps
CPU time 112.2 seconds
Started Jul 14 05:22:24 PM PDT 24
Finished Jul 14 05:24:17 PM PDT 24
Peak memory 198644 kb
Host smart-9df7fbdc-e58b-4deb-b543-01ef75e23b39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430193344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.g
pio_stress_all.430193344
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.88544586
Short name T45
Test name
Test status
Simulation time 48184140 ps
CPU time 0.59 seconds
Started Jul 14 05:22:30 PM PDT 24
Finished Jul 14 05:22:31 PM PDT 24
Peak memory 194736 kb
Host smart-0da14f0a-6c0d-46ab-aa8d-e9c38f1d9210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88544586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.88544586
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.2985101825
Short name T133
Test name
Test status
Simulation time 69400094 ps
CPU time 0.64 seconds
Started Jul 14 05:22:23 PM PDT 24
Finished Jul 14 05:22:25 PM PDT 24
Peak memory 194716 kb
Host smart-49242eca-268b-4e1b-8288-482b1fd4620f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985101825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.2985101825
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.488133831
Short name T217
Test name
Test status
Simulation time 1259058597 ps
CPU time 20.03 seconds
Started Jul 14 05:22:24 PM PDT 24
Finished Jul 14 05:22:45 PM PDT 24
Peak memory 197456 kb
Host smart-efdafee2-855b-415b-99a2-bb7c34babc86
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488133831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.488133831
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1920065951
Short name T640
Test name
Test status
Simulation time 65425746 ps
CPU time 0.78 seconds
Started Jul 14 05:22:23 PM PDT 24
Finished Jul 14 05:22:24 PM PDT 24
Peak memory 196444 kb
Host smart-5244d8df-8205-4e87-b5ac-b46aa7b6e75e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920065951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1920065951
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.2959280236
Short name T288
Test name
Test status
Simulation time 24639838 ps
CPU time 0.73 seconds
Started Jul 14 05:22:23 PM PDT 24
Finished Jul 14 05:22:24 PM PDT 24
Peak memory 194856 kb
Host smart-100fcd6d-647d-4b3c-bcf7-0381c0bef955
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959280236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2959280236
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2858888303
Short name T569
Test name
Test status
Simulation time 217122125 ps
CPU time 2.31 seconds
Started Jul 14 05:22:22 PM PDT 24
Finished Jul 14 05:22:25 PM PDT 24
Peak memory 198428 kb
Host smart-300e807b-afc8-461e-9f24-bc8c2a52a082
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858888303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2858888303
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.1141059184
Short name T473
Test name
Test status
Simulation time 28718588 ps
CPU time 0.93 seconds
Started Jul 14 05:22:24 PM PDT 24
Finished Jul 14 05:22:26 PM PDT 24
Peak memory 196064 kb
Host smart-75b29ec2-3a49-413f-9675-cf90cb9c868b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141059184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.1141059184
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.234838419
Short name T411
Test name
Test status
Simulation time 54979550 ps
CPU time 1.28 seconds
Started Jul 14 05:22:23 PM PDT 24
Finished Jul 14 05:22:25 PM PDT 24
Peak memory 197692 kb
Host smart-79a47640-7f91-4076-a61a-7aa74c6426b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234838419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.234838419
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2882660317
Short name T668
Test name
Test status
Simulation time 91495714 ps
CPU time 1.24 seconds
Started Jul 14 05:22:21 PM PDT 24
Finished Jul 14 05:22:23 PM PDT 24
Peak memory 197048 kb
Host smart-31403528-be75-4af1-8b1c-de80ff0e0aa8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882660317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2882660317
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3057833499
Short name T553
Test name
Test status
Simulation time 540086287 ps
CPU time 6.17 seconds
Started Jul 14 05:22:25 PM PDT 24
Finished Jul 14 05:22:32 PM PDT 24
Peak memory 198488 kb
Host smart-495b6d12-81c5-4769-b045-59f8bcc9bb5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057833499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3057833499
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2310445970
Short name T287
Test name
Test status
Simulation time 244455523 ps
CPU time 1.21 seconds
Started Jul 14 05:22:21 PM PDT 24
Finished Jul 14 05:22:22 PM PDT 24
Peak memory 197704 kb
Host smart-55683fbe-2f05-499d-8ef5-0637570c3063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310445970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2310445970
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.3064979577
Short name T337
Test name
Test status
Simulation time 111113374 ps
CPU time 1.32 seconds
Started Jul 14 05:22:25 PM PDT 24
Finished Jul 14 05:22:27 PM PDT 24
Peak memory 197096 kb
Host smart-ba8a6c69-869e-4f54-a89c-b08b144527a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064979577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.3064979577
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2090600342
Short name T249
Test name
Test status
Simulation time 10617920945 ps
CPU time 47.66 seconds
Started Jul 14 05:22:30 PM PDT 24
Finished Jul 14 05:23:18 PM PDT 24
Peak memory 198720 kb
Host smart-cae854a4-c45d-40d3-933b-c9a7d8f427f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090600342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2090600342
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.99238090
Short name T59
Test name
Test status
Simulation time 49857329772 ps
CPU time 1570.68 seconds
Started Jul 14 05:22:30 PM PDT 24
Finished Jul 14 05:48:41 PM PDT 24
Peak memory 198888 kb
Host smart-0bded3ac-ce85-443e-99ec-79d3c357fe34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=99238090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.99238090
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.2840257515
Short name T673
Test name
Test status
Simulation time 11146464 ps
CPU time 0.56 seconds
Started Jul 14 05:22:37 PM PDT 24
Finished Jul 14 05:22:38 PM PDT 24
Peak memory 194604 kb
Host smart-5bda95eb-5f97-4f5a-aac6-0a4cd909cea1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840257515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2840257515
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.3459431148
Short name T61
Test name
Test status
Simulation time 31452703 ps
CPU time 0.77 seconds
Started Jul 14 05:22:29 PM PDT 24
Finished Jul 14 05:22:30 PM PDT 24
Peak memory 195504 kb
Host smart-3b7185aa-62d6-4fc5-9bb0-5e05da4af896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459431148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.3459431148
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2463850980
Short name T235
Test name
Test status
Simulation time 3186759386 ps
CPU time 26.12 seconds
Started Jul 14 05:22:29 PM PDT 24
Finished Jul 14 05:22:56 PM PDT 24
Peak memory 198668 kb
Host smart-a5effeaf-31e1-482b-af89-a910cb979c7b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463850980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2463850980
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2980582572
Short name T648
Test name
Test status
Simulation time 238668465 ps
CPU time 0.97 seconds
Started Jul 14 05:22:28 PM PDT 24
Finished Jul 14 05:22:30 PM PDT 24
Peak memory 196928 kb
Host smart-a1b00172-7a64-41af-a10c-364be23ad52e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980582572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2980582572
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2281283178
Short name T52
Test name
Test status
Simulation time 71953405 ps
CPU time 1.2 seconds
Started Jul 14 05:22:30 PM PDT 24
Finished Jul 14 05:22:32 PM PDT 24
Peak memory 197424 kb
Host smart-dff99354-e89c-4074-8583-f7b67d6f7ac1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281283178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2281283178
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2718204992
Short name T654
Test name
Test status
Simulation time 514849354 ps
CPU time 3.32 seconds
Started Jul 14 05:22:33 PM PDT 24
Finished Jul 14 05:22:36 PM PDT 24
Peak memory 197052 kb
Host smart-72dadd57-3d6a-4811-9d1d-5bf85c9ac465
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718204992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2718204992
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.2025271966
Short name T150
Test name
Test status
Simulation time 1137541495 ps
CPU time 3.06 seconds
Started Jul 14 05:22:29 PM PDT 24
Finished Jul 14 05:22:32 PM PDT 24
Peak memory 196496 kb
Host smart-cc54f5e8-2712-4b63-8d28-f066ab86a748
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025271966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.2025271966
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.351769157
Short name T460
Test name
Test status
Simulation time 129221127 ps
CPU time 1.02 seconds
Started Jul 14 05:22:30 PM PDT 24
Finished Jul 14 05:22:31 PM PDT 24
Peak memory 196552 kb
Host smart-e8fe99b2-34eb-4049-830a-c0e98666f767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351769157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.351769157
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1105064310
Short name T435
Test name
Test status
Simulation time 133837456 ps
CPU time 1.41 seconds
Started Jul 14 05:22:31 PM PDT 24
Finished Jul 14 05:22:33 PM PDT 24
Peak memory 197604 kb
Host smart-cc3866a3-c25d-4802-a302-96d4efd2a8c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105064310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1105064310
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2880090261
Short name T281
Test name
Test status
Simulation time 223777113 ps
CPU time 3.93 seconds
Started Jul 14 05:22:31 PM PDT 24
Finished Jul 14 05:22:35 PM PDT 24
Peak memory 198504 kb
Host smart-4e9efdeb-aaf4-4e0e-bec6-b7d3bbaca10f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880090261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2880090261
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.750945980
Short name T522
Test name
Test status
Simulation time 153510147 ps
CPU time 1.3 seconds
Started Jul 14 05:22:29 PM PDT 24
Finished Jul 14 05:22:31 PM PDT 24
Peak memory 196452 kb
Host smart-b34c07a4-fe41-4600-9d91-b5e272d24989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750945980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.750945980
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3258106811
Short name T328
Test name
Test status
Simulation time 40426645 ps
CPU time 1.27 seconds
Started Jul 14 05:22:28 PM PDT 24
Finished Jul 14 05:22:29 PM PDT 24
Peak memory 196948 kb
Host smart-117b893e-3fa5-4b15-95bf-012549b0b749
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258106811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3258106811
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3473741931
Short name T393
Test name
Test status
Simulation time 6735055481 ps
CPU time 174.98 seconds
Started Jul 14 05:22:34 PM PDT 24
Finished Jul 14 05:25:29 PM PDT 24
Peak memory 198668 kb
Host smart-832f5f01-3d71-4be4-915c-2b7bbc007bd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473741931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3473741931
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1130181326
Short name T642
Test name
Test status
Simulation time 43153221 ps
CPU time 0.58 seconds
Started Jul 14 05:17:59 PM PDT 24
Finished Jul 14 05:18:00 PM PDT 24
Peak memory 195236 kb
Host smart-8067f03c-4436-4661-9ab3-badae913f0c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130181326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1130181326
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1905625847
Short name T12
Test name
Test status
Simulation time 82261518 ps
CPU time 0.66 seconds
Started Jul 14 05:17:56 PM PDT 24
Finished Jul 14 05:17:57 PM PDT 24
Peak memory 195264 kb
Host smart-b418354b-a7fd-4023-a9cd-bb67f9807d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905625847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.1905625847
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2152993918
Short name T573
Test name
Test status
Simulation time 2410290757 ps
CPU time 16.78 seconds
Started Jul 14 05:17:57 PM PDT 24
Finished Jul 14 05:18:14 PM PDT 24
Peak memory 196252 kb
Host smart-0f116d71-ee64-4b28-b3c8-d167e4ae8289
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152993918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2152993918
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.183914293
Short name T589
Test name
Test status
Simulation time 1366330892 ps
CPU time 1.06 seconds
Started Jul 14 05:17:57 PM PDT 24
Finished Jul 14 05:17:59 PM PDT 24
Peak memory 198312 kb
Host smart-f00142f1-e21a-4652-b0df-e0b6b4401546
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183914293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.183914293
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1034678403
Short name T639
Test name
Test status
Simulation time 43446561 ps
CPU time 0.8 seconds
Started Jul 14 05:17:58 PM PDT 24
Finished Jul 14 05:17:59 PM PDT 24
Peak memory 196176 kb
Host smart-f0d4affb-07d1-4c4d-939e-00d6d8fe6655
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034678403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1034678403
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2152625748
Short name T489
Test name
Test status
Simulation time 453578777 ps
CPU time 2.82 seconds
Started Jul 14 05:17:59 PM PDT 24
Finished Jul 14 05:18:02 PM PDT 24
Peak memory 198676 kb
Host smart-3089718b-fef6-4818-9264-ec419e8bc733
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152625748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2152625748
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.1283474352
Short name T228
Test name
Test status
Simulation time 192599867 ps
CPU time 2.33 seconds
Started Jul 14 05:17:59 PM PDT 24
Finished Jul 14 05:18:02 PM PDT 24
Peak memory 196376 kb
Host smart-c060769b-c68c-4328-b2d8-1bd824bcee60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283474352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
1283474352
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2823699556
Short name T370
Test name
Test status
Simulation time 83348023 ps
CPU time 1.15 seconds
Started Jul 14 05:17:59 PM PDT 24
Finished Jul 14 05:18:00 PM PDT 24
Peak memory 196540 kb
Host smart-923dabde-d0b5-4026-b30a-963ffecba5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823699556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2823699556
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.2413454125
Short name T301
Test name
Test status
Simulation time 60635303 ps
CPU time 0.69 seconds
Started Jul 14 05:17:58 PM PDT 24
Finished Jul 14 05:17:59 PM PDT 24
Peak memory 194896 kb
Host smart-83c78ed6-d583-4737-9019-2dfde0e9efbd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413454125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.2413454125
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3029183062
Short name T234
Test name
Test status
Simulation time 310140145 ps
CPU time 3.82 seconds
Started Jul 14 05:18:02 PM PDT 24
Finished Jul 14 05:18:06 PM PDT 24
Peak memory 198504 kb
Host smart-478dab05-9062-473f-942b-2bb6bca4f22b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029183062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3029183062
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.3468923300
Short name T154
Test name
Test status
Simulation time 74261959 ps
CPU time 0.74 seconds
Started Jul 14 05:17:50 PM PDT 24
Finished Jul 14 05:17:51 PM PDT 24
Peak memory 194740 kb
Host smart-4ebb2999-c839-4db6-b5c8-1c9b2b0df06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468923300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.3468923300
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1809867471
Short name T60
Test name
Test status
Simulation time 42277964 ps
CPU time 1.17 seconds
Started Jul 14 05:17:53 PM PDT 24
Finished Jul 14 05:17:55 PM PDT 24
Peak memory 197156 kb
Host smart-c410d119-ed0a-4d4b-b470-f30a68d89047
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809867471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1809867471
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1568895876
Short name T591
Test name
Test status
Simulation time 7557130016 ps
CPU time 197.69 seconds
Started Jul 14 05:17:57 PM PDT 24
Finished Jul 14 05:21:15 PM PDT 24
Peak memory 198688 kb
Host smart-0750b285-372f-4d25-9336-73aaf9aefc9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568895876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1568895876
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.522563115
Short name T32
Test name
Test status
Simulation time 38315039 ps
CPU time 0.6 seconds
Started Jul 14 05:18:13 PM PDT 24
Finished Jul 14 05:18:14 PM PDT 24
Peak memory 194748 kb
Host smart-e9b44fff-ee29-48a2-9aa7-dfc5dc1adf99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522563115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.522563115
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.533874762
Short name T452
Test name
Test status
Simulation time 32644932 ps
CPU time 0.71 seconds
Started Jul 14 05:18:04 PM PDT 24
Finished Jul 14 05:18:05 PM PDT 24
Peak memory 194656 kb
Host smart-45f6d42f-4749-4cee-9c2a-90d1a9b43c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533874762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.533874762
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3216148903
Short name T674
Test name
Test status
Simulation time 339834556 ps
CPU time 16.93 seconds
Started Jul 14 05:18:03 PM PDT 24
Finished Jul 14 05:18:20 PM PDT 24
Peak memory 197640 kb
Host smart-36b6bce7-b32c-4f09-a429-2b0e718c25cc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216148903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3216148903
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2270993877
Short name T195
Test name
Test status
Simulation time 70288844 ps
CPU time 1.06 seconds
Started Jul 14 05:18:05 PM PDT 24
Finished Jul 14 05:18:06 PM PDT 24
Peak memory 197284 kb
Host smart-7bc56a0c-7eb8-457b-a6a5-1b50e4228d04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270993877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2270993877
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2793875802
Short name T290
Test name
Test status
Simulation time 32451005 ps
CPU time 1.05 seconds
Started Jul 14 05:18:04 PM PDT 24
Finished Jul 14 05:18:06 PM PDT 24
Peak memory 196792 kb
Host smart-6ef6a141-90b8-474f-999d-7632082814bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793875802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2793875802
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2569770293
Short name T447
Test name
Test status
Simulation time 212292955 ps
CPU time 2.51 seconds
Started Jul 14 05:18:04 PM PDT 24
Finished Jul 14 05:18:06 PM PDT 24
Peak memory 198448 kb
Host smart-6632be0a-0b1b-4806-a2a2-795ec6094220
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569770293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2569770293
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3181854772
Short name T513
Test name
Test status
Simulation time 442623821 ps
CPU time 3.11 seconds
Started Jul 14 05:18:06 PM PDT 24
Finished Jul 14 05:18:09 PM PDT 24
Peak memory 197648 kb
Host smart-7e12ea8c-2160-431e-a4e4-27fc1ada506d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181854772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3181854772
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.1112793078
Short name T253
Test name
Test status
Simulation time 58146808 ps
CPU time 1.27 seconds
Started Jul 14 05:17:56 PM PDT 24
Finished Jul 14 05:17:57 PM PDT 24
Peak memory 197828 kb
Host smart-8530b70a-ee0b-4229-9068-9fdc1c0a8c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112793078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1112793078
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.525150158
Short name T689
Test name
Test status
Simulation time 512430483 ps
CPU time 1.26 seconds
Started Jul 14 05:17:55 PM PDT 24
Finished Jul 14 05:17:57 PM PDT 24
Peak memory 197552 kb
Host smart-ef8c577e-60e4-4ee1-87e9-f7b0a165f958
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525150158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.525150158
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2063699048
Short name T209
Test name
Test status
Simulation time 525601090 ps
CPU time 3.17 seconds
Started Jul 14 05:18:07 PM PDT 24
Finished Jul 14 05:18:10 PM PDT 24
Peak memory 198528 kb
Host smart-8deb9215-2641-4a28-a866-b5b0134d8dd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063699048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.2063699048
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1151658743
Short name T638
Test name
Test status
Simulation time 187376231 ps
CPU time 1.06 seconds
Started Jul 14 05:17:56 PM PDT 24
Finished Jul 14 05:17:57 PM PDT 24
Peak memory 196232 kb
Host smart-18ea1f2e-3c62-46be-ba67-17ae76555646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151658743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1151658743
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.4266270339
Short name T645
Test name
Test status
Simulation time 65867970 ps
CPU time 0.85 seconds
Started Jul 14 05:18:01 PM PDT 24
Finished Jul 14 05:18:03 PM PDT 24
Peak memory 196436 kb
Host smart-8cc91390-8d3b-4329-8971-90038f21205b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266270339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.4266270339
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.4048753722
Short name T561
Test name
Test status
Simulation time 5190376967 ps
CPU time 133.63 seconds
Started Jul 14 05:18:03 PM PDT 24
Finished Jul 14 05:20:16 PM PDT 24
Peak memory 198616 kb
Host smart-1dbb0328-4959-42ca-974d-1697b803d2f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048753722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.4048753722
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.1462672152
Short name T53
Test name
Test status
Simulation time 277051293532 ps
CPU time 889.51 seconds
Started Jul 14 05:18:13 PM PDT 24
Finished Jul 14 05:33:04 PM PDT 24
Peak memory 198792 kb
Host smart-77052746-03a0-4bdc-a1ff-125415213a40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1462672152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.1462672152
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.275891912
Short name T186
Test name
Test status
Simulation time 31506356 ps
CPU time 0.58 seconds
Started Jul 14 05:18:16 PM PDT 24
Finished Jul 14 05:18:17 PM PDT 24
Peak memory 194540 kb
Host smart-de5d9c0a-7c44-4661-a380-0cefff5c329f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275891912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.275891912
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3996896649
Short name T387
Test name
Test status
Simulation time 171485283 ps
CPU time 0.94 seconds
Started Jul 14 05:18:12 PM PDT 24
Finished Jul 14 05:18:13 PM PDT 24
Peak memory 197160 kb
Host smart-f3dcd860-bad7-4dd1-aa60-69e24cf28e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996896649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3996896649
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.3168757102
Short name T200
Test name
Test status
Simulation time 162654844 ps
CPU time 4.52 seconds
Started Jul 14 05:18:13 PM PDT 24
Finished Jul 14 05:18:18 PM PDT 24
Peak memory 196524 kb
Host smart-070825a7-0f5d-466c-95cf-2b05b1295f2a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168757102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.3168757102
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.2992388613
Short name T181
Test name
Test status
Simulation time 268219387 ps
CPU time 0.98 seconds
Started Jul 14 05:18:14 PM PDT 24
Finished Jul 14 05:18:15 PM PDT 24
Peak memory 197388 kb
Host smart-5ea46dec-f41f-4749-8f0f-2cbd65d2090c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992388613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.2992388613
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2560385928
Short name T309
Test name
Test status
Simulation time 422496172 ps
CPU time 1.64 seconds
Started Jul 14 05:18:10 PM PDT 24
Finished Jul 14 05:18:13 PM PDT 24
Peak memory 197724 kb
Host smart-523c1a8d-5daa-4a93-8963-93bb14915574
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560385928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2560385928
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2892468950
Short name T560
Test name
Test status
Simulation time 153227727 ps
CPU time 1.69 seconds
Started Jul 14 05:18:14 PM PDT 24
Finished Jul 14 05:18:17 PM PDT 24
Peak memory 197216 kb
Host smart-ccf47663-e68a-42c6-b2c0-b3ec623bceae
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892468950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2892468950
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.4051705774
Short name T462
Test name
Test status
Simulation time 51665003 ps
CPU time 1.3 seconds
Started Jul 14 05:18:10 PM PDT 24
Finished Jul 14 05:18:12 PM PDT 24
Peak memory 196224 kb
Host smart-966b5c7b-f0c1-4007-a0fd-40f5c753a3a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051705774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
4051705774
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1643266275
Short name T174
Test name
Test status
Simulation time 86025551 ps
CPU time 0.82 seconds
Started Jul 14 05:18:13 PM PDT 24
Finished Jul 14 05:18:14 PM PDT 24
Peak memory 196044 kb
Host smart-61b7da5c-7bec-4dd7-abee-821ce8ac989f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643266275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1643266275
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3899406119
Short name T417
Test name
Test status
Simulation time 33364066 ps
CPU time 0.65 seconds
Started Jul 14 05:18:13 PM PDT 24
Finished Jul 14 05:18:14 PM PDT 24
Peak memory 194868 kb
Host smart-a8c2b697-01bb-4fe2-a3f6-b50adc16363c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899406119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3899406119
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1185548425
Short name T120
Test name
Test status
Simulation time 423781326 ps
CPU time 2.41 seconds
Started Jul 14 05:18:13 PM PDT 24
Finished Jul 14 05:18:16 PM PDT 24
Peak memory 198528 kb
Host smart-9b37ffd3-d667-480b-b7de-91fc7cedffc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185548425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.1185548425
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.2661206141
Short name T603
Test name
Test status
Simulation time 220741621 ps
CPU time 1.3 seconds
Started Jul 14 05:18:14 PM PDT 24
Finished Jul 14 05:18:16 PM PDT 24
Peak memory 198556 kb
Host smart-f7ca06fe-b5b4-46d5-a82d-f7e8a8495921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661206141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2661206141
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.1441931401
Short name T512
Test name
Test status
Simulation time 188447855 ps
CPU time 1.56 seconds
Started Jul 14 05:18:11 PM PDT 24
Finished Jul 14 05:18:13 PM PDT 24
Peak memory 197420 kb
Host smart-faf2aad1-944d-4ad5-84ed-5c85d2d16df1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441931401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1441931401
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.3029217446
Short name T563
Test name
Test status
Simulation time 2839389609 ps
CPU time 86.67 seconds
Started Jul 14 05:18:11 PM PDT 24
Finished Jul 14 05:19:38 PM PDT 24
Peak memory 198612 kb
Host smart-df15e64f-6d0e-4870-9890-cf390817da84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029217446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.3029217446
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.3685229759
Short name T349
Test name
Test status
Simulation time 15620752 ps
CPU time 0.57 seconds
Started Jul 14 05:18:25 PM PDT 24
Finished Jul 14 05:18:26 PM PDT 24
Peak memory 194856 kb
Host smart-8ac4e9fa-da34-4137-9495-0549d479836e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685229759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.3685229759
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.4258190833
Short name T529
Test name
Test status
Simulation time 141187294 ps
CPU time 0.88 seconds
Started Jul 14 05:18:21 PM PDT 24
Finished Jul 14 05:18:22 PM PDT 24
Peak memory 197052 kb
Host smart-af9ebd72-214e-4876-b655-4545a6170643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258190833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.4258190833
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.983439238
Short name T697
Test name
Test status
Simulation time 10890452588 ps
CPU time 27.32 seconds
Started Jul 14 05:18:26 PM PDT 24
Finished Jul 14 05:18:55 PM PDT 24
Peak memory 197160 kb
Host smart-7074a754-83ee-43f1-87ea-b0448bfe5bb9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983439238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress
.983439238
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1735278041
Short name T22
Test name
Test status
Simulation time 49891339 ps
CPU time 0.82 seconds
Started Jul 14 05:18:25 PM PDT 24
Finished Jul 14 05:18:26 PM PDT 24
Peak memory 197452 kb
Host smart-9a454db2-09a3-455c-b520-040afb5c8679
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735278041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1735278041
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1673034196
Short name T278
Test name
Test status
Simulation time 84333150 ps
CPU time 1.45 seconds
Started Jul 14 05:18:20 PM PDT 24
Finished Jul 14 05:18:21 PM PDT 24
Peak memory 196388 kb
Host smart-fedf451e-8bb3-4721-97e4-a7d4fd78bd2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673034196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1673034196
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.768460451
Short name T685
Test name
Test status
Simulation time 74037349 ps
CPU time 3.34 seconds
Started Jul 14 05:18:26 PM PDT 24
Finished Jul 14 05:18:30 PM PDT 24
Peak memory 198600 kb
Host smart-9448ec2d-3165-40cd-af61-1bf5186f95b6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768460451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.768460451
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.32769610
Short name T531
Test name
Test status
Simulation time 221025295 ps
CPU time 1.84 seconds
Started Jul 14 05:18:19 PM PDT 24
Finished Jul 14 05:18:21 PM PDT 24
Peak memory 196572 kb
Host smart-2e9e37b3-e2c2-46b5-8763-fe33b477008b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32769610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.32769610
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.773942220
Short name T586
Test name
Test status
Simulation time 74219391 ps
CPU time 0.8 seconds
Started Jul 14 05:18:19 PM PDT 24
Finished Jul 14 05:18:20 PM PDT 24
Peak memory 196000 kb
Host smart-3b13627e-1073-419d-9f99-54ee91881f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773942220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.773942220
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2065229578
Short name T274
Test name
Test status
Simulation time 35534374 ps
CPU time 1.26 seconds
Started Jul 14 05:18:17 PM PDT 24
Finished Jul 14 05:18:18 PM PDT 24
Peak memory 197124 kb
Host smart-c36d0183-a5cb-489e-a568-1b50d4b3c8f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065229578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.2065229578
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2627782592
Short name T300
Test name
Test status
Simulation time 1519983069 ps
CPU time 2.61 seconds
Started Jul 14 05:18:25 PM PDT 24
Finished Jul 14 05:18:28 PM PDT 24
Peak memory 198520 kb
Host smart-2e8e1734-4469-4c58-ba88-9c3f441dc42c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627782592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2627782592
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.880870480
Short name T554
Test name
Test status
Simulation time 80001225 ps
CPU time 0.97 seconds
Started Jul 14 05:18:18 PM PDT 24
Finished Jul 14 05:18:19 PM PDT 24
Peak memory 197104 kb
Host smart-059b298f-52e5-4cb4-90cd-37c304f43b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880870480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.880870480
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1052355797
Short name T343
Test name
Test status
Simulation time 397817401 ps
CPU time 0.97 seconds
Started Jul 14 05:18:17 PM PDT 24
Finished Jul 14 05:18:18 PM PDT 24
Peak memory 197472 kb
Host smart-9a441c41-ac80-4b76-9fa4-a25e036cac91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052355797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1052355797
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1324436185
Short name T655
Test name
Test status
Simulation time 26397918004 ps
CPU time 82.65 seconds
Started Jul 14 05:18:24 PM PDT 24
Finished Jul 14 05:19:47 PM PDT 24
Peak memory 198628 kb
Host smart-43265af0-8f25-4fb6-8abc-42edfe91c5d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324436185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1324436185
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.4052372638
Short name T33
Test name
Test status
Simulation time 46676118 ps
CPU time 0.56 seconds
Started Jul 14 05:18:31 PM PDT 24
Finished Jul 14 05:18:32 PM PDT 24
Peak memory 194824 kb
Host smart-0400a86d-7dd8-4fad-84b8-7c9b9769cefa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052372638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.4052372638
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.599901446
Short name T194
Test name
Test status
Simulation time 119767852 ps
CPU time 0.79 seconds
Started Jul 14 05:18:26 PM PDT 24
Finished Jul 14 05:18:27 PM PDT 24
Peak memory 195836 kb
Host smart-e6360e78-35d8-4e58-9b51-e367caf26e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599901446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.599901446
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.4268640841
Short name T166
Test name
Test status
Simulation time 279887955 ps
CPU time 15.2 seconds
Started Jul 14 05:18:32 PM PDT 24
Finished Jul 14 05:18:48 PM PDT 24
Peak memory 197484 kb
Host smart-e17c4d37-d63d-4c17-a001-7e4d460a5076
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268640841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.4268640841
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.1669864973
Short name T215
Test name
Test status
Simulation time 218290063 ps
CPU time 0.7 seconds
Started Jul 14 05:18:32 PM PDT 24
Finished Jul 14 05:18:33 PM PDT 24
Peak memory 195060 kb
Host smart-f68c9654-4cdc-472b-b075-99d8ce77682f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669864973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.1669864973
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3251847878
Short name T481
Test name
Test status
Simulation time 157409525 ps
CPU time 0.92 seconds
Started Jul 14 05:18:26 PM PDT 24
Finished Jul 14 05:18:28 PM PDT 24
Peak memory 196140 kb
Host smart-de8edaf3-2c5a-4167-a1c4-54d59c194d36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251847878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3251847878
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2576130412
Short name T145
Test name
Test status
Simulation time 184809750 ps
CPU time 3.19 seconds
Started Jul 14 05:18:35 PM PDT 24
Finished Jul 14 05:18:38 PM PDT 24
Peak memory 198704 kb
Host smart-7eb09842-a58e-4278-84fd-8f11193bbf22
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576130412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2576130412
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.917352926
Short name T373
Test name
Test status
Simulation time 167594365 ps
CPU time 3.49 seconds
Started Jul 14 05:18:25 PM PDT 24
Finished Jul 14 05:18:29 PM PDT 24
Peak memory 198584 kb
Host smart-ce2b123c-a1a8-4847-a5c3-bec7c5096b45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917352926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.917352926
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1825243746
Short name T231
Test name
Test status
Simulation time 73442844 ps
CPU time 1.39 seconds
Started Jul 14 05:18:26 PM PDT 24
Finished Jul 14 05:18:28 PM PDT 24
Peak memory 198648 kb
Host smart-dcad7cb2-bb3b-414c-85d3-ce20ace70c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825243746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1825243746
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.67161664
Short name T672
Test name
Test status
Simulation time 154877284 ps
CPU time 1.07 seconds
Started Jul 14 05:18:25 PM PDT 24
Finished Jul 14 05:18:26 PM PDT 24
Peak memory 196412 kb
Host smart-6dfe2d6f-5c76-43ec-95c5-94f64c9fbdcf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67161664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_p
ulldown.67161664
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1859528295
Short name T230
Test name
Test status
Simulation time 228335221 ps
CPU time 3.17 seconds
Started Jul 14 05:18:33 PM PDT 24
Finished Jul 14 05:18:37 PM PDT 24
Peak memory 198500 kb
Host smart-c7af858e-14ad-4752-88df-07c2bf46f6c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859528295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1859528295
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.3411111406
Short name T647
Test name
Test status
Simulation time 90259893 ps
CPU time 1.01 seconds
Started Jul 14 05:18:26 PM PDT 24
Finished Jul 14 05:18:28 PM PDT 24
Peak memory 197832 kb
Host smart-ae8d40ad-9d08-4a78-b292-ca9ba4ace286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411111406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3411111406
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2336870260
Short name T626
Test name
Test status
Simulation time 129668629 ps
CPU time 1.24 seconds
Started Jul 14 05:18:26 PM PDT 24
Finished Jul 14 05:18:28 PM PDT 24
Peak memory 197132 kb
Host smart-2641122b-0116-4240-8b8f-c9b6dbebb413
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336870260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2336870260
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.1304759958
Short name T580
Test name
Test status
Simulation time 2091743016 ps
CPU time 60.92 seconds
Started Jul 14 05:18:31 PM PDT 24
Finished Jul 14 05:19:33 PM PDT 24
Peak memory 198512 kb
Host smart-ec762628-e5ae-4e51-96f2-2bf045c1ff74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304759958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.1304759958
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.407388056
Short name T858
Test name
Test status
Simulation time 161816842 ps
CPU time 1.38 seconds
Started Jul 14 04:22:07 PM PDT 24
Finished Jul 14 04:22:09 PM PDT 24
Peak memory 198280 kb
Host smart-c2ed7484-885e-4fb9-9803-7e089b883578
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=407388056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.407388056
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3701475164
Short name T939
Test name
Test status
Simulation time 78784876 ps
CPU time 1.28 seconds
Started Jul 14 04:23:01 PM PDT 24
Finished Jul 14 04:23:04 PM PDT 24
Peak memory 195848 kb
Host smart-c7f3668c-b941-45f8-b4ae-d2a6fc7153e8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701475164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3701475164
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2121065395
Short name T931
Test name
Test status
Simulation time 68384165 ps
CPU time 1.11 seconds
Started Jul 14 04:18:46 PM PDT 24
Finished Jul 14 04:18:48 PM PDT 24
Peak memory 197232 kb
Host smart-382cb5d0-4886-4d33-935f-94b299974d41
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2121065395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.2121065395
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2836387223
Short name T881
Test name
Test status
Simulation time 151090257 ps
CPU time 0.86 seconds
Started Jul 14 04:21:11 PM PDT 24
Finished Jul 14 04:21:12 PM PDT 24
Peak memory 198072 kb
Host smart-bfe36b1a-2e59-49c6-86ff-d79a48b2a670
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836387223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2836387223
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.107127054
Short name T882
Test name
Test status
Simulation time 395381019 ps
CPU time 1.37 seconds
Started Jul 14 04:22:40 PM PDT 24
Finished Jul 14 04:22:43 PM PDT 24
Peak memory 196928 kb
Host smart-493be90a-6b57-4dc8-a618-5cd4798144a0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=107127054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.107127054
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3427498879
Short name T891
Test name
Test status
Simulation time 142043870 ps
CPU time 1.3 seconds
Started Jul 14 04:22:31 PM PDT 24
Finished Jul 14 04:22:35 PM PDT 24
Peak memory 195952 kb
Host smart-1df13cd1-7bd7-4b53-ba94-7446985f4140
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427498879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3427498879
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1210699147
Short name T846
Test name
Test status
Simulation time 224439869 ps
CPU time 1.17 seconds
Started Jul 14 04:22:27 PM PDT 24
Finished Jul 14 04:22:31 PM PDT 24
Peak memory 196432 kb
Host smart-cba25d71-1eb9-46a2-8603-e9c254810e48
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1210699147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1210699147
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.459513491
Short name T860
Test name
Test status
Simulation time 153915362 ps
CPU time 1.11 seconds
Started Jul 14 04:22:17 PM PDT 24
Finished Jul 14 04:22:19 PM PDT 24
Peak memory 195360 kb
Host smart-30f23d4b-54fb-4003-ab8f-2e66dc49cb35
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459513491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.459513491
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1700759220
Short name T847
Test name
Test status
Simulation time 207027324 ps
CPU time 1.32 seconds
Started Jul 14 04:22:40 PM PDT 24
Finished Jul 14 04:22:43 PM PDT 24
Peak memory 196832 kb
Host smart-53c609a9-6093-4b60-bc6e-3b56855ac03d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1700759220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1700759220
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.426768717
Short name T863
Test name
Test status
Simulation time 138293078 ps
CPU time 1.26 seconds
Started Jul 14 04:18:16 PM PDT 24
Finished Jul 14 04:18:17 PM PDT 24
Peak memory 195888 kb
Host smart-a253cc5f-7926-4847-81eb-96dc5fa5d015
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426768717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.426768717
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2460591594
Short name T854
Test name
Test status
Simulation time 225662616 ps
CPU time 0.73 seconds
Started Jul 14 04:22:18 PM PDT 24
Finished Jul 14 04:22:20 PM PDT 24
Peak memory 195416 kb
Host smart-01f6d559-1c17-4797-860f-339dd624283d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2460591594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2460591594
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.725647916
Short name T920
Test name
Test status
Simulation time 140822030 ps
CPU time 0.81 seconds
Started Jul 14 04:22:18 PM PDT 24
Finished Jul 14 04:22:20 PM PDT 24
Peak memory 195340 kb
Host smart-c9e3c8ac-e55a-4e32-9e3c-9ab07feb050f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725647916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.725647916
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3861161231
Short name T884
Test name
Test status
Simulation time 76277204 ps
CPU time 1.03 seconds
Started Jul 14 04:20:21 PM PDT 24
Finished Jul 14 04:20:22 PM PDT 24
Peak memory 196652 kb
Host smart-1119a6c6-58b0-459c-9d04-f9aa952e19f4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3861161231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3861161231
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.130594174
Short name T928
Test name
Test status
Simulation time 165983015 ps
CPU time 0.97 seconds
Started Jul 14 04:21:53 PM PDT 24
Finished Jul 14 04:21:56 PM PDT 24
Peak memory 197372 kb
Host smart-04270ffd-c5e7-42e0-8d4d-81b1f7c363d0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130594174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.130594174
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.548195719
Short name T927
Test name
Test status
Simulation time 170714113 ps
CPU time 0.98 seconds
Started Jul 14 04:17:55 PM PDT 24
Finished Jul 14 04:17:57 PM PDT 24
Peak memory 195964 kb
Host smart-01e62e02-92cc-4ddc-b731-eab9268a6e41
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=548195719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.548195719
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.762991786
Short name T914
Test name
Test status
Simulation time 68731450 ps
CPU time 0.76 seconds
Started Jul 14 04:18:51 PM PDT 24
Finished Jul 14 04:18:52 PM PDT 24
Peak memory 196376 kb
Host smart-c3333b59-67df-47ab-bc96-388afeab448e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762991786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.762991786
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2455366946
Short name T922
Test name
Test status
Simulation time 123590639 ps
CPU time 1.14 seconds
Started Jul 14 04:22:33 PM PDT 24
Finished Jul 14 04:22:36 PM PDT 24
Peak memory 196152 kb
Host smart-4af59239-845c-406c-8a2f-12299c516e15
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2455366946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2455366946
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1741848411
Short name T870
Test name
Test status
Simulation time 77934860 ps
CPU time 0.85 seconds
Started Jul 14 04:18:06 PM PDT 24
Finished Jul 14 04:18:08 PM PDT 24
Peak memory 195472 kb
Host smart-21910db4-cb6c-4e32-865c-1fd01335c56d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741848411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1741848411
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1084797053
Short name T875
Test name
Test status
Simulation time 185588382 ps
CPU time 1.39 seconds
Started Jul 14 04:17:48 PM PDT 24
Finished Jul 14 04:17:50 PM PDT 24
Peak memory 197132 kb
Host smart-b45e0ea9-be6d-41e1-9656-670d589b59b0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1084797053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1084797053
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3104741337
Short name T840
Test name
Test status
Simulation time 105051581 ps
CPU time 1.4 seconds
Started Jul 14 04:22:45 PM PDT 24
Finished Jul 14 04:22:49 PM PDT 24
Peak memory 195584 kb
Host smart-1e61e150-49e8-4b6a-8e08-202c131e9ce1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104741337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3104741337
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2314629802
Short name T895
Test name
Test status
Simulation time 48960781 ps
CPU time 0.96 seconds
Started Jul 14 04:17:28 PM PDT 24
Finished Jul 14 04:17:30 PM PDT 24
Peak memory 195604 kb
Host smart-b47e1c2b-c438-400a-a254-f697c643a69f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2314629802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2314629802
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1851057196
Short name T842
Test name
Test status
Simulation time 42188583 ps
CPU time 0.86 seconds
Started Jul 14 04:18:03 PM PDT 24
Finished Jul 14 04:18:05 PM PDT 24
Peak memory 197668 kb
Host smart-e06dfe72-9a81-402f-9fd4-8b0a9c44973a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851057196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1851057196
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.670061683
Short name T892
Test name
Test status
Simulation time 39274896 ps
CPU time 1.04 seconds
Started Jul 14 04:22:46 PM PDT 24
Finished Jul 14 04:22:48 PM PDT 24
Peak memory 196896 kb
Host smart-4130ae7a-c455-4013-ba5f-42326f4d75bf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=670061683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.670061683
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1070166598
Short name T902
Test name
Test status
Simulation time 130652978 ps
CPU time 1.04 seconds
Started Jul 14 04:21:53 PM PDT 24
Finished Jul 14 04:21:57 PM PDT 24
Peak memory 195840 kb
Host smart-34de4918-fdf0-44b4-aa8c-31d40b32d4f6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070166598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1070166598
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2896731566
Short name T848
Test name
Test status
Simulation time 47958920 ps
CPU time 1.19 seconds
Started Jul 14 04:23:16 PM PDT 24
Finished Jul 14 04:23:18 PM PDT 24
Peak memory 195972 kb
Host smart-6748c714-d72c-4f43-9400-eb6d24bf0769
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2896731566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2896731566
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1399647349
Short name T905
Test name
Test status
Simulation time 225606803 ps
CPU time 1.18 seconds
Started Jul 14 04:20:57 PM PDT 24
Finished Jul 14 04:20:58 PM PDT 24
Peak memory 195932 kb
Host smart-c5c7add6-f525-4763-ba80-708442c5d9d6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399647349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1399647349
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.559246456
Short name T888
Test name
Test status
Simulation time 65153226 ps
CPU time 1.05 seconds
Started Jul 14 04:23:23 PM PDT 24
Finished Jul 14 04:23:25 PM PDT 24
Peak memory 198308 kb
Host smart-b47547d2-be5c-4d8a-a18b-86c1d73b304b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=559246456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.559246456
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.623160063
Short name T896
Test name
Test status
Simulation time 74650700 ps
CPU time 1.29 seconds
Started Jul 14 04:23:13 PM PDT 24
Finished Jul 14 04:23:16 PM PDT 24
Peak memory 196808 kb
Host smart-7c83ad83-8e3f-40ba-be9f-5472029f2426
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623160063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.623160063
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3369276537
Short name T886
Test name
Test status
Simulation time 147444219 ps
CPU time 0.89 seconds
Started Jul 14 04:23:21 PM PDT 24
Finished Jul 14 04:23:23 PM PDT 24
Peak memory 195548 kb
Host smart-ef72568b-469c-4033-bb3d-ad801b238c58
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3369276537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.3369276537
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3972678592
Short name T867
Test name
Test status
Simulation time 53147125 ps
CPU time 1.1 seconds
Started Jul 14 04:23:15 PM PDT 24
Finished Jul 14 04:23:17 PM PDT 24
Peak memory 198048 kb
Host smart-94983991-462e-4a5b-871b-e9ddfef172d8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972678592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3972678592
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.783573745
Short name T890
Test name
Test status
Simulation time 28916089 ps
CPU time 0.82 seconds
Started Jul 14 04:23:19 PM PDT 24
Finished Jul 14 04:23:22 PM PDT 24
Peak memory 196412 kb
Host smart-96b1bc3f-c550-4919-851e-61f35b1d2f72
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=783573745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.783573745
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3670216402
Short name T861
Test name
Test status
Simulation time 129533338 ps
CPU time 0.82 seconds
Started Jul 14 04:23:18 PM PDT 24
Finished Jul 14 04:23:20 PM PDT 24
Peak memory 196824 kb
Host smart-efde07c7-1478-4aec-804b-00b37d820816
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670216402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3670216402
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.974765455
Short name T899
Test name
Test status
Simulation time 914262222 ps
CPU time 1.36 seconds
Started Jul 14 04:23:08 PM PDT 24
Finished Jul 14 04:23:10 PM PDT 24
Peak memory 196820 kb
Host smart-ea1e67a9-faf7-4011-ae45-1eb7ad7a6870
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=974765455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.974765455
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3879748117
Short name T894
Test name
Test status
Simulation time 57854263 ps
CPU time 1.08 seconds
Started Jul 14 04:23:22 PM PDT 24
Finished Jul 14 04:23:25 PM PDT 24
Peak memory 196880 kb
Host smart-16d06e7e-fa2f-4bbb-978d-4379cf20ab83
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879748117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3879748117
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2901808900
Short name T869
Test name
Test status
Simulation time 104832379 ps
CPU time 1.17 seconds
Started Jul 14 04:23:13 PM PDT 24
Finished Jul 14 04:23:15 PM PDT 24
Peak memory 196696 kb
Host smart-78a50ef4-4987-4960-a393-157913f632e3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2901808900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2901808900
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1760922813
Short name T878
Test name
Test status
Simulation time 680240333 ps
CPU time 1 seconds
Started Jul 14 04:23:17 PM PDT 24
Finished Jul 14 04:23:19 PM PDT 24
Peak memory 196724 kb
Host smart-4b910181-a84d-44c2-a147-5eeccc5bb6a5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760922813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1760922813
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1996071398
Short name T936
Test name
Test status
Simulation time 310354081 ps
CPU time 1.36 seconds
Started Jul 14 04:23:13 PM PDT 24
Finished Jul 14 04:23:16 PM PDT 24
Peak memory 198284 kb
Host smart-074c9ba0-2efe-4ca5-8935-2eab1814da00
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1996071398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1996071398
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3304973592
Short name T864
Test name
Test status
Simulation time 266040379 ps
CPU time 1.44 seconds
Started Jul 14 04:23:13 PM PDT 24
Finished Jul 14 04:23:16 PM PDT 24
Peak memory 196904 kb
Host smart-9ef139d6-75c3-47d1-a071-8468adc17e11
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304973592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3304973592
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1752491447
Short name T926
Test name
Test status
Simulation time 88082638 ps
CPU time 1.33 seconds
Started Jul 14 04:23:18 PM PDT 24
Finished Jul 14 04:23:21 PM PDT 24
Peak memory 197068 kb
Host smart-0e5ad480-01a3-42c4-9074-537084606607
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1752491447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1752491447
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2198172861
Short name T906
Test name
Test status
Simulation time 226184724 ps
CPU time 0.89 seconds
Started Jul 14 04:23:23 PM PDT 24
Finished Jul 14 04:23:25 PM PDT 24
Peak memory 196804 kb
Host smart-01176d53-ee2f-496f-91fd-930f544d865c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198172861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2198172861
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.507042446
Short name T921
Test name
Test status
Simulation time 95135794 ps
CPU time 0.86 seconds
Started Jul 14 04:23:17 PM PDT 24
Finished Jul 14 04:23:20 PM PDT 24
Peak memory 196652 kb
Host smart-83b45373-f706-44d7-b38e-486c634cae92
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=507042446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.507042446
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3598776332
Short name T885
Test name
Test status
Simulation time 125468856 ps
CPU time 1.22 seconds
Started Jul 14 04:23:23 PM PDT 24
Finished Jul 14 04:23:25 PM PDT 24
Peak memory 198316 kb
Host smart-ad996160-f959-407d-b72b-cb450aa41bd6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598776332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3598776332
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3388918174
Short name T862
Test name
Test status
Simulation time 525858320 ps
CPU time 1.17 seconds
Started Jul 14 04:23:12 PM PDT 24
Finished Jul 14 04:23:14 PM PDT 24
Peak memory 196204 kb
Host smart-a982fbe9-6ecd-4325-b4e8-456d75c399db
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3388918174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3388918174
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.903547884
Short name T844
Test name
Test status
Simulation time 101485510 ps
CPU time 1.29 seconds
Started Jul 14 04:23:18 PM PDT 24
Finished Jul 14 04:23:20 PM PDT 24
Peak memory 197048 kb
Host smart-98d1ed6b-cff2-4a27-85d6-8ccda7d977e8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903547884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.903547884
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1441647048
Short name T871
Test name
Test status
Simulation time 197053073 ps
CPU time 0.93 seconds
Started Jul 14 04:23:20 PM PDT 24
Finished Jul 14 04:23:22 PM PDT 24
Peak memory 196860 kb
Host smart-26e48d73-583c-4754-9ab8-c8a0d53ff989
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1441647048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1441647048
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.904367519
Short name T910
Test name
Test status
Simulation time 123741577 ps
CPU time 1.19 seconds
Started Jul 14 04:23:13 PM PDT 24
Finished Jul 14 04:23:16 PM PDT 24
Peak memory 198184 kb
Host smart-543fcea8-cdd5-43b2-b207-3810f4395a84
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904367519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.904367519
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.217778769
Short name T913
Test name
Test status
Simulation time 311091615 ps
CPU time 1.26 seconds
Started Jul 14 04:18:36 PM PDT 24
Finished Jul 14 04:18:38 PM PDT 24
Peak memory 196720 kb
Host smart-7a6dda35-055f-4d64-9e9c-5d531e0b7eac
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=217778769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.217778769
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3491847861
Short name T841
Test name
Test status
Simulation time 60245724 ps
CPU time 1.02 seconds
Started Jul 14 04:22:25 PM PDT 24
Finished Jul 14 04:22:27 PM PDT 24
Peak memory 196148 kb
Host smart-7908aa25-8931-4e18-836b-91b8ba2bd4b6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491847861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3491847861
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.4185791047
Short name T874
Test name
Test status
Simulation time 29297250 ps
CPU time 0.84 seconds
Started Jul 14 04:23:13 PM PDT 24
Finished Jul 14 04:23:14 PM PDT 24
Peak memory 197592 kb
Host smart-2fdac82e-36fa-4fb0-b05f-312c2d49f2ec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4185791047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.4185791047
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1170470851
Short name T937
Test name
Test status
Simulation time 31948294 ps
CPU time 0.78 seconds
Started Jul 14 04:23:13 PM PDT 24
Finished Jul 14 04:23:15 PM PDT 24
Peak memory 196368 kb
Host smart-bf85ac3c-7aad-4700-bb89-6cb5b5259a7a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170470851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1170470851
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2876774996
Short name T893
Test name
Test status
Simulation time 87681370 ps
CPU time 1.18 seconds
Started Jul 14 04:23:21 PM PDT 24
Finished Jul 14 04:23:23 PM PDT 24
Peak memory 195932 kb
Host smart-a690328b-0f0e-43a5-afd5-405b9a26ffe3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2876774996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2876774996
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3501276137
Short name T919
Test name
Test status
Simulation time 379565054 ps
CPU time 0.85 seconds
Started Jul 14 04:23:15 PM PDT 24
Finished Jul 14 04:23:17 PM PDT 24
Peak memory 196636 kb
Host smart-911f6f5f-f76f-4b09-8dbf-8a47ac5f0a05
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501276137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3501276137
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.156711044
Short name T859
Test name
Test status
Simulation time 158625066 ps
CPU time 0.93 seconds
Started Jul 14 04:23:13 PM PDT 24
Finished Jul 14 04:23:15 PM PDT 24
Peak memory 195544 kb
Host smart-8b2d68b7-e2b4-4316-a7f9-05ca03b379a4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=156711044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.156711044
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2584925317
Short name T935
Test name
Test status
Simulation time 299012436 ps
CPU time 1 seconds
Started Jul 14 04:23:13 PM PDT 24
Finished Jul 14 04:23:16 PM PDT 24
Peak memory 196892 kb
Host smart-f2746069-7a25-4900-a3ff-6ab81f6a5150
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584925317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2584925317
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2486452224
Short name T917
Test name
Test status
Simulation time 30159036 ps
CPU time 0.9 seconds
Started Jul 14 04:23:21 PM PDT 24
Finished Jul 14 04:23:23 PM PDT 24
Peak memory 196504 kb
Host smart-a901672d-7907-4df9-bed8-68f3c2d85bd4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2486452224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2486452224
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1887517192
Short name T849
Test name
Test status
Simulation time 37350144 ps
CPU time 1.09 seconds
Started Jul 14 04:23:22 PM PDT 24
Finished Jul 14 04:23:25 PM PDT 24
Peak memory 196204 kb
Host smart-0979917d-dd62-4812-b10b-83de673a45b0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887517192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1887517192
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.756338345
Short name T903
Test name
Test status
Simulation time 156790957 ps
CPU time 1.42 seconds
Started Jul 14 04:23:26 PM PDT 24
Finished Jul 14 04:23:28 PM PDT 24
Peak memory 198244 kb
Host smart-285535d8-5d50-4924-917a-7656078791c7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=756338345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.756338345
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.530211114
Short name T933
Test name
Test status
Simulation time 236718290 ps
CPU time 1.15 seconds
Started Jul 14 04:23:27 PM PDT 24
Finished Jul 14 04:23:29 PM PDT 24
Peak memory 191940 kb
Host smart-c7f336f7-ee00-4dcc-a5a2-b6cb58bcb051
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530211114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.530211114
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2559083531
Short name T853
Test name
Test status
Simulation time 398775664 ps
CPU time 1.38 seconds
Started Jul 14 04:23:27 PM PDT 24
Finished Jul 14 04:23:29 PM PDT 24
Peak memory 198328 kb
Host smart-a15a86b4-1e03-425a-ad32-9d23e072d07a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2559083531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.2559083531
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2997649456
Short name T845
Test name
Test status
Simulation time 65904873 ps
CPU time 1.11 seconds
Started Jul 14 04:23:22 PM PDT 24
Finished Jul 14 04:23:25 PM PDT 24
Peak memory 196720 kb
Host smart-aacc5d4f-273c-4a9f-a4d2-f53d796115f3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997649456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2997649456
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2288698618
Short name T855
Test name
Test status
Simulation time 70503274 ps
CPU time 1.13 seconds
Started Jul 14 04:23:28 PM PDT 24
Finished Jul 14 04:23:31 PM PDT 24
Peak memory 196424 kb
Host smart-fed5af64-c9bd-4f7b-8c77-f46f83a0384a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2288698618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2288698618
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4119964985
Short name T923
Test name
Test status
Simulation time 307752116 ps
CPU time 1.23 seconds
Started Jul 14 04:23:21 PM PDT 24
Finished Jul 14 04:23:24 PM PDT 24
Peak memory 198276 kb
Host smart-6a0d46a3-80a1-4845-bfb8-b6efbe4f8f7f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119964985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4119964985
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3259207755
Short name T850
Test name
Test status
Simulation time 190527780 ps
CPU time 1.2 seconds
Started Jul 14 04:23:28 PM PDT 24
Finished Jul 14 04:23:30 PM PDT 24
Peak memory 196892 kb
Host smart-0ae1cf40-6978-4c47-a8c9-2d1450756eef
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3259207755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.3259207755
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.132064613
Short name T918
Test name
Test status
Simulation time 48831331 ps
CPU time 0.83 seconds
Started Jul 14 04:23:24 PM PDT 24
Finished Jul 14 04:23:26 PM PDT 24
Peak memory 197508 kb
Host smart-b1b5bca1-1d95-4377-8c4b-0f25972e059d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132064613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.132064613
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1040699204
Short name T852
Test name
Test status
Simulation time 76862073 ps
CPU time 1.11 seconds
Started Jul 14 04:23:23 PM PDT 24
Finished Jul 14 04:23:26 PM PDT 24
Peak memory 198276 kb
Host smart-c78d45be-cce4-4e34-b7f7-f086b8b70ab8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1040699204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1040699204
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.236317119
Short name T843
Test name
Test status
Simulation time 176461699 ps
CPU time 1.32 seconds
Started Jul 14 04:23:29 PM PDT 24
Finished Jul 14 04:23:32 PM PDT 24
Peak memory 191932 kb
Host smart-66d3b14a-c47b-4a26-8f44-c574967ff0a4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236317119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.236317119
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1192648698
Short name T901
Test name
Test status
Simulation time 61023729 ps
CPU time 0.95 seconds
Started Jul 14 04:23:30 PM PDT 24
Finished Jul 14 04:23:33 PM PDT 24
Peak memory 195916 kb
Host smart-69eb566b-af1a-4da4-a6b5-1611d256782b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1192648698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1192648698
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3638435685
Short name T889
Test name
Test status
Simulation time 204377965 ps
CPU time 0.96 seconds
Started Jul 14 04:23:26 PM PDT 24
Finished Jul 14 04:23:27 PM PDT 24
Peak memory 196136 kb
Host smart-3208a630-ef2b-4a32-84c3-2a75e240e6a1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638435685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3638435685
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2515530966
Short name T879
Test name
Test status
Simulation time 42531321 ps
CPU time 1.01 seconds
Started Jul 14 04:22:20 PM PDT 24
Finished Jul 14 04:22:22 PM PDT 24
Peak memory 196784 kb
Host smart-642ce019-2c11-4fa2-834c-16ea6dc476a1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2515530966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2515530966
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2613159854
Short name T911
Test name
Test status
Simulation time 26258379 ps
CPU time 0.69 seconds
Started Jul 14 04:22:20 PM PDT 24
Finished Jul 14 04:22:22 PM PDT 24
Peak memory 194368 kb
Host smart-8d9b6253-caa2-4c0c-b55a-38b3ec37d4ac
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613159854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2613159854
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.765218796
Short name T883
Test name
Test status
Simulation time 333746075 ps
CPU time 1.23 seconds
Started Jul 14 04:23:21 PM PDT 24
Finished Jul 14 04:23:23 PM PDT 24
Peak memory 196788 kb
Host smart-472fd52e-0e39-4d61-aaf4-65dca235e551
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=765218796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.765218796
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2515422843
Short name T877
Test name
Test status
Simulation time 108664621 ps
CPU time 1.38 seconds
Started Jul 14 04:23:22 PM PDT 24
Finished Jul 14 04:23:25 PM PDT 24
Peak memory 197040 kb
Host smart-419f78ba-ab9f-40e8-b44a-eb491557a0cd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515422843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2515422843
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.4023942907
Short name T876
Test name
Test status
Simulation time 450604515 ps
CPU time 1.17 seconds
Started Jul 14 04:23:30 PM PDT 24
Finished Jul 14 04:23:33 PM PDT 24
Peak memory 196660 kb
Host smart-79c0587b-8244-4351-af17-83008fe43a05
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4023942907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.4023942907
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.177250588
Short name T897
Test name
Test status
Simulation time 48542606 ps
CPU time 1.29 seconds
Started Jul 14 04:23:29 PM PDT 24
Finished Jul 14 04:23:32 PM PDT 24
Peak memory 197036 kb
Host smart-c5d45123-fb29-4a9a-aa2e-d716a65c42e5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177250588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.177250588
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2960225548
Short name T904
Test name
Test status
Simulation time 612948922 ps
CPU time 1 seconds
Started Jul 14 04:23:20 PM PDT 24
Finished Jul 14 04:23:22 PM PDT 24
Peak memory 196840 kb
Host smart-a5f13dea-e346-4fca-9801-68851ad634bc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2960225548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.2960225548
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1743334299
Short name T873
Test name
Test status
Simulation time 114602815 ps
CPU time 1.06 seconds
Started Jul 14 04:23:23 PM PDT 24
Finished Jul 14 04:23:26 PM PDT 24
Peak memory 196760 kb
Host smart-a33e0a3e-2e0d-44aa-bb83-ae1beb7e7e63
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743334299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1743334299
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2552812204
Short name T915
Test name
Test status
Simulation time 222755388 ps
CPU time 1.11 seconds
Started Jul 14 04:23:31 PM PDT 24
Finished Jul 14 04:23:35 PM PDT 24
Peak memory 196776 kb
Host smart-adc048ec-4708-4db1-a339-b4d61b02103f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2552812204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2552812204
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1863768749
Short name T851
Test name
Test status
Simulation time 51129835 ps
CPU time 1.32 seconds
Started Jul 14 04:23:27 PM PDT 24
Finished Jul 14 04:23:29 PM PDT 24
Peak memory 196928 kb
Host smart-6fde5f62-a1d1-4cdf-8068-f2492081d208
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863768749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1863768749
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1665456942
Short name T934
Test name
Test status
Simulation time 84569452 ps
CPU time 0.97 seconds
Started Jul 14 04:23:31 PM PDT 24
Finished Jul 14 04:23:35 PM PDT 24
Peak memory 198192 kb
Host smart-fdc4f32e-c4d6-42d0-bc51-f04228cdc31a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1665456942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1665456942
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1988864334
Short name T887
Test name
Test status
Simulation time 33534853 ps
CPU time 1.09 seconds
Started Jul 14 04:23:20 PM PDT 24
Finished Jul 14 04:23:22 PM PDT 24
Peak memory 196112 kb
Host smart-c1a4943b-cf06-4035-9657-f8e9e4de542a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988864334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1988864334
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.80167490
Short name T912
Test name
Test status
Simulation time 33298127 ps
CPU time 0.92 seconds
Started Jul 14 04:23:28 PM PDT 24
Finished Jul 14 04:23:30 PM PDT 24
Peak memory 196844 kb
Host smart-88fb8302-abd4-4564-92fb-0917186e6337
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=80167490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.80167490
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1466796370
Short name T938
Test name
Test status
Simulation time 625769609 ps
CPU time 0.94 seconds
Started Jul 14 04:23:25 PM PDT 24
Finished Jul 14 04:23:27 PM PDT 24
Peak memory 196888 kb
Host smart-d6be14fa-4c55-49c5-ad32-66bf1cf051b0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466796370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1466796370
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1579344429
Short name T908
Test name
Test status
Simulation time 78878977 ps
CPU time 0.9 seconds
Started Jul 14 04:23:28 PM PDT 24
Finished Jul 14 04:23:30 PM PDT 24
Peak memory 196472 kb
Host smart-011ea239-45ea-402b-894b-abb39048b2e9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1579344429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1579344429
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2655392050
Short name T924
Test name
Test status
Simulation time 479658894 ps
CPU time 1.22 seconds
Started Jul 14 04:23:22 PM PDT 24
Finished Jul 14 04:23:25 PM PDT 24
Peak memory 197192 kb
Host smart-ca4bda11-230b-4969-9910-714b7793da2e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655392050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2655392050
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1685039721
Short name T900
Test name
Test status
Simulation time 140656885 ps
CPU time 1.24 seconds
Started Jul 14 04:23:19 PM PDT 24
Finished Jul 14 04:23:22 PM PDT 24
Peak memory 197564 kb
Host smart-8420453a-8734-4ef9-a570-5bac9daa9f1a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1685039721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1685039721
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2081618800
Short name T907
Test name
Test status
Simulation time 172801405 ps
CPU time 1.2 seconds
Started Jul 14 04:23:31 PM PDT 24
Finished Jul 14 04:23:35 PM PDT 24
Peak memory 197132 kb
Host smart-7e66998b-4af8-4f15-8d18-7638ad6ca776
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081618800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2081618800
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3013979285
Short name T856
Test name
Test status
Simulation time 64841633 ps
CPU time 1.06 seconds
Started Jul 14 04:23:23 PM PDT 24
Finished Jul 14 04:23:25 PM PDT 24
Peak memory 198272 kb
Host smart-f1dcd9f9-5a3b-44b3-9472-81943dd11728
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3013979285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3013979285
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1554884203
Short name T872
Test name
Test status
Simulation time 53027488 ps
CPU time 0.95 seconds
Started Jul 14 04:23:30 PM PDT 24
Finished Jul 14 04:23:33 PM PDT 24
Peak memory 197936 kb
Host smart-cb39707b-0371-4125-8741-2394252370ac
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554884203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1554884203
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1436787585
Short name T866
Test name
Test status
Simulation time 380162715 ps
CPU time 1.14 seconds
Started Jul 14 04:23:21 PM PDT 24
Finished Jul 14 04:23:23 PM PDT 24
Peak memory 197236 kb
Host smart-89d0b78d-5aac-4a7e-8a1f-5784c7ca0247
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1436787585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1436787585
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1304808086
Short name T868
Test name
Test status
Simulation time 426372627 ps
CPU time 1.06 seconds
Started Jul 14 04:23:28 PM PDT 24
Finished Jul 14 04:23:30 PM PDT 24
Peak memory 197072 kb
Host smart-a0412238-2ad5-4e2a-b386-58d59150c046
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304808086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1304808086
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.4150705958
Short name T916
Test name
Test status
Simulation time 38943047 ps
CPU time 0.92 seconds
Started Jul 14 04:22:29 PM PDT 24
Finished Jul 14 04:22:31 PM PDT 24
Peak memory 194996 kb
Host smart-122484ed-5b95-49af-b09e-b281a9d85cc9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4150705958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.4150705958
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2137631649
Short name T865
Test name
Test status
Simulation time 38844701 ps
CPU time 0.88 seconds
Started Jul 14 04:22:29 PM PDT 24
Finished Jul 14 04:22:31 PM PDT 24
Peak memory 194152 kb
Host smart-86ef3390-55b2-40a9-9d7b-aa759d34d07b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137631649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2137631649
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1534179696
Short name T898
Test name
Test status
Simulation time 162642752 ps
CPU time 0.84 seconds
Started Jul 14 04:21:34 PM PDT 24
Finished Jul 14 04:21:35 PM PDT 24
Peak memory 195644 kb
Host smart-4261643c-d346-4dae-8638-76bc80b48e55
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1534179696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1534179696
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3093557659
Short name T925
Test name
Test status
Simulation time 105011890 ps
CPU time 1.4 seconds
Started Jul 14 04:22:49 PM PDT 24
Finished Jul 14 04:22:51 PM PDT 24
Peak memory 197920 kb
Host smart-f83c65c6-f31c-4a72-abb5-9c8302594a1d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093557659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3093557659
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.222738768
Short name T930
Test name
Test status
Simulation time 172020152 ps
CPU time 1.25 seconds
Started Jul 14 04:21:45 PM PDT 24
Finished Jul 14 04:21:47 PM PDT 24
Peak memory 197116 kb
Host smart-7a7d684e-e130-44ea-9a62-39aa47f18ce0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=222738768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.222738768
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1216213668
Short name T857
Test name
Test status
Simulation time 272143449 ps
CPU time 1.19 seconds
Started Jul 14 04:21:44 PM PDT 24
Finished Jul 14 04:21:47 PM PDT 24
Peak memory 195040 kb
Host smart-543717a3-11da-4db3-9a86-fd40a5d30957
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216213668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1216213668
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1611395085
Short name T880
Test name
Test status
Simulation time 34477007 ps
CPU time 1.15 seconds
Started Jul 14 04:23:01 PM PDT 24
Finished Jul 14 04:23:04 PM PDT 24
Peak memory 195628 kb
Host smart-3a0a8536-5917-437b-9931-935d490d562c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1611395085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1611395085
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2525217911
Short name T909
Test name
Test status
Simulation time 286445933 ps
CPU time 1.28 seconds
Started Jul 14 04:21:59 PM PDT 24
Finished Jul 14 04:22:02 PM PDT 24
Peak memory 197240 kb
Host smart-db7d8d75-1242-4b14-a767-9f044228a514
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525217911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2525217911
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1623220940
Short name T932
Test name
Test status
Simulation time 220475669 ps
CPU time 1.21 seconds
Started Jul 14 04:21:45 PM PDT 24
Finished Jul 14 04:21:47 PM PDT 24
Peak memory 196960 kb
Host smart-78281014-2aab-4c7a-837c-c61c5d2f1fff
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1623220940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1623220940
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.415337018
Short name T929
Test name
Test status
Simulation time 134072571 ps
CPU time 1.13 seconds
Started Jul 14 04:21:58 PM PDT 24
Finished Jul 14 04:22:01 PM PDT 24
Peak memory 195960 kb
Host smart-54b7992f-599e-4369-99c3-a355c654d187
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415337018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.415337018
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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