Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4395545	1			T26	58		T27	500		T28	1
all_pins[1]	4395545	1			T26	58		T27	500		T28	1
all_pins[2]	4395545	1			T26	58		T27	500		T28	1
all_pins[3]	4395545	1			T26	58		T27	500		T28	1
all_pins[4]	4395545	1			T26	58		T27	500		T28	1
all_pins[5]	4395545	1			T26	58		T27	500		T28	1
all_pins[6]	4395545	1			T26	58		T27	500		T28	1
all_pins[7]	4395545	1			T26	58		T27	500		T28	1
all_pins[8]	4395545	1			T26	58		T27	500		T28	1
all_pins[9]	4395545	1			T26	58		T27	500		T28	1
all_pins[10]	4395545	1			T26	58		T27	500		T28	1
all_pins[11]	4395545	1			T26	58		T27	500		T28	1
all_pins[12]	4395545	1			T26	58		T27	500		T28	1
all_pins[13]	4395545	1			T26	58		T27	500		T28	1
all_pins[14]	4395545	1			T26	58		T27	500		T28	1
all_pins[15]	4395545	1			T26	58		T27	500		T28	1
all_pins[16]	4395545	1			T26	58		T27	500		T28	1
all_pins[17]	4395545	1			T26	58		T27	500		T28	1
all_pins[18]	4395545	1			T26	58		T27	500		T28	1
all_pins[19]	4395545	1			T26	58		T27	500		T28	1
all_pins[20]	4395545	1			T26	58		T27	500		T28	1
all_pins[21]	4395545	1			T26	58		T27	500		T28	1
all_pins[22]	4395545	1			T26	58		T27	500		T28	1
all_pins[23]	4395545	1			T26	58		T27	500		T28	1
all_pins[24]	4395545	1			T26	58		T27	500		T28	1
all_pins[25]	4395545	1			T26	58		T27	500		T28	1
all_pins[26]	4395545	1			T26	58		T27	500		T28	1
all_pins[27]	4395545	1			T26	58		T27	500		T28	1
all_pins[28]	4395545	1			T26	58		T27	500		T28	1
all_pins[29]	4395545	1			T26	58		T27	500		T28	1
all_pins[30]	4395545	1			T26	58		T27	500		T28	1
all_pins[31]	4395545	1			T26	58		T27	500		T28	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	87344359	1			T26	1513		T27	10254		T28	32
values[0x1]	53313081	1			T26	343		T27	5746		T30	170426
transitions[0x0=>0x1]	31935598	1			T26	221		T27	3543		T30	102242
transitions[0x1=>0x0]	31935445	1			T26	221		T27	3542		T30	102242

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2730710	1			T26	57		T27	287		T28	1
all_pins[0]	values[0x1]	1664835	1			T26	1		T27	213		T30	5177
all_pins[0]	transitions[0x0=>0x1]	1029807	1			T26	1		T27	124		T30	3382
all_pins[0]	transitions[0x1=>0x0]	1028798	1			T26	1		T27	130		T30	3246
all_pins[1]	values[0x0]	2726476	1			T26	35		T27	345		T28	1
all_pins[1]	values[0x1]	1669069	1			T26	23		T27	155		T30	5541
all_pins[1]	transitions[0x0=>0x1]	999493	1			T26	22		T27	92		T30	3259
all_pins[1]	transitions[0x1=>0x0]	995259	1			T27	150		T30	2895		T33	17
all_pins[2]	values[0x0]	2729626	1			T26	55		T27	339		T28	1
all_pins[2]	values[0x1]	1665919	1			T26	3		T27	161		T30	5507
all_pins[2]	transitions[0x0=>0x1]	995689	1			T26	1		T27	95		T30	3373
all_pins[2]	transitions[0x1=>0x0]	998839	1			T26	21		T27	89		T30	3407
all_pins[3]	values[0x0]	2728178	1			T26	51		T27	290		T28	1
all_pins[3]	values[0x1]	1667367	1			T26	7		T27	210		T30	5212
all_pins[3]	transitions[0x0=>0x1]	996933	1			T26	7		T27	135		T30	3131
all_pins[3]	transitions[0x1=>0x0]	995485	1			T26	3		T27	86		T30	3426
all_pins[4]	values[0x0]	2727074	1			T26	51		T27	256		T28	1
all_pins[4]	values[0x1]	1668471	1			T26	7		T27	244		T30	5616
all_pins[4]	transitions[0x0=>0x1]	997393	1			T26	7		T27	126		T30	3484
all_pins[4]	transitions[0x1=>0x0]	996289	1			T26	7		T27	92		T30	3080
all_pins[5]	values[0x0]	2724182	1			T26	42		T27	359		T28	1
all_pins[5]	values[0x1]	1671363	1			T26	16		T27	141		T30	5417
all_pins[5]	transitions[0x0=>0x1]	997981	1			T26	11		T27	87		T30	3099
all_pins[5]	transitions[0x1=>0x0]	995089	1			T26	2		T27	190		T30	3298
all_pins[6]	values[0x0]	2727218	1			T26	52		T27	309		T28	1
all_pins[6]	values[0x1]	1668327	1			T26	6		T27	191		T30	5154
all_pins[6]	transitions[0x0=>0x1]	994097	1			T26	1		T27	141		T30	3217
all_pins[6]	transitions[0x1=>0x0]	997133	1			T26	11		T27	91		T30	3480
all_pins[7]	values[0x0]	2734972	1			T26	54		T27	301		T28	1
all_pins[7]	values[0x1]	1660573	1			T26	4		T27	199		T30	5292
all_pins[7]	transitions[0x0=>0x1]	992554	1			T26	1		T27	128		T30	3181
all_pins[7]	transitions[0x1=>0x0]	1000308	1			T26	3		T27	120		T30	3043
all_pins[8]	values[0x0]	2730442	1			T26	33		T27	260		T28	1
all_pins[8]	values[0x1]	1665103	1			T26	25		T27	240		T30	5172
all_pins[8]	transitions[0x0=>0x1]	997836	1			T26	21		T27	119		T30	3138
all_pins[8]	transitions[0x1=>0x0]	993306	1			T27	78		T30	3258		T33	28
all_pins[9]	values[0x0]	2734084	1			T26	48		T27	348		T28	1
all_pins[9]	values[0x1]	1661461	1			T26	10		T27	152		T30	5294
all_pins[9]	transitions[0x0=>0x1]	996458	1			T26	1		T27	92		T30	3257
all_pins[9]	transitions[0x1=>0x0]	1000100	1			T26	16		T27	180		T30	3135
all_pins[10]	values[0x0]	2731673	1			T26	51		T27	384		T28	1
all_pins[10]	values[0x1]	1663872	1			T26	7		T27	116		T30	5191
all_pins[10]	transitions[0x0=>0x1]	996167	1			T26	3		T27	68		T30	2985
all_pins[10]	transitions[0x1=>0x0]	993756	1			T26	6		T27	104		T30	3088
all_pins[11]	values[0x0]	2732371	1			T26	53		T27	254		T28	1
all_pins[11]	values[0x1]	1663174	1			T26	5		T27	246		T30	5232
all_pins[11]	transitions[0x0=>0x1]	998043	1			T26	4		T27	172		T30	3232
all_pins[11]	transitions[0x1=>0x0]	998741	1			T26	6		T27	42		T30	3191
all_pins[12]	values[0x0]	2730080	1			T26	49		T27	315		T28	1
all_pins[12]	values[0x1]	1665465	1			T26	9		T27	185		T30	5324
all_pins[12]	transitions[0x0=>0x1]	998583	1			T26	7		T27	94		T30	3259
all_pins[12]	transitions[0x1=>0x0]	996292	1			T26	3		T27	155		T30	3167
all_pins[13]	values[0x0]	2725191	1			T26	33		T27	355		T28	1
all_pins[13]	values[0x1]	1670354	1			T26	25		T27	145		T30	5231
all_pins[13]	transitions[0x0=>0x1]	998955	1			T26	16		T27	77		T30	2971
all_pins[13]	transitions[0x1=>0x0]	994066	1			T27	117		T30	3064		T33	15
all_pins[14]	values[0x0]	2728453	1			T26	51		T27	287		T28	1
all_pins[14]	values[0x1]	1667092	1			T26	7		T27	213		T30	5348
all_pins[14]	transitions[0x0=>0x1]	997288	1			T26	4		T27	161		T30	3127
all_pins[14]	transitions[0x1=>0x0]	1000550	1			T26	22		T27	93		T30	3010
all_pins[15]	values[0x0]	2727762	1			T26	53		T27	290		T28	1
all_pins[15]	values[0x1]	1667783	1			T26	5		T27	210		T30	5374
all_pins[15]	transitions[0x0=>0x1]	999244	1			T26	3		T27	92		T30	3199
all_pins[15]	transitions[0x1=>0x0]	998553	1			T26	5		T27	95		T30	3173
all_pins[16]	values[0x0]	2723681	1			T26	43		T27	333		T28	1
all_pins[16]	values[0x1]	1671864	1			T26	15		T27	167		T30	5226
all_pins[16]	transitions[0x0=>0x1]	1001370	1			T26	12		T27	80		T30	3045
all_pins[16]	transitions[0x1=>0x0]	997289	1			T26	2		T27	123		T30	3193
all_pins[17]	values[0x0]	2731650	1			T26	47		T27	368		T28	1
all_pins[17]	values[0x1]	1663895	1			T26	11		T27	132		T30	5237
all_pins[17]	transitions[0x0=>0x1]	993113	1			T26	5		T27	80		T30	3088
all_pins[17]	transitions[0x1=>0x0]	1001082	1			T26	9		T27	115		T30	3077
all_pins[18]	values[0x0]	2730409	1			T26	41		T27	321		T28	1
all_pins[18]	values[0x1]	1665136	1			T26	17		T27	179		T30	5457
all_pins[18]	transitions[0x0=>0x1]	997486	1			T26	15		T27	125		T30	3341
all_pins[18]	transitions[0x1=>0x0]	996245	1			T26	9		T27	78		T30	3121
all_pins[19]	values[0x0]	2726468	1			T26	47		T27	352		T28	1
all_pins[19]	values[0x1]	1669077	1			T26	11		T27	148		T30	5552
all_pins[19]	transitions[0x0=>0x1]	1000379	1			T26	7		T27	102		T30	3326
all_pins[19]	transitions[0x1=>0x0]	996438	1			T26	13		T27	133		T30	3231
all_pins[20]	values[0x0]	2724827	1			T26	54		T27	296		T28	1
all_pins[20]	values[0x1]	1670718	1			T26	4		T27	204		T30	5453
all_pins[20]	transitions[0x0=>0x1]	1000501	1			T26	3		T27	157		T30	3192
all_pins[20]	transitions[0x1=>0x0]	998860	1			T26	10		T27	101		T30	3291
all_pins[21]	values[0x0]	2733629	1			T26	45		T27	337		T28	1
all_pins[21]	values[0x1]	1661916	1			T26	13		T27	163		T30	5382
all_pins[21]	transitions[0x0=>0x1]	992931	1			T26	9		T27	91		T30	3187
all_pins[21]	transitions[0x1=>0x0]	1001733	1			T27	132		T30	3258		T33	14
all_pins[22]	values[0x0]	2735158	1			T26	41		T27	317		T28	1
all_pins[22]	values[0x1]	1660387	1			T26	17		T27	183		T30	5318
all_pins[22]	transitions[0x0=>0x1]	996165	1			T26	11		T27	103		T30	3142
all_pins[22]	transitions[0x1=>0x0]	997694	1			T26	7		T27	83		T30	3206
all_pins[23]	values[0x0]	2729594	1			T26	43		T27	328		T28	1
all_pins[23]	values[0x1]	1665951	1			T26	15		T27	172		T30	4995
all_pins[23]	transitions[0x0=>0x1]	997128	1			T26	8		T27	98		T30	2860
all_pins[23]	transitions[0x1=>0x0]	991564	1			T26	10		T27	109		T30	3183
all_pins[24]	values[0x0]	2730310	1			T26	52		T27	374		T28	1
all_pins[24]	values[0x1]	1665235	1			T26	6		T27	126		T30	5269
all_pins[24]	transitions[0x0=>0x1]	993976	1			T27	68		T30	3367		T33	16
all_pins[24]	transitions[0x1=>0x0]	994692	1			T26	9		T27	114		T30	3093
all_pins[25]	values[0x0]	2730299	1			T26	49		T27	317		T28	1
all_pins[25]	values[0x1]	1665246	1			T26	9		T27	183		T30	5313
all_pins[25]	transitions[0x0=>0x1]	998136	1			T26	4		T27	147		T30	3209
all_pins[25]	transitions[0x1=>0x0]	998125	1			T26	1		T27	90		T30	3165
all_pins[26]	values[0x0]	2730685	1			T26	44		T27	297		T28	1
all_pins[26]	values[0x1]	1664860	1			T26	14		T27	203		T30	5544
all_pins[26]	transitions[0x0=>0x1]	995002	1			T26	9		T27	129		T30	3356
all_pins[26]	transitions[0x1=>0x0]	995388	1			T26	4		T27	109		T30	3125
all_pins[27]	values[0x0]	2732314	1			T26	45		T27	367		T28	1
all_pins[27]	values[0x1]	1663231	1			T26	13		T27	133		T30	5250
all_pins[27]	transitions[0x0=>0x1]	994870	1			T26	10		T27	70		T30	3056
all_pins[27]	transitions[0x1=>0x0]	996499	1			T26	11		T27	140		T30	3350
all_pins[28]	values[0x0]	2732365	1			T26	46		T27	332		T28	1
all_pins[28]	values[0x1]	1663180	1			T26	12		T27	168		T30	5559
all_pins[28]	transitions[0x0=>0x1]	998281	1			T26	4		T27	121		T30	3398
all_pins[28]	transitions[0x1=>0x0]	998332	1			T26	5		T27	86		T30	3089
all_pins[29]	values[0x0]	2727270	1			T26	37		T27	333		T28	1
all_pins[29]	values[0x1]	1668275	1			T26	21		T27	167		T30	5459
all_pins[29]	transitions[0x0=>0x1]	998629	1			T26	13		T27	122		T30	3249
all_pins[29]	transitions[0x1=>0x0]	993534	1			T26	4		T27	123		T30	3349
all_pins[30]	values[0x0]	2725642	1			T26	54		T27	323		T28	1
all_pins[30]	values[0x1]	1669903	1			T26	4		T27	177		T30	5289
all_pins[30]	transitions[0x0=>0x1]	997149	1			T27	115		T30	3156		T33	19
all_pins[30]	transitions[0x1=>0x0]	995521	1			T26	17		T27	105		T30	3326
all_pins[31]	values[0x0]	2731566	1			T26	57		T27	280		T28	1
all_pins[31]	values[0x1]	1663979	1			T26	1		T27	220		T30	5041
all_pins[31]	transitions[0x0=>0x1]	993961	1			T26	1		T27	132		T30	2976
all_pins[31]	transitions[0x1=>0x0]	999885	1			T26	4		T27	89		T30	3224