Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14611021	1			T26	75		T27	1211		T28	405
all_values[1]	14611021	1			T26	75		T27	1211		T28	405
all_values[2]	14611021	1			T26	75		T27	1211		T28	405
all_values[3]	14611021	1			T26	75		T27	1211		T28	405
all_values[4]	14611021	1			T26	75		T27	1211		T28	405
all_values[5]	14611021	1			T26	75		T27	1211		T28	405
all_values[6]	14611021	1			T26	75		T27	1211		T28	405
all_values[7]	14611021	1			T26	75		T27	1211		T28	405
all_values[8]	14611021	1			T26	75		T27	1211		T28	405
all_values[9]	14611021	1			T26	75		T27	1211		T28	405
all_values[10]	14611021	1			T26	75		T27	1211		T28	405
all_values[11]	14611021	1			T26	75		T27	1211		T28	405
all_values[12]	14611021	1			T26	75		T27	1211		T28	405
all_values[13]	14611021	1			T26	75		T27	1211		T28	405
all_values[14]	14611021	1			T26	75		T27	1211		T28	405
all_values[15]	14611021	1			T26	75		T27	1211		T28	405
all_values[16]	14611021	1			T26	75		T27	1211		T28	405
all_values[17]	14611021	1			T26	75		T27	1211		T28	405
all_values[18]	14611021	1			T26	75		T27	1211		T28	405
all_values[19]	14611021	1			T26	75		T27	1211		T28	405
all_values[20]	14611021	1			T26	75		T27	1211		T28	405
all_values[21]	14611021	1			T26	75		T27	1211		T28	405
all_values[22]	14611021	1			T26	75		T27	1211		T28	405
all_values[23]	14611021	1			T26	75		T27	1211		T28	405
all_values[24]	14611021	1			T26	75		T27	1211		T28	405
all_values[25]	14611021	1			T26	75		T27	1211		T28	405
all_values[26]	14611021	1			T26	75		T27	1211		T28	405
all_values[27]	14611021	1			T26	75		T27	1211		T28	405
all_values[28]	14611021	1			T26	75		T27	1211		T28	405
all_values[29]	14611021	1			T26	75		T27	1211		T28	405
all_values[30]	14611021	1			T26	75		T27	1211		T28	405
all_values[31]	14611021	1			T26	75		T27	1211		T28	405

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

267626322

1

T26

1529

T27

19935

T28

12960

auto[1]

199926350

1

T26

871

T27

18817

T30

578113

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105958869

1

T26

1681

T27

5841

T28

12960

auto[1]

361593803

1

T26

719

T27

32911

T30

102898

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

462328945

1

T26

2308

T27

37265

T28

12960

auto[1]

5223727

1

T26

92

T27

1487

T30

19374

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2711880	1			T26	39		T27	79		T28	405
all_values[0]	auto[0]	auto[0]	auto[1]	5577267	1			T26	4		T27	428		T30	15927
all_values[0]	auto[0]	auto[1]	auto[0]	596267	1			T26	28		T27	76		T30	1911
all_values[0]	auto[0]	auto[1]	auto[1]	5562513	1			T27	574		T30	15734		T34	1437
all_values[0]	auto[1]	auto[0]	auto[1]	81905	1			T26	3		T27	28		T30	311
all_values[0]	auto[1]	auto[1]	auto[1]	81189	1			T26	1		T27	26		T30	295
all_values[1]	auto[0]	auto[0]	auto[0]	2707453	1			T26	36		T27	106		T28	405
all_values[1]	auto[0]	auto[0]	auto[1]	5575538	1			T27	532		T30	15035		T34	1040
all_values[1]	auto[0]	auto[1]	auto[0]	601079	1			T26	10		T27	77		T30	1862
all_values[1]	auto[0]	auto[1]	auto[1]	5563787	1			T26	29		T27	459		T30	15717
all_values[1]	auto[1]	auto[0]	auto[1]	81209	1			T27	20		T30	291		T35	39
all_values[1]	auto[1]	auto[1]	auto[1]	81955	1			T27	17		T30	332		T35	38
all_values[2]	auto[0]	auto[0]	auto[0]	2711390	1			T26	41		T27	152		T28	405
all_values[2]	auto[0]	auto[0]	auto[1]	5585629	1			T26	8		T27	495		T30	15197
all_values[2]	auto[0]	auto[1]	auto[0]	615008	1			T26	22		T27	53		T30	1599
all_values[2]	auto[0]	auto[1]	auto[1]	5535701	1			T26	1		T27	465		T30	17014
all_values[2]	auto[1]	auto[0]	auto[1]	82149	1			T26	2		T27	23		T30	308
all_values[2]	auto[1]	auto[1]	auto[1]	81144	1			T26	1		T27	23		T30	300
all_values[3]	auto[0]	auto[0]	auto[0]	2712783	1			T26	39		T27	84		T28	405
all_values[3]	auto[0]	auto[0]	auto[1]	5552747	1			T26	18		T27	440		T30	16623
all_values[3]	auto[0]	auto[1]	auto[0]	607284	1			T26	10		T27	108		T30	1815
all_values[3]	auto[0]	auto[1]	auto[1]	5574454	1			T26	5		T27	535		T30	15205
all_values[3]	auto[1]	auto[0]	auto[1]	82455	1			T26	2		T27	18		T30	314
all_values[3]	auto[1]	auto[1]	auto[1]	81298	1			T26	1		T27	26		T30	300
all_values[4]	auto[0]	auto[0]	auto[0]	2707071	1			T26	32		T27	52		T28	405
all_values[4]	auto[0]	auto[0]	auto[1]	5547438	1			T26	14		T27	486		T30	15234
all_values[4]	auto[0]	auto[1]	auto[0]	606837	1			T26	18		T27	36		T30	1619
all_values[4]	auto[0]	auto[1]	auto[1]	5586907	1			T26	8		T27	596		T30	16752
all_values[4]	auto[1]	auto[0]	auto[1]	81828	1			T26	1		T27	18		T30	293
all_values[4]	auto[1]	auto[1]	auto[1]	80940	1			T26	2		T27	23		T30	317
all_values[5]	auto[0]	auto[0]	auto[0]	2710804	1			T26	37		T27	126		T28	405
all_values[5]	auto[0]	auto[0]	auto[1]	5538715	1			T26	10		T27	554		T30	15300
all_values[5]	auto[0]	auto[1]	auto[0]	601576	1			T26	3		T27	95		T30	1809
all_values[5]	auto[0]	auto[1]	auto[1]	5596727	1			T26	20		T27	395		T30	16226
all_values[5]	auto[1]	auto[0]	auto[1]	81478	1			T26	3		T27	21		T30	304
all_values[5]	auto[1]	auto[1]	auto[1]	81721	1			T26	2		T27	20		T30	296
all_values[6]	auto[0]	auto[0]	auto[0]	2700789	1			T26	44		T27	95		T28	405
all_values[6]	auto[0]	auto[0]	auto[1]	5581416	1			T26	5		T27	547		T30	16829
all_values[6]	auto[0]	auto[1]	auto[0]	598471	1			T26	16		T27	64		T30	2040
all_values[6]	auto[0]	auto[1]	auto[1]	5567013	1			T26	8		T27	464		T30	14561
all_values[6]	auto[1]	auto[0]	auto[1]	81821	1			T26	1		T27	23		T30	327
all_values[6]	auto[1]	auto[1]	auto[1]	81511	1			T26	1		T27	18		T30	297
all_values[7]	auto[0]	auto[0]	auto[0]	2716342	1			T26	51		T27	56		T28	405
all_values[7]	auto[0]	auto[0]	auto[1]	5622289	1			T26	13		T27	435		T30	16377
all_values[7]	auto[0]	auto[1]	auto[0]	598373	1			T26	5		T27	131		T30	1724
all_values[7]	auto[0]	auto[1]	auto[1]	5510773	1			T26	4		T27	534		T30	15478
all_values[7]	auto[1]	auto[0]	auto[1]	81846	1			T26	2		T27	23		T30	324
all_values[7]	auto[1]	auto[1]	auto[1]	81398	1			T27	32		T30	279		T35	55
all_values[8]	auto[0]	auto[0]	auto[0]	2709720	1			T26	31		T27	84		T28	405
all_values[8]	auto[0]	auto[0]	auto[1]	5561253	1			T26	7		T27	368		T30	16344
all_values[8]	auto[0]	auto[1]	auto[0]	602377	1			T26	8		T27	117		T30	1861
all_values[8]	auto[0]	auto[1]	auto[1]	5573966	1			T26	25		T27	602		T30	15307
all_values[8]	auto[1]	auto[0]	auto[1]	81805	1			T26	2		T27	16		T30	312
all_values[8]	auto[1]	auto[1]	auto[1]	81900	1			T26	2		T27	24		T30	291
all_values[9]	auto[0]	auto[0]	auto[0]	2710864	1			T26	36		T27	114		T28	405
all_values[9]	auto[0]	auto[0]	auto[1]	5580359	1			T26	15		T27	622		T30	15834
all_values[9]	auto[0]	auto[1]	auto[0]	607713	1			T26	13		T27	50		T30	1656
all_values[9]	auto[0]	auto[1]	auto[1]	5549028	1			T26	7		T27	379		T30	15881
all_values[9]	auto[1]	auto[0]	auto[1]	81857	1			T26	2		T27	29		T30	300
all_values[9]	auto[1]	auto[1]	auto[1]	81200	1			T26	2		T27	17		T30	301
all_values[10]	auto[0]	auto[0]	auto[0]	2702210	1			T26	38		T27	84		T28	405
all_values[10]	auto[0]	auto[0]	auto[1]	5596428	1			T26	13		T27	659		T30	16303
all_values[10]	auto[0]	auto[1]	auto[0]	599782	1			T26	17		T27	58		T30	1713
all_values[10]	auto[0]	auto[1]	auto[1]	5549255	1			T26	4		T27	352		T30	15611
all_values[10]	auto[1]	auto[0]	auto[1]	82250	1			T26	2		T27	36		T30	285
all_values[10]	auto[1]	auto[1]	auto[1]	81096	1			T26	1		T27	22		T30	306
all_values[11]	auto[0]	auto[0]	auto[0]	2703179	1			T26	37		T27	80		T28	405
all_values[11]	auto[0]	auto[0]	auto[1]	5595640	1			T26	3		T27	437		T30	15821
all_values[11]	auto[0]	auto[1]	auto[0]	606555	1			T26	26		T27	63		T30	1896
all_values[11]	auto[0]	auto[1]	auto[1]	5542654	1			T26	6		T27	583		T30	15795
all_values[11]	auto[1]	auto[0]	auto[1]	81977	1			T27	25		T30	325		T35	46
all_values[11]	auto[1]	auto[1]	auto[1]	81016	1			T26	3		T27	23		T30	287
all_values[12]	auto[0]	auto[0]	auto[0]	2711371	1			T26	42		T27	76		T28	405
all_values[12]	auto[0]	auto[0]	auto[1]	5527956	1			T26	11		T27	511		T30	14896
all_values[12]	auto[0]	auto[1]	auto[0]	601177	1			T26	11		T27	98		T30	1843
all_values[12]	auto[0]	auto[1]	auto[1]	5607519	1			T26	9		T27	476		T30	16864
all_values[12]	auto[1]	auto[0]	auto[1]	81521	1			T26	1		T27	30		T30	283
all_values[12]	auto[1]	auto[1]	auto[1]	81477	1			T26	1		T27	20		T30	320
all_values[13]	auto[0]	auto[0]	auto[0]	2708253	1			T26	37		T27	100		T28	405
all_values[13]	auto[0]	auto[0]	auto[1]	5555748	1			T26	2		T27	577		T30	16347
all_values[13]	auto[0]	auto[1]	auto[0]	610352	1			T26	5		T27	63		T30	2158
all_values[13]	auto[0]	auto[1]	auto[1]	5573467	1			T26	29		T27	424		T30	14990
all_values[13]	auto[1]	auto[0]	auto[1]	81747	1			T27	30		T30	302		T35	48
all_values[13]	auto[1]	auto[1]	auto[1]	81454	1			T26	2		T27	17		T30	304
all_values[14]	auto[0]	auto[0]	auto[0]	2709695	1			T26	32		T27	69		T28	405
all_values[14]	auto[0]	auto[0]	auto[1]	5578076	1			T26	18		T27	430		T30	15605
all_values[14]	auto[0]	auto[1]	auto[0]	612014	1			T26	18		T27	76		T30	2150
all_values[14]	auto[0]	auto[1]	auto[1]	5547940	1			T26	5		T27	589		T30	15748
all_values[14]	auto[1]	auto[0]	auto[1]	81606	1			T26	1		T27	15		T30	307
all_values[14]	auto[1]	auto[1]	auto[1]	81690	1			T26	1		T27	32		T30	299
all_values[15]	auto[0]	auto[0]	auto[0]	2696188	1			T26	31		T27	57		T28	405
all_values[15]	auto[0]	auto[0]	auto[1]	5590390	1			T26	16		T27	443		T30	15347
all_values[15]	auto[0]	auto[1]	auto[0]	598905	1			T26	18		T27	104		T30	2572
all_values[15]	auto[0]	auto[1]	auto[1]	5562087	1			T26	8		T27	555		T30	15435
all_values[15]	auto[1]	auto[0]	auto[1]	81655	1			T26	2		T27	20		T30	307
all_values[15]	auto[1]	auto[1]	auto[1]	81796	1			T27	32		T30	313		T35	42
all_values[16]	auto[0]	auto[0]	auto[0]	2697581	1			T26	38		T27	90		T28	405
all_values[16]	auto[0]	auto[0]	auto[1]	5556207	1			T26	3		T27	526		T30	15480
all_values[16]	auto[0]	auto[1]	auto[0]	599640	1			T26	16		T27	85		T30	1918
all_values[16]	auto[0]	auto[1]	auto[1]	5594613	1			T26	15		T27	467		T30	16172
all_values[16]	auto[1]	auto[0]	auto[1]	81040	1			T26	2		T27	16		T30	302
all_values[16]	auto[1]	auto[1]	auto[1]	81940	1			T26	1		T27	27		T30	308
all_values[17]	auto[0]	auto[0]	auto[0]	2715299	1			T26	26		T27	70		T28	405
all_values[17]	auto[0]	auto[0]	auto[1]	5571939	1			T27	646		T30	15558		T34	1266
all_values[17]	auto[0]	auto[1]	auto[0]	600735	1			T26	35		T27	65		T30	1955
all_values[17]	auto[0]	auto[1]	auto[1]	5559272	1			T26	12		T27	377		T30	15888
all_values[17]	auto[1]	auto[0]	auto[1]	82034	1			T27	36		T30	318		T35	50
all_values[17]	auto[1]	auto[1]	auto[1]	81742	1			T26	2		T27	17		T30	301
all_values[18]	auto[0]	auto[0]	auto[0]	2707508	1			T26	31		T27	91		T28	405
all_values[18]	auto[0]	auto[0]	auto[1]	5582977	1			T26	16		T27	576		T30	15467
all_values[18]	auto[0]	auto[1]	auto[0]	595916	1			T26	9		T27	43		T30	1761
all_values[18]	auto[0]	auto[1]	auto[1]	5561443	1			T26	15		T27	456		T30	16483
all_values[18]	auto[1]	auto[0]	auto[1]	81709	1			T26	1		T27	24		T30	301
all_values[18]	auto[1]	auto[1]	auto[1]	81468	1			T26	3		T27	21		T30	292
all_values[19]	auto[0]	auto[0]	auto[0]	2704307	1			T26	44		T27	91		T28	405
all_values[19]	auto[0]	auto[0]	auto[1]	5600347	1			T26	15		T27	570		T30	14855
all_values[19]	auto[0]	auto[1]	auto[0]	596626	1			T26	4		T27	97		T30	1947
all_values[19]	auto[0]	auto[1]	auto[1]	5546635	1			T26	8		T27	413		T30	16764
all_values[19]	auto[1]	auto[0]	auto[1]	81387	1			T26	2		T27	20		T30	321
all_values[19]	auto[1]	auto[1]	auto[1]	81719	1			T26	2		T27	20		T30	310
all_values[20]	auto[0]	auto[0]	auto[0]	2706638	1			T26	34		T27	117		T28	405
all_values[20]	auto[0]	auto[0]	auto[1]	5550149	1			T26	4		T27	425		T30	15345
all_values[20]	auto[0]	auto[1]	auto[0]	607009	1			T26	33		T27	88		T30	2384
all_values[20]	auto[0]	auto[1]	auto[1]	5583987	1			T26	3		T27	528		T30	15895
all_values[20]	auto[1]	auto[0]	auto[1]	81677	1			T27	27		T30	297		T35	42
all_values[20]	auto[1]	auto[1]	auto[1]	81561	1			T26	1		T27	26		T30	326
all_values[21]	auto[0]	auto[0]	auto[0]	2707141	1			T26	31		T27	60		T28	405
all_values[21]	auto[0]	auto[0]	auto[1]	5566337	1			T26	10		T27	557		T30	15078
all_values[21]	auto[0]	auto[1]	auto[0]	602079	1			T26	19		T27	94		T30	2206
all_values[21]	auto[0]	auto[1]	auto[1]	5572233	1			T26	12		T27	442		T30	16301
all_values[21]	auto[1]	auto[0]	auto[1]	82265	1			T26	2		T27	23		T30	276
all_values[21]	auto[1]	auto[1]	auto[1]	80966	1			T26	1		T27	35		T30	318
all_values[22]	auto[0]	auto[0]	auto[0]	2702388	1			T26	36		T27	131		T28	405
all_values[22]	auto[0]	auto[0]	auto[1]	5618925	1			T26	5		T27	421		T30	16358
all_values[22]	auto[0]	auto[1]	auto[0]	602507	1			T26	11		T27	92		T30	1755
all_values[22]	auto[0]	auto[1]	auto[1]	5523756	1			T26	21		T27	524		T30	15654
all_values[22]	auto[1]	auto[0]	auto[1]	82146	1			T26	1		T27	25		T30	321
all_values[22]	auto[1]	auto[1]	auto[1]	81299	1			T26	1		T27	18		T30	298
all_values[23]	auto[0]	auto[0]	auto[0]	2715642	1			T26	36		T27	178		T28	405
all_values[23]	auto[0]	auto[0]	auto[1]	5582362	1			T26	8		T27	422		T30	16244
all_values[23]	auto[0]	auto[1]	auto[0]	597727	1			T26	16		T27	113		T30	1944
all_values[23]	auto[0]	auto[1]	auto[1]	5552148	1			T26	12		T27	457		T30	14995
all_values[23]	auto[1]	auto[0]	auto[1]	81541	1			T26	1		T27	17		T30	312
all_values[23]	auto[1]	auto[1]	auto[1]	81601	1			T26	2		T27	24		T30	292
all_values[24]	auto[0]	auto[0]	auto[0]	2710431	1			T26	49		T27	129		T28	405
all_values[24]	auto[0]	auto[0]	auto[1]	5546891	1			T26	7		T27	595		T30	15662
all_values[24]	auto[0]	auto[1]	auto[0]	611995	1			T26	10		T27	52		T30	2891
all_values[24]	auto[0]	auto[1]	auto[1]	5578253	1			T26	5		T27	388		T30	15061
all_values[24]	auto[1]	auto[0]	auto[1]	81541	1			T26	3		T27	31		T30	314
all_values[24]	auto[1]	auto[1]	auto[1]	81910	1			T26	1		T27	16		T30	271
all_values[25]	auto[0]	auto[0]	auto[0]	2707867	1			T26	41		T27	69		T28	405
all_values[25]	auto[0]	auto[0]	auto[1]	5600802	1			T26	3		T27	444		T30	15868
all_values[25]	auto[0]	auto[1]	auto[0]	600313	1			T26	19		T27	126		T30	1766
all_values[25]	auto[0]	auto[1]	auto[1]	5539086	1			T26	8		T27	527		T30	15874
all_values[25]	auto[1]	auto[0]	auto[1]	81797	1			T26	1		T27	21		T30	306
all_values[25]	auto[1]	auto[1]	auto[1]	81156	1			T26	3		T27	24		T30	304
all_values[26]	auto[0]	auto[0]	auto[0]	2706690	1			T26	41		T27	100		T28	405
all_values[26]	auto[0]	auto[0]	auto[1]	5570775	1			T26	9		T27	429		T30	15400
all_values[26]	auto[0]	auto[1]	auto[0]	605186	1			T26	11		T27	100		T30	1764
all_values[26]	auto[0]	auto[1]	auto[1]	5565032	1			T26	12		T27	539		T30	16122
all_values[26]	auto[1]	auto[0]	auto[1]	81801	1			T26	2		T27	20		T30	314
all_values[26]	auto[1]	auto[1]	auto[1]	81537	1			T27	23		T30	262		T35	50
all_values[27]	auto[0]	auto[0]	auto[0]	2705022	1			T26	23		T27	207		T28	405
all_values[27]	auto[0]	auto[0]	auto[1]	5570285	1			T26	8		T27	518		T30	16495
all_values[27]	auto[0]	auto[1]	auto[0]	606490	1			T26	26		T27	72		T30	1880
all_values[27]	auto[0]	auto[1]	auto[1]	5565930	1			T26	15		T27	368		T30	15179
all_values[27]	auto[1]	auto[0]	auto[1]	81711	1			T26	1		T27	32		T30	298
all_values[27]	auto[1]	auto[1]	auto[1]	81583	1			T26	2		T27	14		T30	306
all_values[28]	auto[0]	auto[0]	auto[0]	2705175	1			T26	34		T27	82		T28	405
all_values[28]	auto[0]	auto[0]	auto[1]	5585542	1			T26	6		T27	513		T30	15732
all_values[28]	auto[0]	auto[1]	auto[0]	609026	1			T26	15		T27	92		T30	1826
all_values[28]	auto[0]	auto[1]	auto[1]	5547758	1			T26	15		T27	478		T30	16070
all_values[28]	auto[1]	auto[0]	auto[1]	81687	1			T26	3		T27	17		T30	305
all_values[28]	auto[1]	auto[1]	auto[1]	81833	1			T26	2		T27	29		T30	315
all_values[29]	auto[0]	auto[0]	auto[0]	2705460	1			T26	34		T27	150		T28	405
all_values[29]	auto[0]	auto[0]	auto[1]	5572926	1			T26	11		T27	463		T30	15885
all_values[29]	auto[0]	auto[1]	auto[0]	604590	1			T26	7		T27	95		T30	1736
all_values[29]	auto[0]	auto[1]	auto[1]	5565018	1			T26	19		T27	461		T30	15841
all_values[29]	auto[1]	auto[0]	auto[1]	81964	1			T26	1		T27	20		T30	285
all_values[29]	auto[1]	auto[1]	auto[1]	81063	1			T26	3		T27	22		T30	287
all_values[30]	auto[0]	auto[0]	auto[0]	2715880	1			T26	52		T27	112		T28	405
all_values[30]	auto[0]	auto[0]	auto[1]	5538729	1			T26	8		T27	543		T30	14800
all_values[30]	auto[0]	auto[1]	auto[0]	602007	1			T26	10		T27	50		T30	1887
all_values[30]	auto[0]	auto[1]	auto[1]	5591595	1			T26	3		T27	457		T30	16653
all_values[30]	auto[1]	auto[0]	auto[1]	81298	1			T26	2		T27	24		T30	314
all_values[30]	auto[1]	auto[1]	auto[1]	81512	1			T27	25		T30	272		T35	46
all_values[31]	auto[0]	auto[0]	auto[0]	2707956	1			T26	45		T27	106		T28	405
all_values[31]	auto[0]	auto[0]	auto[1]	5577013	1			T26	13		T27	376		T30	15826
all_values[31]	auto[0]	auto[1]	auto[0]	602276	1			T26	14		T27	111		T30	2139
all_values[31]	auto[0]	auto[1]	auto[1]	5560431	1			T26	1		T27	572		T30	15270
all_values[31]	auto[1]	auto[0]	auto[1]	81543	1			T26	2		T27	22		T30	311
all_values[31]	auto[1]	auto[1]	auto[1]	81802	1			T27	24		T30	287		T35	41

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal