Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[1]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[2]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[3]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[4]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[5]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[6]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[7]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[8]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[9]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[10]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[11]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[12]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[13]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[14]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[15]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[16]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[17]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[18]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[19]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[20]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[21]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[22]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[23]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[24]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[25]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[26]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[27]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[28]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[29]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[30]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[31]	14364504	1			T26	137		T27	1140		T28	617

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

274549875

1

T26

1760

T27

27596

T28

6590

auto[1]

185114253

1

T26

2624

T27

8884

T28

13154

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

368150998

1

T26

3840

T27

20498

T28

12979

auto[1]

91513130

1

T26

544

T27

15982

T28

6765

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

341273605

1

T26

3138

T27

18144

T28

13290

auto[1]

118390523

1

T26

1246

T27

18336

T28

6454

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5318812	1			T26	50		T27	242		T28	97
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3907130	1			T26	54		T27	9		T28	211
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1443551	1			T26	4		T27	303		T28	133
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1821955	1			T26	20		T27	308		T30	468
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	449912	1			T26	4		T27	14		T28	80
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1423144	1			T26	5		T27	264		T28	96
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5315914	1			T26	10		T27	271		T28	95
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3905872	1			T26	74		T27	17		T28	216
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1442573	1			T26	4		T27	302		T28	90
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1817622	1			T26	19		T27	295		T30	418
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	451110	1			T26	12		T27	7		T28	114
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1431413	1			T26	18		T27	248		T28	102
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5316473	1			T26	42		T27	314		T28	107
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3907134	1			T26	37		T27	15		T28	215
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1433640	1			T26	3		T27	293		T28	88
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1828099	1			T26	24		T27	258		T30	386
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	454893	1			T26	17		T27	14		T28	98
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1424265	1			T26	14		T27	246		T28	109
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5317087	1			T26	50		T27	308		T28	90
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3912445	1			T26	38		T27	14		T28	226
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1444353	1			T26	2		T27	198		T28	86
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1814269	1			T26	9		T27	372		T30	444
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	450741	1			T26	11		T27	16		T28	121
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1425609	1			T26	27		T27	232		T28	94
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5323229	1			T26	19		T27	368		T28	101
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3893264	1			T26	71		T27	11		T28	202
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1443230	1			T26	9		T27	207		T28	106
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1820445	1			T26	13		T27	288		T30	421
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	456071	1			T26	15		T27	11		T28	122
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1428265	1			T26	10		T27	255		T28	86
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5324875	1			T26	24		T27	300		T28	104
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3903028	1			T26	54		T27	22		T28	210
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1441945	1			T26	9		T27	222		T28	119
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1821808	1			T26	18		T27	316		T30	442
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	449823	1			T26	16		T27	12		T28	58
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1423025	1			T26	16		T27	268		T28	126
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5302037	1			T26	66		T27	257		T28	89
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3922848	1			T26	8		T27	12		T28	217
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1441104	1			T26	3		T27	230		T28	119
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1824646	1			T26	20		T27	384		T30	423
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	445597	1			T26	13		T27	10		T28	98
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1428272	1			T26	27		T27	247		T28	94
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5313783	1			T26	34		T27	347		T28	95
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3914068	1			T26	52		T27	16		T28	205
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1434947	1			T26	3		T27	277		T28	90
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1827188	1			T26	24		T27	243		T30	427
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	451226	1			T26	12		T27	8		T28	100
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1423292	1			T26	12		T27	249		T28	127
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5317836	1			T26	29		T27	387		T28	84
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3908721	1			T26	64		T27	15		T28	226
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1447618	1			T26	3		T27	180		T28	88
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1817670	1			T26	5		T27	334		T30	477
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	452214	1			T26	18		T27	9		T28	114
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1420445	1			T26	18		T27	215		T28	105
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5319080	1			T26	38		T27	284		T28	98
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3905695	1			T26	54		T27	7		T28	200
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1439685	1			T26	3		T27	216		T28	127
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1818281	1			T26	14		T27	377		T30	467
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	454769	1			T26	11		T27	22		T28	82
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1426994	1			T26	17		T27	234		T28	110
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5308092	1			T26	25		T27	220		T28	102
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3914287	1			T26	58		T27	13		T28	188
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1440902	1			T26	1		T27	250		T28	104
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1825993	1			T26	21		T27	328		T30	498
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	450408	1			T26	14		T27	18		T28	123
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1424822	1			T26	18		T27	311		T28	100
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5310537	1			T26	52		T27	261		T28	102
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3908949	1			T26	33		T27	18		T28	207
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1436618	1			T26	9		T27	296		T28	120
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1826632	1			T26	8		T27	240		T30	425
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	453709	1			T26	16		T27	13		T28	92
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1428059	1			T26	19		T27	312		T28	96
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5316255	1			T26	37		T27	307		T28	96
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3912440	1			T26	58		T27	11		T28	206
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1436551	1			T26	4		T27	238		T28	80
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1820644	1			T26	17		T27	335		T30	497
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	454261	1			T26	13		T27	18		T28	139
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1424353	1			T26	8		T27	231		T28	96
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5320803	1			T26	49		T27	235		T28	88
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3910085	1			T26	25		T27	22		T28	188
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1441906	1			T26	9		T27	240		T28	106
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1817368	1			T26	27		T27	335		T30	464
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	452472	1			T26	13		T27	10		T28	112
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1421870	1			T26	14		T27	298		T28	123
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5317164	1			T26	27		T27	318		T28	115
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3904433	1			T26	41		T27	14		T28	191
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1437112	1			T26	1		T27	181		T28	91
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1825570	1			T26	16		T27	359		T30	405
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	453707	1			T26	21		T27	10		T28	94
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1426518	1			T26	31		T27	258		T28	126
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5321450	1			T26	50		T27	261		T28	109
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3901817	1			T26	57		T27	7		T28	205
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1441448	1			T26	4		T27	263		T28	116
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1820180	1			T27	284		T30	439		T32	322
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	451095	1			T26	10		T27	15		T28	87
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1428514	1			T26	16		T27	310		T28	100
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5316482	1			T26	22		T27	243		T28	110
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3916324	1			T26	79		T27	11		T28	179
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1435245	1			T26	7		T27	234		T28	120
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1826243	1			T26	7		T27	319		T30	390
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	450593	1			T26	16		T27	11		T28	104
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1419617	1			T26	6		T27	322		T28	104
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5304945	1			T26	28		T27	278		T28	93
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3916633	1			T26	74		T27	10		T28	207
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1436148	1			T26	2		T27	304		T28	129
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1829037	1			T26	17		T27	283		T30	356
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	453546	1			T26	14		T27	15		T28	72
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1424195	1			T26	2		T27	250		T28	116
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5325865	1			T26	37		T27	295		T28	94
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3906584	1			T26	62		T27	16		T28	217
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1431537	1			T26	3		T27	231		T28	122
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1827525	1			T26	7		T27	339		T30	455
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	455076	1			T26	20		T27	10		T28	82
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1417917	1			T26	8		T27	249		T28	102
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5319390	1			T26	48		T27	281		T28	94
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3909158	1			T26	46		T27	8		T28	228
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1433037	1			T26	4		T27	200		T28	100
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1828971	1			T26	6		T27	351		T30	418
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	453346	1			T26	22		T27	13		T28	107
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1420602	1			T26	11		T27	287		T28	88
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5310497	1			T26	48		T27	325		T28	89
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3923920	1			T26	68		T27	12		T28	195
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1432144	1			T26	5		T27	370		T28	106
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1826072	1			T26	9		T27	245		T30	422
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	452477	1			T26	4		T27	10		T28	105
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1419394	1			T26	3		T27	178		T28	122
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5327586	1			T26	22		T27	305		T28	101
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3902228	1			T26	80		T27	16		T28	204
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1432393	1			T27	257		T28	104		T30	4202
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1823392	1			T26	8		T27	291		T30	527
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	454891	1			T26	17		T27	18		T28	100
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1424014	1			T26	10		T27	253		T28	108
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5323570	1			T26	36		T27	367		T28	95
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3908489	1			T26	56		T27	9		T28	198
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1430560	1			T27	218		T28	120		T30	3988
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1829611	1			T26	17		T27	299		T30	435
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	451352	1			T26	15		T27	12		T28	88
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1420922	1			T26	13		T27	235		T28	116
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5322087	1			T26	54		T27	470		T28	89
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3910629	1			T26	64		T27	12		T28	201
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1432681	1			T26	3		T27	251		T28	112
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1829412	1			T26	10		T27	238		T30	461
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	453239	1			T26	5		T27	7		T28	106
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1416456	1			T26	1		T27	162		T28	109
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5336811	1			T26	61		T27	272		T28	90
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3903386	1			T26	29		T27	10		T28	228
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1431692	1			T26	6		T27	153		T28	100
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1821506	1			T26	14		T27	422		T30	424
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	454209	1			T26	10		T27	14		T28	111
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1416900	1			T26	17		T27	269		T28	88
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5320290	1			T26	43		T27	311		T28	100
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3912303	1			T26	56		T27	16		T28	228
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1433080	1			T26	7		T27	278		T28	118
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1826882	1			T26	5		T27	289		T30	540
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	452760	1			T26	16		T27	16		T28	76
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1419189	1			T26	10		T27	230		T28	95
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5323170	1			T26	36		T27	262		T28	95
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3908967	1			T26	44		T27	15		T28	235
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1436424	1			T26	12		T27	213		T28	112
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1822322	1			T26	13		T27	334		T30	387
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	454377	1			T26	16		T27	14		T28	102
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1419244	1			T26	16		T27	302		T28	73
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5316844	1			T26	22		T27	351		T28	101
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3912351	1			T26	75		T27	17		T28	233
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1429108	1			T26	14		T27	297		T28	96
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1829195	1			T26	11		T27	218		T30	450
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	453232	1			T26	10		T27	5		T28	98
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1423774	1			T26	5		T27	252		T28	89
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5327766	1			T26	18		T27	351		T28	101
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3903820	1			T26	94		T27	13		T28	203
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1431959	1			T26	5		T27	199		T28	114
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1827227	1			T26	3		T27	293		T30	423
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	450188	1			T26	15		T27	8		T28	89
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1423544	1			T26	2		T27	276		T28	110
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5322978	1			T26	53		T27	341		T28	105
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3908994	1			T26	56		T27	11		T28	215
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1430912	1			T26	4		T27	189		T28	114
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1824701	1			T26	6		T27	320		T30	495
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	453098	1			T26	15		T27	17		T28	84
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1423821	1			T26	3		T27	262		T28	99
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5315623	1			T26	43		T27	318		T28	93
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3919094	1			T26	56		T27	6		T28	205
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1434755	1			T27	313		T28	123		T30	4108
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1825173	1			T26	13		T27	314		T30	338
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	451729	1			T26	13		T27	7		T28	102
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1418130	1			T26	12		T27	182		T28	94
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5321929	1			T26	39		T27	362		T28	91
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3903746	1			T26	64		T27	15		T28	211
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1436645	1			T26	2		T27	309		T28	124
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1829473	1			T26	2		T27	261		T30	428
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	451663	1			T26	20		T27	10		T28	106
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1421048	1			T26	10		T27	183		T28	85

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal