Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[1]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[2]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[3]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[4]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[5]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[6]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[7]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[8]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[9]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[10]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[11]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[12]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[13]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[14]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[15]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[16]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[17]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[18]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[19]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[20]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[21]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[22]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[23]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[24]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[25]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[26]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[27]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[28]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[29]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[30]	14364504	1			T26	137		T27	1140		T28	617
bins_for_gpio_bits[31]	14364504	1			T26	137		T27	1140		T28	617

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

274549875

1

T26

1760

T27

27596

T28

6590

auto[1]

185114253

1

T26

2624

T27

8884

T28

13154

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

274543908

1

T26

1766

T27

27588

T28

6597

auto[1]

185120220

1

T26

2618

T27

8892

T28

13147

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	8330027	1			T26	73		T27	816		T28	202
bins_for_gpio_bits[0]	auto[0]	auto[1]	254151	1			T26	1		T27	37		T28	29
bins_for_gpio_bits[0]	auto[1]	auto[0]	254291	1			T26	1		T27	37		T28	28
bins_for_gpio_bits[0]	auto[1]	auto[1]	5526035	1			T26	62		T27	250		T28	358
bins_for_gpio_bits[1]	auto[0]	auto[0]	8321248	1			T26	32		T27	830		T28	161
bins_for_gpio_bits[1]	auto[0]	auto[1]	254692	1			T26	1		T27	38		T28	24
bins_for_gpio_bits[1]	auto[1]	auto[0]	254861	1			T26	1		T27	38		T28	24
bins_for_gpio_bits[1]	auto[1]	auto[1]	5533703	1			T26	103		T27	234		T28	408
bins_for_gpio_bits[2]	auto[0]	auto[0]	8323740	1			T26	69		T27	833		T28	170
bins_for_gpio_bits[2]	auto[0]	auto[1]	254252	1			T27	32		T28	25		T30	700
bins_for_gpio_bits[2]	auto[1]	auto[0]	254472	1			T27	32		T28	25		T30	698
bins_for_gpio_bits[2]	auto[1]	auto[1]	5532040	1			T26	68		T27	243		T28	397
bins_for_gpio_bits[3]	auto[0]	auto[0]	8320886	1			T26	61		T27	843		T28	150
bins_for_gpio_bits[3]	auto[0]	auto[1]	254618	1			T27	34		T28	26		T30	670
bins_for_gpio_bits[3]	auto[1]	auto[0]	254823	1			T27	35		T28	26		T30	668
bins_for_gpio_bits[3]	auto[1]	auto[1]	5534177	1			T26	76		T27	228		T28	415
bins_for_gpio_bits[4]	auto[0]	auto[0]	8332424	1			T26	39		T27	831		T28	179
bins_for_gpio_bits[4]	auto[0]	auto[1]	254299	1			T26	2		T27	32		T28	28
bins_for_gpio_bits[4]	auto[1]	auto[0]	254480	1			T26	2		T27	32		T28	28
bins_for_gpio_bits[4]	auto[1]	auto[1]	5523301	1			T26	94		T27	245		T28	382
bins_for_gpio_bits[5]	auto[0]	auto[0]	8334590	1			T26	49		T27	798		T28	193
bins_for_gpio_bits[5]	auto[0]	auto[1]	253880	1			T26	2		T27	40		T28	31
bins_for_gpio_bits[5]	auto[1]	auto[0]	254038	1			T26	2		T27	40		T28	30
bins_for_gpio_bits[5]	auto[1]	auto[1]	5521996	1			T26	84		T27	262		T28	363
bins_for_gpio_bits[6]	auto[0]	auto[0]	8312679	1			T26	89		T27	832		T28	178
bins_for_gpio_bits[6]	auto[0]	auto[1]	254881	1			T27	38		T28	31		T30	674
bins_for_gpio_bits[6]	auto[1]	auto[0]	255108	1			T27	39		T28	30		T30	674
bins_for_gpio_bits[6]	auto[1]	auto[1]	5541836	1			T26	48		T27	231		T28	378
bins_for_gpio_bits[7]	auto[0]	auto[0]	8321886	1			T26	60		T27	834		T28	159
bins_for_gpio_bits[7]	auto[0]	auto[1]	253860	1			T26	1		T27	32		T28	26
bins_for_gpio_bits[7]	auto[1]	auto[0]	254032	1			T26	1		T27	33		T28	26
bins_for_gpio_bits[7]	auto[1]	auto[1]	5534726	1			T26	75		T27	241		T28	406
bins_for_gpio_bits[8]	auto[0]	auto[0]	8329426	1			T26	36		T27	872		T28	148
bins_for_gpio_bits[8]	auto[0]	auto[1]	253535	1			T26	1		T27	28		T28	24
bins_for_gpio_bits[8]	auto[1]	auto[0]	253698	1			T26	1		T27	29		T28	24
bins_for_gpio_bits[8]	auto[1]	auto[1]	5527845	1			T26	99		T27	211		T28	421
bins_for_gpio_bits[9]	auto[0]	auto[0]	8322557	1			T26	55		T27	837		T28	197
bins_for_gpio_bits[9]	auto[0]	auto[1]	254326	1			T27	40		T28	29		T30	655
bins_for_gpio_bits[9]	auto[1]	auto[0]	254489	1			T27	40		T28	28		T30	654
bins_for_gpio_bits[9]	auto[1]	auto[1]	5533132	1			T26	82		T27	223		T28	363
bins_for_gpio_bits[10]	auto[0]	auto[0]	8320494	1			T26	47		T27	755		T28	183
bins_for_gpio_bits[10]	auto[0]	auto[1]	254276	1			T27	43		T28	23		T30	692
bins_for_gpio_bits[10]	auto[1]	auto[0]	254493	1			T27	43		T28	23		T30	691
bins_for_gpio_bits[10]	auto[1]	auto[1]	5535241	1			T26	90		T27	299		T28	388
bins_for_gpio_bits[11]	auto[0]	auto[0]	8318819	1			T26	68		T27	759		T28	195
bins_for_gpio_bits[11]	auto[0]	auto[1]	254819	1			T26	2		T27	38		T28	27
bins_for_gpio_bits[11]	auto[1]	auto[0]	254968	1			T26	1		T27	38		T28	27
bins_for_gpio_bits[11]	auto[1]	auto[1]	5535898	1			T26	66		T27	305		T28	368
bins_for_gpio_bits[12]	auto[0]	auto[0]	8319639	1			T26	57		T27	846		T28	152
bins_for_gpio_bits[12]	auto[0]	auto[1]	253615	1			T26	1		T27	34		T28	24
bins_for_gpio_bits[12]	auto[1]	auto[0]	253811	1			T26	1		T27	34		T28	24
bins_for_gpio_bits[12]	auto[1]	auto[1]	5537439	1			T26	78		T27	226		T28	417
bins_for_gpio_bits[13]	auto[0]	auto[0]	8326018	1			T26	84		T27	776		T28	170
bins_for_gpio_bits[13]	auto[0]	auto[1]	253880	1			T26	2		T27	33		T28	24
bins_for_gpio_bits[13]	auto[1]	auto[0]	254059	1			T26	1		T27	34		T28	24
bins_for_gpio_bits[13]	auto[1]	auto[1]	5530547	1			T26	50		T27	297		T28	399
bins_for_gpio_bits[14]	auto[0]	auto[0]	8325181	1			T26	44		T27	822		T28	181
bins_for_gpio_bits[14]	auto[0]	auto[1]	254475	1			T26	1		T27	36		T28	26
bins_for_gpio_bits[14]	auto[1]	auto[0]	254665	1			T27	36		T28	25		T30	722
bins_for_gpio_bits[14]	auto[1]	auto[1]	5530183	1			T26	92		T27	246		T28	385
bins_for_gpio_bits[15]	auto[0]	auto[0]	8328196	1			T26	53		T27	770		T28	201
bins_for_gpio_bits[15]	auto[0]	auto[1]	254668	1			T26	1		T27	38		T28	24
bins_for_gpio_bits[15]	auto[1]	auto[0]	254882	1			T26	1		T27	38		T28	24
bins_for_gpio_bits[15]	auto[1]	auto[1]	5526758	1			T26	82		T27	294		T28	368
bins_for_gpio_bits[16]	auto[0]	auto[0]	8323217	1			T26	35		T27	755		T28	204
bins_for_gpio_bits[16]	auto[0]	auto[1]	254559	1			T26	1		T27	41		T28	26
bins_for_gpio_bits[16]	auto[1]	auto[0]	254753	1			T26	1		T27	41		T28	26
bins_for_gpio_bits[16]	auto[1]	auto[1]	5531975	1			T26	100		T27	303		T28	361
bins_for_gpio_bits[17]	auto[0]	auto[0]	8315074	1			T26	47		T27	831		T28	193
bins_for_gpio_bits[17]	auto[0]	auto[1]	254841	1			T27	34		T28	30		T30	718
bins_for_gpio_bits[17]	auto[1]	auto[0]	255056	1			T27	34		T28	29		T30	717
bins_for_gpio_bits[17]	auto[1]	auto[1]	5539533	1			T26	90		T27	241		T28	365
bins_for_gpio_bits[18]	auto[0]	auto[0]	8330545	1			T26	46		T27	827		T28	186
bins_for_gpio_bits[18]	auto[0]	auto[1]	254212	1			T26	1		T27	38		T28	30
bins_for_gpio_bits[18]	auto[1]	auto[0]	254382	1			T26	1		T27	38		T28	30
bins_for_gpio_bits[18]	auto[1]	auto[1]	5525365	1			T26	89		T27	237		T28	371
bins_for_gpio_bits[19]	auto[0]	auto[0]	8326948	1			T26	57		T27	798		T28	169
bins_for_gpio_bits[19]	auto[0]	auto[1]	254268	1			T26	1		T27	34		T28	25
bins_for_gpio_bits[19]	auto[1]	auto[0]	254450	1			T26	1		T27	34		T28	25
bins_for_gpio_bits[19]	auto[1]	auto[1]	5528838	1			T26	78		T27	274		T28	398
bins_for_gpio_bits[20]	auto[0]	auto[0]	8313684	1			T26	62		T27	916		T28	167
bins_for_gpio_bits[20]	auto[0]	auto[1]	254897	1			T26	1		T27	24		T28	28
bins_for_gpio_bits[20]	auto[1]	auto[0]	255029	1			T27	24		T28	28		T30	690
bins_for_gpio_bits[20]	auto[1]	auto[1]	5540894	1			T26	74		T27	176		T28	394
bins_for_gpio_bits[21]	auto[0]	auto[0]	8328975	1			T26	30		T27	819		T28	178
bins_for_gpio_bits[21]	auto[0]	auto[1]	254211	1			T27	34		T28	27		T30	700
bins_for_gpio_bits[21]	auto[1]	auto[0]	254396	1			T27	34		T28	27		T30	696
bins_for_gpio_bits[21]	auto[1]	auto[1]	5526922	1			T26	107		T27	253		T28	385
bins_for_gpio_bits[22]	auto[0]	auto[0]	8328759	1			T26	53		T27	855		T28	184
bins_for_gpio_bits[22]	auto[0]	auto[1]	254808	1			T27	29		T28	31		T30	694
bins_for_gpio_bits[22]	auto[1]	auto[0]	254982	1			T27	29		T28	31		T30	692
bins_for_gpio_bits[22]	auto[1]	auto[1]	5525955	1			T26	84		T27	227		T28	371
bins_for_gpio_bits[23]	auto[0]	auto[0]	8329319	1			T26	66		T27	934		T28	172
bins_for_gpio_bits[23]	auto[0]	auto[1]	254654	1			T26	1		T27	25		T28	29
bins_for_gpio_bits[23]	auto[1]	auto[0]	254861	1			T26	1		T27	25		T28	29
bins_for_gpio_bits[23]	auto[1]	auto[1]	5525670	1			T26	69		T27	156		T28	387
bins_for_gpio_bits[24]	auto[0]	auto[0]	8335758	1			T26	79		T27	808		T28	161
bins_for_gpio_bits[24]	auto[0]	auto[1]	254053	1			T26	2		T27	38		T28	29
bins_for_gpio_bits[24]	auto[1]	auto[0]	254251	1			T26	2		T27	39		T28	29
bins_for_gpio_bits[24]	auto[1]	auto[1]	5520442	1			T26	54		T27	255		T28	398
bins_for_gpio_bits[25]	auto[0]	auto[0]	8326025	1			T26	54		T27	850		T28	189
bins_for_gpio_bits[25]	auto[0]	auto[1]	254041	1			T26	1		T27	27		T28	29
bins_for_gpio_bits[25]	auto[1]	auto[0]	254227	1			T26	1		T27	28		T28	29
bins_for_gpio_bits[25]	auto[1]	auto[1]	5530211	1			T26	81		T27	235		T28	370
bins_for_gpio_bits[26]	auto[0]	auto[0]	8327803	1			T26	58		T27	766		T28	181
bins_for_gpio_bits[26]	auto[0]	auto[1]	253877	1			T26	3		T27	43		T28	26
bins_for_gpio_bits[26]	auto[1]	auto[0]	254113	1			T26	3		T27	43		T28	26
bins_for_gpio_bits[26]	auto[1]	auto[1]	5528711	1			T26	73		T27	288		T28	384
bins_for_gpio_bits[27]	auto[0]	auto[0]	8320717	1			T26	46		T27	831		T28	172
bins_for_gpio_bits[27]	auto[0]	auto[1]	254269	1			T26	2		T27	35		T28	25
bins_for_gpio_bits[27]	auto[1]	auto[0]	254430	1			T26	1		T27	35		T28	25
bins_for_gpio_bits[27]	auto[1]	auto[1]	5535088	1			T26	88		T27	239		T28	395
bins_for_gpio_bits[28]	auto[0]	auto[0]	8332699	1			T26	26		T27	809		T28	186
bins_for_gpio_bits[28]	auto[0]	auto[1]	254056	1			T26	1		T27	34		T28	29
bins_for_gpio_bits[28]	auto[1]	auto[0]	254253	1			T27	34		T28	29		T30	698
bins_for_gpio_bits[28]	auto[1]	auto[1]	5523496	1			T26	110		T27	263		T28	373
bins_for_gpio_bits[29]	auto[0]	auto[0]	8324536	1			T26	62		T27	820		T28	193
bins_for_gpio_bits[29]	auto[0]	auto[1]	253842	1			T26	1		T27	30		T28	26
bins_for_gpio_bits[29]	auto[1]	auto[0]	254055	1			T26	1		T27	30		T28	26
bins_for_gpio_bits[29]	auto[1]	auto[1]	5532071	1			T26	73		T27	260		T28	372
bins_for_gpio_bits[30]	auto[0]	auto[0]	8321117	1			T26	56		T27	913		T28	187
bins_for_gpio_bits[30]	auto[0]	auto[1]	254239	1			T27	32		T28	30		T30	691
bins_for_gpio_bits[30]	auto[1]	auto[0]	254434	1			T27	32		T28	29		T30	689
bins_for_gpio_bits[30]	auto[1]	auto[1]	5534714	1			T26	81		T27	163		T28	371
bins_for_gpio_bits[31]	auto[0]	auto[0]	8333648	1			T26	43		T27	905		T28	189
bins_for_gpio_bits[31]	auto[0]	auto[1]	254220	1			T27	26		T28	26		T30	661
bins_for_gpio_bits[31]	auto[1]	auto[0]	254399	1			T27	27		T28	26		T30	659
bins_for_gpio_bits[31]	auto[1]	auto[1]	5522237	1			T26	94		T27	182		T28	376