Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8371052 |
1 |
|
|
T26 |
46 |
|
T27 |
535 |
|
T28 |
405 |
| auto[1] |
6239969 |
1 |
|
|
T26 |
29 |
|
T27 |
676 |
|
T30 |
17940 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13818851 |
1 |
|
|
T26 |
75 |
|
T27 |
1187 |
|
T28 |
405 |
| auto[1] |
792170 |
1 |
|
|
T27 |
24 |
|
T30 |
1914 |
|
T34 |
202 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8389199 |
1 |
|
|
T26 |
64 |
|
T27 |
567 |
|
T28 |
405 |
| auto[1] |
6221822 |
1 |
|
|
T26 |
11 |
|
T27 |
644 |
|
T30 |
17464 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2721535 |
1 |
|
|
T26 |
5 |
|
T27 |
260 |
|
T30 |
7894 |
| auto[1] |
auto[0] |
auto[1] |
396643 |
1 |
|
|
T27 |
13 |
|
T30 |
962 |
|
T34 |
79 |
| auto[1] |
auto[1] |
auto[0] |
2708117 |
1 |
|
|
T26 |
6 |
|
T27 |
360 |
|
T30 |
7656 |
| auto[1] |
auto[1] |
auto[1] |
395527 |
1 |
|
|
T27 |
11 |
|
T30 |
952 |
|
T34 |
123 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8364200 |
1 |
|
|
T26 |
36 |
|
T27 |
658 |
|
T28 |
405 |
| auto[1] |
6246821 |
1 |
|
|
T26 |
39 |
|
T27 |
553 |
|
T30 |
17911 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13811474 |
1 |
|
|
T26 |
75 |
|
T27 |
1185 |
|
T28 |
405 |
| auto[1] |
799547 |
1 |
|
|
T27 |
26 |
|
T30 |
1961 |
|
T34 |
268 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8349801 |
1 |
|
|
T26 |
56 |
|
T27 |
649 |
|
T28 |
405 |
| auto[1] |
6261220 |
1 |
|
|
T26 |
19 |
|
T27 |
562 |
|
T30 |
17339 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2733066 |
1 |
|
|
T26 |
4 |
|
T27 |
255 |
|
T30 |
7596 |
| auto[1] |
auto[0] |
auto[1] |
400228 |
1 |
|
|
T27 |
11 |
|
T30 |
975 |
|
T34 |
113 |
| auto[1] |
auto[1] |
auto[0] |
2728607 |
1 |
|
|
T26 |
15 |
|
T27 |
281 |
|
T30 |
7782 |
| auto[1] |
auto[1] |
auto[1] |
399319 |
1 |
|
|
T27 |
15 |
|
T30 |
986 |
|
T34 |
155 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8380888 |
1 |
|
|
T26 |
53 |
|
T27 |
779 |
|
T28 |
405 |
| auto[1] |
6230133 |
1 |
|
|
T26 |
22 |
|
T27 |
432 |
|
T30 |
17630 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13815589 |
1 |
|
|
T26 |
75 |
|
T27 |
1181 |
|
T28 |
405 |
| auto[1] |
795432 |
1 |
|
|
T27 |
30 |
|
T30 |
2114 |
|
T34 |
283 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8363796 |
1 |
|
|
T26 |
62 |
|
T27 |
584 |
|
T28 |
405 |
| auto[1] |
6247225 |
1 |
|
|
T26 |
13 |
|
T27 |
627 |
|
T30 |
17748 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2740249 |
1 |
|
|
T26 |
6 |
|
T27 |
400 |
|
T30 |
7795 |
| auto[1] |
auto[0] |
auto[1] |
400139 |
1 |
|
|
T27 |
22 |
|
T30 |
1045 |
|
T34 |
136 |
| auto[1] |
auto[1] |
auto[0] |
2711544 |
1 |
|
|
T26 |
7 |
|
T27 |
197 |
|
T30 |
7839 |
| auto[1] |
auto[1] |
auto[1] |
395293 |
1 |
|
|
T27 |
8 |
|
T30 |
1069 |
|
T34 |
147 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8380796 |
1 |
|
|
T26 |
40 |
|
T27 |
542 |
|
T28 |
405 |
| auto[1] |
6230225 |
1 |
|
|
T26 |
35 |
|
T27 |
669 |
|
T30 |
17978 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13811808 |
1 |
|
|
T26 |
74 |
|
T27 |
1182 |
|
T28 |
405 |
| auto[1] |
799213 |
1 |
|
|
T26 |
1 |
|
T27 |
29 |
|
T30 |
2132 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8338788 |
1 |
|
|
T26 |
60 |
|
T27 |
616 |
|
T28 |
405 |
| auto[1] |
6272233 |
1 |
|
|
T26 |
15 |
|
T27 |
595 |
|
T30 |
17952 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2757379 |
1 |
|
|
T27 |
269 |
|
T30 |
7883 |
|
T34 |
372 |
| auto[1] |
auto[0] |
auto[1] |
403643 |
1 |
|
|
T27 |
15 |
|
T30 |
1067 |
|
T34 |
83 |
| auto[1] |
auto[1] |
auto[0] |
2715641 |
1 |
|
|
T26 |
14 |
|
T27 |
297 |
|
T30 |
7937 |
| auto[1] |
auto[1] |
auto[1] |
395570 |
1 |
|
|
T26 |
1 |
|
T27 |
14 |
|
T30 |
1065 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8320848 |
1 |
|
|
T26 |
54 |
|
T27 |
617 |
|
T28 |
405 |
| auto[1] |
6290173 |
1 |
|
|
T26 |
21 |
|
T27 |
594 |
|
T30 |
19027 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13814261 |
1 |
|
|
T26 |
75 |
|
T27 |
1184 |
|
T28 |
405 |
| auto[1] |
796760 |
1 |
|
|
T27 |
27 |
|
T30 |
2166 |
|
T34 |
237 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8355544 |
1 |
|
|
T26 |
65 |
|
T27 |
559 |
|
T28 |
405 |
| auto[1] |
6255477 |
1 |
|
|
T26 |
10 |
|
T27 |
652 |
|
T30 |
18380 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2712042 |
1 |
|
|
T26 |
9 |
|
T27 |
336 |
|
T30 |
7719 |
| auto[1] |
auto[0] |
auto[1] |
394019 |
1 |
|
|
T27 |
13 |
|
T30 |
960 |
|
T34 |
154 |
| auto[1] |
auto[1] |
auto[0] |
2746675 |
1 |
|
|
T26 |
1 |
|
T27 |
289 |
|
T30 |
8495 |
| auto[1] |
auto[1] |
auto[1] |
402741 |
1 |
|
|
T27 |
14 |
|
T30 |
1206 |
|
T34 |
83 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8345748 |
1 |
|
|
T26 |
39 |
|
T27 |
707 |
|
T28 |
405 |
| auto[1] |
6265273 |
1 |
|
|
T26 |
36 |
|
T27 |
504 |
|
T30 |
17452 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13816658 |
1 |
|
|
T26 |
75 |
|
T27 |
1195 |
|
T28 |
405 |
| auto[1] |
794363 |
1 |
|
|
T27 |
16 |
|
T30 |
1898 |
|
T34 |
219 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8363103 |
1 |
|
|
T26 |
71 |
|
T27 |
653 |
|
T28 |
405 |
| auto[1] |
6247918 |
1 |
|
|
T26 |
4 |
|
T27 |
558 |
|
T30 |
17140 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2738266 |
1 |
|
|
T26 |
4 |
|
T27 |
337 |
|
T30 |
7840 |
| auto[1] |
auto[0] |
auto[1] |
399241 |
1 |
|
|
T27 |
11 |
|
T30 |
1004 |
|
T34 |
88 |
| auto[1] |
auto[1] |
auto[0] |
2715289 |
1 |
|
|
T27 |
205 |
|
T30 |
7402 |
|
T34 |
556 |
| auto[1] |
auto[1] |
auto[1] |
395122 |
1 |
|
|
T27 |
5 |
|
T30 |
894 |
|
T34 |
131 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8369377 |
1 |
|
|
T26 |
51 |
|
T27 |
514 |
|
T28 |
405 |
| auto[1] |
6241644 |
1 |
|
|
T26 |
24 |
|
T27 |
697 |
|
T30 |
18197 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13812040 |
1 |
|
|
T26 |
74 |
|
T27 |
1188 |
|
T28 |
405 |
| auto[1] |
798981 |
1 |
|
|
T26 |
1 |
|
T27 |
23 |
|
T30 |
2182 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8353294 |
1 |
|
|
T26 |
63 |
|
T27 |
671 |
|
T28 |
405 |
| auto[1] |
6257727 |
1 |
|
|
T26 |
12 |
|
T27 |
540 |
|
T30 |
18352 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2735570 |
1 |
|
|
T26 |
11 |
|
T27 |
205 |
|
T30 |
8134 |
| auto[1] |
auto[0] |
auto[1] |
400034 |
1 |
|
|
T26 |
1 |
|
T27 |
9 |
|
T30 |
1113 |
| auto[1] |
auto[1] |
auto[0] |
2723176 |
1 |
|
|
T27 |
312 |
|
T30 |
8036 |
|
T34 |
472 |
| auto[1] |
auto[1] |
auto[1] |
398947 |
1 |
|
|
T27 |
14 |
|
T30 |
1069 |
|
T34 |
118 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8368233 |
1 |
|
|
T26 |
49 |
|
T27 |
520 |
|
T28 |
405 |
| auto[1] |
6242788 |
1 |
|
|
T26 |
26 |
|
T27 |
691 |
|
T30 |
18320 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13816993 |
1 |
|
|
T26 |
75 |
|
T27 |
1182 |
|
T28 |
405 |
| auto[1] |
794028 |
1 |
|
|
T27 |
29 |
|
T30 |
1955 |
|
T34 |
242 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8368472 |
1 |
|
|
T26 |
70 |
|
T27 |
575 |
|
T28 |
405 |
| auto[1] |
6242549 |
1 |
|
|
T26 |
5 |
|
T27 |
636 |
|
T30 |
17385 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2738260 |
1 |
|
|
T27 |
227 |
|
T30 |
7632 |
|
T34 |
599 |
| auto[1] |
auto[0] |
auto[1] |
400155 |
1 |
|
|
T27 |
13 |
|
T30 |
997 |
|
T34 |
139 |
| auto[1] |
auto[1] |
auto[0] |
2710261 |
1 |
|
|
T26 |
5 |
|
T27 |
380 |
|
T30 |
7798 |
| auto[1] |
auto[1] |
auto[1] |
393873 |
1 |
|
|
T27 |
16 |
|
T30 |
958 |
|
T34 |
103 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8334828 |
1 |
|
|
T26 |
43 |
|
T27 |
632 |
|
T28 |
405 |
| auto[1] |
6276193 |
1 |
|
|
T26 |
32 |
|
T27 |
579 |
|
T30 |
18398 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13813105 |
1 |
|
|
T26 |
75 |
|
T27 |
1193 |
|
T28 |
405 |
| auto[1] |
797916 |
1 |
|
|
T27 |
18 |
|
T30 |
2264 |
|
T34 |
215 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8345451 |
1 |
|
|
T26 |
59 |
|
T27 |
769 |
|
T28 |
405 |
| auto[1] |
6265570 |
1 |
|
|
T26 |
16 |
|
T27 |
442 |
|
T30 |
19345 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2723358 |
1 |
|
|
T26 |
1 |
|
T27 |
199 |
|
T30 |
8500 |
| auto[1] |
auto[0] |
auto[1] |
397640 |
1 |
|
|
T27 |
10 |
|
T30 |
1209 |
|
T34 |
83 |
| auto[1] |
auto[1] |
auto[0] |
2744296 |
1 |
|
|
T26 |
15 |
|
T27 |
225 |
|
T30 |
8581 |
| auto[1] |
auto[1] |
auto[1] |
400276 |
1 |
|
|
T27 |
8 |
|
T30 |
1055 |
|
T34 |
132 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8369272 |
1 |
|
|
T26 |
26 |
|
T27 |
752 |
|
T28 |
405 |
| auto[1] |
6241749 |
1 |
|
|
T26 |
49 |
|
T27 |
459 |
|
T30 |
18144 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13813297 |
1 |
|
|
T26 |
74 |
|
T27 |
1188 |
|
T28 |
405 |
| auto[1] |
797724 |
1 |
|
|
T26 |
1 |
|
T27 |
23 |
|
T30 |
1963 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8350012 |
1 |
|
|
T26 |
49 |
|
T27 |
589 |
|
T28 |
405 |
| auto[1] |
6261009 |
1 |
|
|
T26 |
26 |
|
T27 |
622 |
|
T30 |
17367 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2739416 |
1 |
|
|
T27 |
413 |
|
T30 |
7685 |
|
T34 |
565 |
| auto[1] |
auto[0] |
auto[1] |
399933 |
1 |
|
|
T27 |
17 |
|
T30 |
970 |
|
T34 |
132 |
| auto[1] |
auto[1] |
auto[0] |
2723869 |
1 |
|
|
T26 |
25 |
|
T27 |
186 |
|
T30 |
7719 |
| auto[1] |
auto[1] |
auto[1] |
397791 |
1 |
|
|
T26 |
1 |
|
T27 |
6 |
|
T30 |
993 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8372194 |
1 |
|
|
T26 |
48 |
|
T27 |
691 |
|
T28 |
405 |
| auto[1] |
6238827 |
1 |
|
|
T26 |
27 |
|
T27 |
520 |
|
T30 |
18536 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13818285 |
1 |
|
|
T26 |
75 |
|
T27 |
1176 |
|
T28 |
405 |
| auto[1] |
792736 |
1 |
|
|
T27 |
35 |
|
T30 |
2237 |
|
T34 |
221 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8385466 |
1 |
|
|
T26 |
50 |
|
T27 |
495 |
|
T28 |
405 |
| auto[1] |
6225555 |
1 |
|
|
T26 |
25 |
|
T27 |
716 |
|
T30 |
18499 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2740279 |
1 |
|
|
T26 |
10 |
|
T27 |
381 |
|
T30 |
7724 |
| auto[1] |
auto[0] |
auto[1] |
400689 |
1 |
|
|
T27 |
19 |
|
T30 |
1000 |
|
T34 |
109 |
| auto[1] |
auto[1] |
auto[0] |
2692540 |
1 |
|
|
T26 |
15 |
|
T27 |
300 |
|
T30 |
8538 |
| auto[1] |
auto[1] |
auto[1] |
392047 |
1 |
|
|
T27 |
16 |
|
T30 |
1237 |
|
T34 |
112 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8386041 |
1 |
|
|
T26 |
61 |
|
T27 |
681 |
|
T28 |
405 |
| auto[1] |
6224980 |
1 |
|
|
T26 |
14 |
|
T27 |
530 |
|
T30 |
19021 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13811954 |
1 |
|
|
T26 |
75 |
|
T27 |
1191 |
|
T28 |
405 |
| auto[1] |
799067 |
1 |
|
|
T27 |
20 |
|
T30 |
2011 |
|
T34 |
263 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8350487 |
1 |
|
|
T26 |
58 |
|
T27 |
689 |
|
T28 |
405 |
| auto[1] |
6260534 |
1 |
|
|
T26 |
17 |
|
T27 |
522 |
|
T30 |
17746 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2727978 |
1 |
|
|
T26 |
12 |
|
T27 |
287 |
|
T30 |
7838 |
| auto[1] |
auto[0] |
auto[1] |
399350 |
1 |
|
|
T27 |
12 |
|
T30 |
995 |
|
T34 |
152 |
| auto[1] |
auto[1] |
auto[0] |
2733489 |
1 |
|
|
T26 |
5 |
|
T27 |
215 |
|
T30 |
7897 |
| auto[1] |
auto[1] |
auto[1] |
399717 |
1 |
|
|
T27 |
8 |
|
T30 |
1016 |
|
T34 |
111 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8379168 |
1 |
|
|
T26 |
51 |
|
T27 |
670 |
|
T28 |
405 |
| auto[1] |
6231853 |
1 |
|
|
T26 |
24 |
|
T27 |
541 |
|
T30 |
18913 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13814048 |
1 |
|
|
T26 |
75 |
|
T27 |
1187 |
|
T28 |
405 |
| auto[1] |
796973 |
1 |
|
|
T27 |
24 |
|
T30 |
1914 |
|
T34 |
255 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8359585 |
1 |
|
|
T26 |
54 |
|
T27 |
581 |
|
T28 |
405 |
| auto[1] |
6251436 |
1 |
|
|
T26 |
21 |
|
T27 |
630 |
|
T30 |
16680 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2737023 |
1 |
|
|
T26 |
10 |
|
T27 |
303 |
|
T30 |
7180 |
| auto[1] |
auto[0] |
auto[1] |
398918 |
1 |
|
|
T27 |
13 |
|
T30 |
905 |
|
T34 |
96 |
| auto[1] |
auto[1] |
auto[0] |
2717440 |
1 |
|
|
T26 |
11 |
|
T27 |
303 |
|
T30 |
7586 |
| auto[1] |
auto[1] |
auto[1] |
398055 |
1 |
|
|
T27 |
11 |
|
T30 |
1009 |
|
T34 |
159 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8338464 |
1 |
|
|
T26 |
38 |
|
T27 |
569 |
|
T28 |
405 |
| auto[1] |
6272557 |
1 |
|
|
T26 |
37 |
|
T27 |
642 |
|
T30 |
18605 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13816709 |
1 |
|
|
T26 |
75 |
|
T27 |
1190 |
|
T28 |
405 |
| auto[1] |
794312 |
1 |
|
|
T27 |
21 |
|
T30 |
2059 |
|
T34 |
279 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8382376 |
1 |
|
|
T26 |
65 |
|
T27 |
672 |
|
T28 |
405 |
| auto[1] |
6228645 |
1 |
|
|
T26 |
10 |
|
T27 |
539 |
|
T30 |
17722 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2695300 |
1 |
|
|
T26 |
1 |
|
T27 |
274 |
|
T30 |
7236 |
| auto[1] |
auto[0] |
auto[1] |
393837 |
1 |
|
|
T27 |
14 |
|
T30 |
920 |
|
T34 |
119 |
| auto[1] |
auto[1] |
auto[0] |
2739033 |
1 |
|
|
T26 |
9 |
|
T27 |
244 |
|
T30 |
8427 |
| auto[1] |
auto[1] |
auto[1] |
400475 |
1 |
|
|
T27 |
7 |
|
T30 |
1139 |
|
T34 |
160 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8355743 |
1 |
|
|
T26 |
43 |
|
T27 |
640 |
|
T28 |
405 |
| auto[1] |
6255278 |
1 |
|
|
T26 |
32 |
|
T27 |
571 |
|
T30 |
18825 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13814488 |
1 |
|
|
T26 |
75 |
|
T27 |
1192 |
|
T28 |
405 |
| auto[1] |
796533 |
1 |
|
|
T27 |
19 |
|
T30 |
1992 |
|
T34 |
290 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8355935 |
1 |
|
|
T26 |
65 |
|
T27 |
656 |
|
T28 |
405 |
| auto[1] |
6255086 |
1 |
|
|
T26 |
10 |
|
T27 |
555 |
|
T30 |
17564 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2723141 |
1 |
|
|
T26 |
6 |
|
T27 |
294 |
|
T30 |
7609 |
| auto[1] |
auto[0] |
auto[1] |
396955 |
1 |
|
|
T27 |
10 |
|
T30 |
967 |
|
T34 |
122 |
| auto[1] |
auto[1] |
auto[0] |
2735412 |
1 |
|
|
T26 |
4 |
|
T27 |
242 |
|
T30 |
7963 |
| auto[1] |
auto[1] |
auto[1] |
399578 |
1 |
|
|
T27 |
9 |
|
T30 |
1025 |
|
T34 |
168 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8403459 |
1 |
|
|
T26 |
42 |
|
T27 |
577 |
|
T28 |
405 |
| auto[1] |
6207562 |
1 |
|
|
T26 |
33 |
|
T27 |
634 |
|
T30 |
17707 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13817402 |
1 |
|
|
T26 |
75 |
|
T27 |
1192 |
|
T28 |
405 |
| auto[1] |
793619 |
1 |
|
|
T27 |
19 |
|
T30 |
2102 |
|
T34 |
209 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8380148 |
1 |
|
|
T26 |
57 |
|
T27 |
607 |
|
T28 |
405 |
| auto[1] |
6230873 |
1 |
|
|
T26 |
18 |
|
T27 |
604 |
|
T30 |
17616 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2737780 |
1 |
|
|
T26 |
5 |
|
T27 |
316 |
|
T30 |
8185 |
| auto[1] |
auto[0] |
auto[1] |
400120 |
1 |
|
|
T27 |
8 |
|
T30 |
1162 |
|
T34 |
134 |
| auto[1] |
auto[1] |
auto[0] |
2699474 |
1 |
|
|
T26 |
13 |
|
T27 |
269 |
|
T30 |
7329 |
| auto[1] |
auto[1] |
auto[1] |
393499 |
1 |
|
|
T27 |
11 |
|
T30 |
940 |
|
T34 |
75 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8379545 |
1 |
|
|
T26 |
45 |
|
T27 |
617 |
|
T28 |
405 |
| auto[1] |
6231476 |
1 |
|
|
T26 |
30 |
|
T27 |
594 |
|
T30 |
17231 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13814840 |
1 |
|
|
T26 |
74 |
|
T27 |
1187 |
|
T28 |
405 |
| auto[1] |
796181 |
1 |
|
|
T26 |
1 |
|
T27 |
24 |
|
T30 |
1980 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8362651 |
1 |
|
|
T26 |
70 |
|
T27 |
468 |
|
T28 |
405 |
| auto[1] |
6248370 |
1 |
|
|
T26 |
5 |
|
T27 |
743 |
|
T30 |
17163 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2717430 |
1 |
|
|
T27 |
378 |
|
T30 |
7754 |
|
T34 |
628 |
| auto[1] |
auto[0] |
auto[1] |
396425 |
1 |
|
|
T27 |
11 |
|
T30 |
997 |
|
T34 |
146 |
| auto[1] |
auto[1] |
auto[0] |
2734759 |
1 |
|
|
T26 |
4 |
|
T27 |
341 |
|
T30 |
7429 |
| auto[1] |
auto[1] |
auto[1] |
399756 |
1 |
|
|
T26 |
1 |
|
T27 |
13 |
|
T30 |
983 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8338863 |
1 |
|
|
T26 |
59 |
|
T27 |
755 |
|
T28 |
405 |
| auto[1] |
6272158 |
1 |
|
|
T26 |
16 |
|
T27 |
456 |
|
T30 |
18223 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13811510 |
1 |
|
|
T26 |
75 |
|
T27 |
1182 |
|
T28 |
405 |
| auto[1] |
799511 |
1 |
|
|
T27 |
29 |
|
T30 |
1970 |
|
T34 |
242 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8342480 |
1 |
|
|
T26 |
70 |
|
T27 |
399 |
|
T28 |
405 |
| auto[1] |
6268541 |
1 |
|
|
T26 |
5 |
|
T27 |
812 |
|
T30 |
17527 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2731281 |
1 |
|
|
T26 |
1 |
|
T27 |
474 |
|
T30 |
7617 |
| auto[1] |
auto[0] |
auto[1] |
400242 |
1 |
|
|
T27 |
18 |
|
T30 |
962 |
|
T34 |
150 |
| auto[1] |
auto[1] |
auto[0] |
2737749 |
1 |
|
|
T26 |
4 |
|
T27 |
309 |
|
T30 |
7940 |
| auto[1] |
auto[1] |
auto[1] |
399269 |
1 |
|
|
T27 |
11 |
|
T30 |
1008 |
|
T34 |
92 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8390466 |
1 |
|
|
T26 |
45 |
|
T27 |
534 |
|
T28 |
405 |
| auto[1] |
6220555 |
1 |
|
|
T26 |
30 |
|
T27 |
677 |
|
T30 |
17944 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13813487 |
1 |
|
|
T26 |
75 |
|
T27 |
1201 |
|
T28 |
405 |
| auto[1] |
797534 |
1 |
|
|
T27 |
10 |
|
T30 |
2227 |
|
T34 |
243 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8366005 |
1 |
|
|
T26 |
50 |
|
T27 |
779 |
|
T28 |
405 |
| auto[1] |
6245016 |
1 |
|
|
T26 |
25 |
|
T27 |
432 |
|
T30 |
18407 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2732225 |
1 |
|
|
T26 |
5 |
|
T27 |
184 |
|
T30 |
7616 |
| auto[1] |
auto[0] |
auto[1] |
399648 |
1 |
|
|
T27 |
4 |
|
T30 |
1074 |
|
T34 |
160 |
| auto[1] |
auto[1] |
auto[0] |
2715257 |
1 |
|
|
T26 |
20 |
|
T27 |
238 |
|
T30 |
8564 |
| auto[1] |
auto[1] |
auto[1] |
397886 |
1 |
|
|
T27 |
6 |
|
T30 |
1153 |
|
T34 |
83 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8359266 |
1 |
|
|
T26 |
52 |
|
T27 |
549 |
|
T28 |
405 |
| auto[1] |
6251755 |
1 |
|
|
T26 |
23 |
|
T27 |
662 |
|
T30 |
18148 |