Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8330997 |
1 |
|
|
T26 |
50 |
|
T27 |
701 |
|
T28 |
405 |
| auto[1] |
6280024 |
1 |
|
|
T26 |
25 |
|
T27 |
510 |
|
T30 |
18331 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13817190 |
1 |
|
|
T26 |
75 |
|
T27 |
1196 |
|
T28 |
405 |
| auto[1] |
793831 |
1 |
|
|
T27 |
15 |
|
T30 |
2097 |
|
T34 |
263 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8378445 |
1 |
|
|
T26 |
61 |
|
T27 |
776 |
|
T28 |
405 |
| auto[1] |
6232576 |
1 |
|
|
T26 |
14 |
|
T27 |
435 |
|
T30 |
18222 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2706088 |
1 |
|
|
T26 |
4 |
|
T27 |
211 |
|
T30 |
7512 |
| auto[1] |
auto[0] |
auto[1] |
394502 |
1 |
|
|
T27 |
9 |
|
T30 |
914 |
|
T34 |
125 |
| auto[1] |
auto[1] |
auto[0] |
2732657 |
1 |
|
|
T26 |
10 |
|
T27 |
209 |
|
T30 |
8613 |
| auto[1] |
auto[1] |
auto[1] |
399329 |
1 |
|
|
T27 |
6 |
|
T30 |
1183 |
|
T34 |
138 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |