Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8364026 |
1 |
|
|
T26 |
50 |
|
T27 |
665 |
|
T28 |
405 |
| auto[1] |
6246995 |
1 |
|
|
T26 |
25 |
|
T27 |
546 |
|
T30 |
16898 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13813311 |
1 |
|
|
T26 |
74 |
|
T27 |
1191 |
|
T28 |
405 |
| auto[1] |
797710 |
1 |
|
|
T26 |
1 |
|
T27 |
20 |
|
T30 |
2093 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8349275 |
1 |
|
|
T26 |
58 |
|
T27 |
692 |
|
T28 |
405 |
| auto[1] |
6261746 |
1 |
|
|
T26 |
17 |
|
T27 |
519 |
|
T30 |
18093 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2729332 |
1 |
|
|
T26 |
4 |
|
T27 |
290 |
|
T30 |
8479 |
| auto[1] |
auto[0] |
auto[1] |
398474 |
1 |
|
|
T27 |
8 |
|
T30 |
1117 |
|
T34 |
162 |
| auto[1] |
auto[1] |
auto[0] |
2734704 |
1 |
|
|
T26 |
12 |
|
T27 |
209 |
|
T30 |
7521 |
| auto[1] |
auto[1] |
auto[1] |
399236 |
1 |
|
|
T26 |
1 |
|
T27 |
12 |
|
T30 |
976 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |