Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8352778 |
1 |
|
|
T26 |
40 |
|
T27 |
468 |
|
T28 |
405 |
| auto[1] |
6258243 |
1 |
|
|
T26 |
35 |
|
T27 |
743 |
|
T30 |
17459 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13817741 |
1 |
|
|
T26 |
75 |
|
T27 |
1192 |
|
T28 |
405 |
| auto[1] |
793280 |
1 |
|
|
T27 |
19 |
|
T30 |
1964 |
|
T34 |
180 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8382821 |
1 |
|
|
T26 |
61 |
|
T27 |
597 |
|
T28 |
405 |
| auto[1] |
6228200 |
1 |
|
|
T26 |
14 |
|
T27 |
614 |
|
T30 |
17585 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2703582 |
1 |
|
|
T26 |
10 |
|
T27 |
214 |
|
T30 |
8000 |
| auto[1] |
auto[0] |
auto[1] |
394743 |
1 |
|
|
T27 |
2 |
|
T30 |
1041 |
|
T34 |
90 |
| auto[1] |
auto[1] |
auto[0] |
2731338 |
1 |
|
|
T26 |
4 |
|
T27 |
381 |
|
T30 |
7621 |
| auto[1] |
auto[1] |
auto[1] |
398537 |
1 |
|
|
T27 |
17 |
|
T30 |
923 |
|
T34 |
90 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |