Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8373080 |
1 |
|
|
T26 |
53 |
|
T27 |
765 |
|
T28 |
405 |
| auto[1] |
6237941 |
1 |
|
|
T26 |
22 |
|
T27 |
446 |
|
T30 |
17838 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13812964 |
1 |
|
|
T26 |
75 |
|
T27 |
1188 |
|
T28 |
405 |
| auto[1] |
798057 |
1 |
|
|
T27 |
23 |
|
T30 |
2153 |
|
T34 |
218 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8347814 |
1 |
|
|
T26 |
59 |
|
T27 |
640 |
|
T28 |
405 |
| auto[1] |
6263207 |
1 |
|
|
T26 |
16 |
|
T27 |
571 |
|
T30 |
18706 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2730269 |
1 |
|
|
T26 |
11 |
|
T27 |
372 |
|
T30 |
8229 |
| auto[1] |
auto[0] |
auto[1] |
397388 |
1 |
|
|
T27 |
15 |
|
T30 |
1016 |
|
T34 |
94 |
| auto[1] |
auto[1] |
auto[0] |
2734881 |
1 |
|
|
T26 |
5 |
|
T27 |
176 |
|
T30 |
8324 |
| auto[1] |
auto[1] |
auto[1] |
400669 |
1 |
|
|
T27 |
8 |
|
T30 |
1137 |
|
T34 |
124 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |