Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8380888 |
1 |
|
|
T26 |
53 |
|
T27 |
779 |
|
T28 |
405 |
| auto[1] |
6230133 |
1 |
|
|
T26 |
22 |
|
T27 |
432 |
|
T30 |
17630 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12043844 |
1 |
|
|
T26 |
71 |
|
T27 |
1021 |
|
T28 |
405 |
| auto[1] |
2567177 |
1 |
|
|
T26 |
4 |
|
T27 |
190 |
|
T30 |
12487 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8370358 |
1 |
|
|
T26 |
52 |
|
T27 |
653 |
|
T28 |
405 |
| auto[1] |
6240663 |
1 |
|
|
T26 |
23 |
|
T27 |
558 |
|
T30 |
19763 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1849768 |
1 |
|
|
T26 |
11 |
|
T27 |
240 |
|
T30 |
3774 |
| auto[1] |
auto[0] |
auto[1] |
1291600 |
1 |
|
|
T26 |
4 |
|
T27 |
138 |
|
T30 |
6207 |
| auto[1] |
auto[1] |
auto[0] |
1823718 |
1 |
|
|
T26 |
8 |
|
T27 |
128 |
|
T30 |
3502 |
| auto[1] |
auto[1] |
auto[1] |
1275577 |
1 |
|
|
T27 |
52 |
|
T30 |
6280 |
|
T34 |
405 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |