Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13821431 |
1 |
|
|
T26 |
74 |
|
T27 |
1183 |
|
T28 |
405 |
| auto[1] |
789590 |
1 |
|
|
T26 |
1 |
|
T27 |
28 |
|
T30 |
1956 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8404024 |
1 |
|
|
T26 |
65 |
|
T27 |
511 |
|
T28 |
405 |
| auto[1] |
6206997 |
1 |
|
|
T26 |
10 |
|
T27 |
700 |
|
T30 |
17180 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2709397 |
1 |
|
|
T26 |
4 |
|
T27 |
255 |
|
T30 |
7549 |
| auto[1] |
auto[0] |
auto[1] |
396153 |
1 |
|
|
T26 |
1 |
|
T27 |
8 |
|
T30 |
946 |
| auto[1] |
auto[1] |
auto[0] |
2708010 |
1 |
|
|
T26 |
5 |
|
T27 |
417 |
|
T30 |
7675 |
| auto[1] |
auto[1] |
auto[1] |
393437 |
1 |
|
|
T27 |
20 |
|
T30 |
1010 |
|
T34 |
123 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |