Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8368233 |
1 |
|
|
T26 |
49 |
|
T27 |
520 |
|
T28 |
405 |
| auto[1] |
6242788 |
1 |
|
|
T26 |
26 |
|
T27 |
691 |
|
T30 |
18320 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12050251 |
1 |
|
|
T26 |
59 |
|
T27 |
1005 |
|
T28 |
405 |
| auto[1] |
2560770 |
1 |
|
|
T26 |
16 |
|
T27 |
206 |
|
T30 |
11238 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8381195 |
1 |
|
|
T26 |
57 |
|
T27 |
534 |
|
T28 |
405 |
| auto[1] |
6229826 |
1 |
|
|
T26 |
18 |
|
T27 |
677 |
|
T30 |
17761 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1841556 |
1 |
|
|
T26 |
1 |
|
T27 |
234 |
|
T30 |
3334 |
| auto[1] |
auto[0] |
auto[1] |
1285804 |
1 |
|
|
T26 |
14 |
|
T27 |
72 |
|
T30 |
5658 |
| auto[1] |
auto[1] |
auto[0] |
1827500 |
1 |
|
|
T26 |
1 |
|
T27 |
237 |
|
T30 |
3189 |
| auto[1] |
auto[1] |
auto[1] |
1274966 |
1 |
|
|
T26 |
2 |
|
T27 |
134 |
|
T30 |
5580 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |