Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8334828 |
1 |
|
|
T26 |
43 |
|
T27 |
632 |
|
T28 |
405 |
| auto[1] |
6276193 |
1 |
|
|
T26 |
32 |
|
T27 |
579 |
|
T30 |
18398 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12044982 |
1 |
|
|
T26 |
72 |
|
T27 |
1071 |
|
T28 |
405 |
| auto[1] |
2566039 |
1 |
|
|
T26 |
3 |
|
T27 |
140 |
|
T30 |
10883 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8363741 |
1 |
|
|
T26 |
55 |
|
T27 |
754 |
|
T28 |
405 |
| auto[1] |
6247280 |
1 |
|
|
T26 |
20 |
|
T27 |
457 |
|
T30 |
17500 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1825324 |
1 |
|
|
T26 |
5 |
|
T27 |
177 |
|
T30 |
3321 |
| auto[1] |
auto[0] |
auto[1] |
1280316 |
1 |
|
|
T26 |
1 |
|
T27 |
99 |
|
T30 |
5459 |
| auto[1] |
auto[1] |
auto[0] |
1855917 |
1 |
|
|
T26 |
12 |
|
T27 |
140 |
|
T30 |
3296 |
| auto[1] |
auto[1] |
auto[1] |
1285723 |
1 |
|
|
T26 |
2 |
|
T27 |
41 |
|
T30 |
5424 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |