Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8369272 |
1 |
|
|
T26 |
26 |
|
T27 |
752 |
|
T28 |
405 |
| auto[1] |
6241749 |
1 |
|
|
T26 |
49 |
|
T27 |
459 |
|
T30 |
18144 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12046710 |
1 |
|
|
T26 |
72 |
|
T27 |
1069 |
|
T28 |
405 |
| auto[1] |
2564311 |
1 |
|
|
T26 |
3 |
|
T27 |
142 |
|
T30 |
10654 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8359330 |
1 |
|
|
T26 |
61 |
|
T27 |
612 |
|
T28 |
405 |
| auto[1] |
6251691 |
1 |
|
|
T26 |
14 |
|
T27 |
599 |
|
T30 |
16546 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1846066 |
1 |
|
|
T27 |
307 |
|
T30 |
2911 |
|
T34 |
345 |
| auto[1] |
auto[0] |
auto[1] |
1286428 |
1 |
|
|
T27 |
115 |
|
T30 |
5355 |
|
T34 |
376 |
| auto[1] |
auto[1] |
auto[0] |
1841314 |
1 |
|
|
T26 |
11 |
|
T27 |
150 |
|
T30 |
2981 |
| auto[1] |
auto[1] |
auto[1] |
1277883 |
1 |
|
|
T26 |
3 |
|
T27 |
27 |
|
T30 |
5299 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |